lw

cpu.gprj

@@ -6,6 +6,7 @@
     <Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
     <FileList>
         <File path="src/core.v" type="file.verilog" enable="1"/>
+        <File path="src/defs.vh" type="file.verilog" enable="1"/>
         <File path="src/memory.v" type="file.verilog" enable="1"/>
         <File path="src/top.v" type="file.verilog" enable="1"/>
         <File path="src/uart.v" type="file.verilog" enable="1"/>

impl/gwsynthesis/cpu.log

@@ -4,14 +4,18 @@ Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\memory.v'
 Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\top.v'
 Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\uart.v'
 Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\core.v'
+Analyzing included file 'C:\Users\kuroc\Downloads\cpu\src\defs.vh'("C:\Users\kuroc\Downloads\cpu\src\core.v":1)
+Back to file 'C:\Users\kuroc\Downloads\cpu\src\core.v'("C:\Users\kuroc\Downloads\cpu\src\core.v":1)
+Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\defs.vh'
 Compiling module 'TOP'("C:\Users\kuroc\Downloads\cpu\src\top.v":1)
 Compiling module 'UART'("C:\Users\kuroc\Downloads\cpu\src\uart.v":1)
 WARN  (EX3791) : Expression size 5 truncated to fit in target size 4("C:\Users\kuroc\Downloads\cpu\src\uart.v":98)
 Compiling module 'MEMORY'("C:\Users\kuroc\Downloads\cpu\src\memory.v":1)
 Extracting RAM for identifier 'mem'("C:\Users\kuroc\Downloads\cpu\src\memory.v":13)
-Compiling module 'CORE'("C:\Users\kuroc\Downloads\cpu\src\core.v":1)
+WARN  (EX3784) : Index 33 is out of range [32:0] for 'mem'("C:\Users\kuroc\Downloads\cpu\src\memory.v":19)
-Extracting RAM for identifier 'register'("C:\Users\kuroc\Downloads\cpu\src\core.v":17)
+Compiling module 'CORE'("C:\Users\kuroc\Downloads\cpu\src\core.v":3)
-WARN  (EX3791) : Expression size 32 truncated to fit in target size 21("C:\Users\kuroc\Downloads\cpu\src\core.v":102)
+Extracting RAM for identifier 'register'("C:\Users\kuroc\Downloads\cpu\src\core.v":19)
+WARN  (EX3791) : Expression size 32 truncated to fit in target size 21("C:\Users\kuroc\Downloads\cpu\src\core.v":101)
 NOTE  (EX0101) : Current top module is "TOP"
 [5%] Running netlist conversion ...
 Running device independent optimization ...

impl/gwsynthesis/cpu.prj

@@ -8,6 +8,7 @@
         <File path="C:\Users\kuroc\Downloads\cpu\src\top.v" type="verilog"/>
         <File path="C:\Users\kuroc\Downloads\cpu\src\uart.v" type="verilog"/>
         <File path="C:\Users\kuroc\Downloads\cpu\src\core.v" type="verilog"/>
+        <File path="C:\Users\kuroc\Downloads\cpu\src\defs.vh" type="verilog"/>
     </FileList>
     <OptionList>
         <Option type="disable_insert_pad" value="0"/>

impl/gwsynthesis/cpu_syn_resource.html

@@ -39,29 +39,29 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 </tr>
 <td class="label">&nbsp&nbsp&nbsp&nbsp|--uart0
  (C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
-<td align = "center">52</td>
+<td align = "center">58</td>
 <td align = "center">31</td>
-<td align = "center">36</td>
+<td align = "center">39</td>
 <td align = "center">-</td>
 <td align = "center">-</td>
 <td align = "center">-</td>
 </tr>
 <td class="label">&nbsp&nbsp&nbsp&nbsp|--mem0
  (C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
-<td align = "center">156</td>
+<td align = "center">512</td>
-<td align = "center">-</td>
+<td align = "center">78</td>
-<td align = "center">931</td>
+<td align = "center">4036</td>
 <td align = "center">-</td>
 <td align = "center">-</td>
 <td align = "center">-</td>
 </tr>
 <td class="label">&nbsp&nbsp&nbsp&nbsp|--core0
  (C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
-<td align = "center">92</td>
+<td align = "center">185</td>
-<td align = "center">7</td>
+<td align = "center">62</td>
-<td align = "center">27</td>
+<td align = "center">125</td>
-<td align = "center">-</td>
 <td align = "center">-</td>
+<td align = "center">2</td>
 <td align = "center">-</td>
 </tr>
 </table>

impl/gwsynthesis/cpu_syn_rsc.xml

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <Module name="TOP">
-    <SubModule name="uart0" Register="52" Alu="31" Lut="36"/>
+    <SubModule name="uart0" Register="58" Alu="31" Lut="39"/>
-    <SubModule name="mem0" Register="156" Lut="931"/>
+    <SubModule name="mem0" Register="512" Alu="78" Lut="4036"/>
-    <SubModule name="core0" Register="92" Alu="7" Lut="27"/>
+    <SubModule name="core0" Register="185" Alu="62" Lut="125" Bsram="2"/>
 </Module>

impl/pnr/cpu.log

@@ -25,5 +25,5 @@ Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.pin.html" completed
 Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.rpt.html" completed
 Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.rpt.txt" completed
 Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.tr.html" completed
-Thu May 18 11:35:38 2023
+Thu May 18 14:32:04 2023
 

impl/pnr/cpu.pin.html

@@ -74,7 +74,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Created Time</td>
-<td>Thu May 18 11:35:38 2023
+<td>Thu May 18 14:32:04 2023
 </td>
 </tr>
 <tr>

impl/pnr/cpu.power.html

@@ -83,7 +83,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Created Time</td>
-<td>Thu May 18 11:35:38 2023
+<td>Thu May 18 14:32:04 2023
 </td>
 </tr>
 <tr>
@@ -96,7 +96,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 <table class="summary_table">
 <tr>
 <td class="label">Total Power (mW)</td>
-<td>163.969</td>
+<td>200.003</td>
 </tr>
 <tr>
 <td class="label">Quiescent Power (mW)</td>
@@ -104,14 +104,14 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Dynamic Power (mW)</td>
-<td>3.540</td>
+<td>39.574</td>
 </tr>
 </table>
 <h2><a name="Thermal_Info">Thermal Information:</a></h2>
 <table class="summary_table">
 <tr>
 <td class="label">Junction Temperature</td>
-<td>30.250</td>
+<td>31.404</td>
 </tr>
 <tr>
 <td class="label">Theta JA</td>
@@ -119,7 +119,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Max Allowed Ambient Temperature</td>
-<td>79.750</td>
+<td>78.596</td>
 </tr>
 </table>
 <h2><a name="Configure_Info">Configure Information:</a></h2>
@@ -188,9 +188,9 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 <tr>
 <td>VCC</td>
 <td>1.000</td>
-<td>1.873</td>
+<td>37.908</td>
 <td>101.834</td>
-<td>103.707</td>
+<td>139.742</td>
 </tr>
 <tr>
 <td>VCCX</td>
@@ -225,7 +225,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td>Logic</td>
-<td>1.432</td>
+<td>5.586</td>
 <td>NA</td>
 <td>12.500</td>
 </tr>
@@ -235,6 +235,12 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 <td>0.550
 <td>41.667
 </tr>
+<tr>
+<td>BSRAM</td>
+<td>31.860
+<td>NA</td>
+<td>NA</td>
+</tr>
 </table>
 <h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
 <table class="detail_table">
@@ -245,20 +251,20 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td>TOP</td>
-<td>1.432</td>
+<td>37.446</td>
-<td>1.432(1.432)</td>
+<td>37.446(37.446)</td>
 <tr>
 <td>TOP/core0/</td>
-<td>0.126</td>
+<td>32.569</td>
-<td>0.126(0.000)</td>
+<td>32.569(0.000)</td>
 <tr>
 <td>TOP/mem0/</td>
-<td>1.003</td>
+<td>4.567</td>
-<td>1.003(0.000)</td>
+<td>4.567(0.000)</td>
 <tr>
 <td>TOP/uart0/</td>
-<td>0.303</td>
+<td>0.309</td>
-<td>0.303(0.000)</td>
+<td>0.309(0.000)</td>
 </table>
 <h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
 <table class="detail_table">
@@ -270,7 +276,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 <tr>
 <td>clock</td>
 <td>100.000</td>
-<td>1.439</td>
+<td>37.473</td>
 </tr>
 </table>
 </div><!-- content -->

impl/pnr/cpu.rpt.html

@@ -79,7 +79,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Created Time</td>
-<td>Thu May 18 11:35:38 2023
+<td>Thu May 18 14:32:04 2023
 </td>
 </tr>
 <tr>
@@ -93,23 +93,23 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 <tr>
 <td class="label">Place & Route Process</td>
 <td>Running placement:
-   Placement Phase 0: CPU time = 0h 0m 0.054s, Elapsed time = 0h 0m 0.055s
+   Placement Phase 0: CPU time = 0h 0m 0.329s, Elapsed time = 0h 0m 0.33s
-   Placement Phase 1: CPU time = 0h 0m 0.297s, Elapsed time = 0h 0m 0.296s
+   Placement Phase 1: CPU time = 0h 0m 0.575s, Elapsed time = 0h 0m 0.575s
-   Placement Phase 2: CPU time = 0h 0m 0.092s, Elapsed time = 0h 0m 0.092s
+   Placement Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
-   Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
+   Placement Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s
-   Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
+   Total Placement: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s
 Running routing:
-   Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s
+   Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
-   Routing Phase 1: CPU time = 0h 0m 0.153s, Elapsed time = 0h 0m 0.153s
+   Routing Phase 1: CPU time = 0h 0m 0.229s, Elapsed time = 0h 0m 0.229s
-   Routing Phase 2: CPU time = 0h 0m 0.926s, Elapsed time = 0h 0m 0.926s
+   Routing Phase 2: CPU time = 0h 0m 32s, Elapsed time = 0h 0m 32s
-   Total Routing: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
+   Total Routing: CPU time = 0h 0m 33s, Elapsed time = 0h 0m 33s
 Generate output files:
-   CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
+   CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
 </td>
 </tr>
 <tr>
 <td class="label">Total Time and Memory Usage</td>
-<td>CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 317MB</td>
+<td>CPU time = 0h 0m 47s, Elapsed time = 0h 0m 47s, Peak memory usage = 370MB</td>
 </tr>
 </table>
 <br/>
@@ -124,12 +124,12 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">Logic</td>
-<td>1034/20736</td>
+<td>4382/20736</td>
-<td>4%</td>
+<td>21%</td>
 </tr>
 <tr>
 <td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
-<td>1034(994 LUT, 40 ALU, 0 ROM16)</td>
+<td>4382(4200 LUT, 182 ALU, 0 ROM16)</td>
 <td>-</td>
 </tr>
 <tr>
@@ -139,8 +139,8 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">Register</td>
-<td>300/16173</td>
+<td>755/16173</td>
-<td>1%</td>
+<td>4%</td>
 </tr>
 <tr>
 <td class="label">&nbsp &nbsp --Logic Register as Latch</td>
@@ -149,8 +149,8 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">&nbsp &nbsp --Logic Register as FF</td>
-<td>300/15552</td>
+<td>755/15552</td>
-<td>1%</td>
+<td>4%</td>
 </tr>
 <tr>
 <td class="label">&nbsp &nbsp --I/O Register as Latch</td>
@@ -164,8 +164,8 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">CLS</td>
-<td>612/10368</td>
+<td>2410/10368</td>
-<td>5%</td>
+<td>23%</td>
 </tr>
 <tr>
 <td class="label">I/O Port</td>
@@ -199,8 +199,8 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">BSRAM</td>
-<td>0</td>
+<td>2 SDPB<br/></td>
-<td>0%</td>
+<td>4%</td>
 </tr>
 <tr>
 <td class="label">DSP</td>
@@ -329,7 +329,7 @@ Generate output files:
 <tr>
 <td class="label">clock_d</td>
 <td>PRIMARY</td>
-<td> TR</td>
+<td> TR TL BR BL</td>
 </tr>
 </table>
 <br/>

impl/pnr/cpu.rpt.txt

@@ -11,26 +11,26 @@
   <PnR Version>: V1.9.8.09 Education
   <Part Number>: GW2A-LV18PG256C8/I7
   <Device>: GW2A-18C
-  <Created Time>:Thu May 18 11:35:38 2023
+  <Created Time>:Thu May 18 14:32:04 2023
 
 
 2. PnR Details
 
   Running placement:
-    Placement Phase 0: CPU time = 0h 0m 0.054s, Elapsed time = 0h 0m 0.055s
+    Placement Phase 0: CPU time = 0h 0m 0.329s, Elapsed time = 0h 0m 0.33s
-    Placement Phase 1: CPU time = 0h 0m 0.297s, Elapsed time = 0h 0m 0.296s
+    Placement Phase 1: CPU time = 0h 0m 0.575s, Elapsed time = 0h 0m 0.575s
-    Placement Phase 2: CPU time = 0h 0m 0.092s, Elapsed time = 0h 0m 0.092s
+    Placement Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
-    Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
+    Placement Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s
-    Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
+    Total Placement: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s
  Running routing:
-    Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s
+    Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
-    Routing Phase 1: CPU time = 0h 0m 0.153s, Elapsed time = 0h 0m 0.153s
+    Routing Phase 1: CPU time = 0h 0m 0.229s, Elapsed time = 0h 0m 0.229s
-    Routing Phase 2: CPU time = 0h 0m 0.926s, Elapsed time = 0h 0m 0.926s
+    Routing Phase 2: CPU time = 0h 0m 32s, Elapsed time = 0h 0m 32s
-    Total Routing: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
+    Total Routing: CPU time = 0h 0m 33s, Elapsed time = 0h 0m 33s
  Generate output files:
-    CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
+    CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
 
- Total Time and Memory Usage: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 317MB
+ Total Time and Memory Usage: CPU time = 0h 0m 47s, Elapsed time = 0h 0m 47s, Peak memory usage = 370MB
 
 
 3. Resource Usage Summary
@@ -38,22 +38,23 @@
   ----------------------------------------------------------
   Resources                   | Usage
   ----------------------------------------------------------
-  Logic                       | 1034/20736  4%
+  Logic                       | 4382/20736  21%
-    --LUT,ALU,ROM16           | 1034(994 LUT, 40 ALU, 0 ROM16)
+    --LUT,ALU,ROM16           | 4382(4200 LUT, 182 ALU, 0 ROM16)
     --SSRAM(RAM16)            | 0
-  Register                    | 300/16173  1%
+  Register                    | 755/16173  4%
     --Logic Register as Latch | 0/15552  0%
-    --Logic Register as FF    | 300/15552  1%
+    --Logic Register as FF    | 755/15552  4%
     --I/O Register as Latch   | 0/621  0%
     --I/O Register as FF      | 0/621  0%
-  CLS                         | 612/10368  5%
+  CLS                         | 2410/10368  23%
   I/O Port                    | 3
   I/O Buf                     | 3
     --Input Buf               | 1
     --Output Buf              | 2
     --Inout Buf               | 0
   IOLOGIC                     | 0%
-  BSRAM                       | 0%
+  BSRAM                       | 4%
+    --SDPB                    | 2
   DSP                         | 0%
   PLL                         | 0/4  0%
   DCS                         | 0/8  0%
@@ -102,7 +103,7 @@
   -------------------------------------------
   Signal         | Global Clock   | Location
   -------------------------------------------
-  clock_d        | PRIMARY        |  TR
+  clock_d        | PRIMARY        |  TR TL BR BL
   ===========================================
 
 

impl/pnr/cpu_tr_cata.html

@@ -31,7 +31,7 @@ function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.
 <ul>
 <li><div class="triangle_fake"></div><a href="cpu_tr_content.html#STA_Tool_Run_Summary" style=" font-size: 14px;" target="mainFrame">STA Tool Run Summary</a></li>
 <li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Clock_Report" style=" font-size: 14px;" target="mainFrame">Clock Summary</a></li>
-<li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;" target="mainFrame">Max Frequency Summary</a></li>
+<li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;color: #FF0000;" target="mainFrame">Max Frequency Summary</a></li>
 <li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Total_Negative_Slack_Report" style=" font-size: 14px;" target="mainFrame">Total Negative Slack Summary</a></li>
 </ul>
 </li>
@@ -43,7 +43,7 @@ function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.
 <li><div class="triangle" onclick="onClick(this)"></div><a href="cpu_tr_content.html#All_Path_Slack_Table" style=" font-size: 14px;" target="mainFrame">Path Slacks Table</a>
 <ul>
 <!--Setup_Slack_Table begin-->
-<li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;" target="mainFrame">Setup Paths Table</a>
+<li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;color: #FF0000;" target="mainFrame">Setup Paths Table</a>
 </li>
 <!--Setup_Slack_Table end-->
 <!--Hold_Slack_Table begin-->

impl/temp/rtl_parser.result

@@ -28,7 +28,7 @@
     "InstLine" : 36,
     "InstName" : "core0",
     "ModuleFile" : "C:/Users/kuroc/Downloads/cpu/src/core.v",
-    "ModuleLine" : 1,
+    "ModuleLine" : 3,
     "ModuleName" : "CORE"
    }
   ]

impl/temp/rtl_parser_arg.json

@@ -15,6 +15,10 @@
   {
    "Path" : "C:/Users/kuroc/Downloads/cpu/src/core.v",
    "Type" : "verilog"
+  },
+  {
+   "Path" : "C:/Users/kuroc/Downloads/cpu/src/defs.vh",
+   "Type" : "verilog"
   }
  ],
  "IncludePath" : [

src/core.v

@@ -1,3 +1,5 @@
+`include "defs.vh"
+
 module CORE(
     input clock,
 
@@ -39,9 +41,9 @@ module CORE(
     wire [31:0] rs2_data;
 
     reg [11:0] i_imm;
-    reg [31:0] i_imm_sext;
+    wire [31:0] i_imm_sext;
     reg [11:0] s_imm;
-    reg [31:0] s_imm_sext;
+    wire [31:0] s_imm_sext;
     reg [12:0] b_imm;
     reg [31:0] u_imm;
     reg [20:0] j_imm;
@@ -78,7 +80,6 @@ module CORE(
                 reg_tx_start <= 1;
                 reg_tx_data <= rdata[31:24];
                 REGISTER_TEST <= register[1][31:0];
-                reg_iaddr <= pc;
                 reg_inst <= inst;
                 pc_p4 <= pc + 4;
 
@@ -94,9 +95,7 @@ module CORE(
                 funct7 = reg_inst[25+:7];
 
                 i_imm <= reg_inst[20+:12];
-                i_imm_sext <= { {20{i_imm[11]}}, i_imm[10:0] };
                 s_imm <= { reg_inst[31:25], reg_inst[11:7] };
-                s_imm_sext <= { {20{s_imm[11]}}, s_imm[10:0] };
                 b_imm = { reg_inst[25+:7], reg_inst[7+:5] };
                 u_imm[31:12] = reg_inst[31:12];
                 j_imm = {{12{reg_inst[31]}}, reg_inst[19:12], reg_inst[20], reg_inst[30:25], reg_inst[24:21], 1'b0};
@@ -106,23 +105,33 @@ module CORE(
 
             ST_EX: begin
 
-                alu_out = rs1_data + s_imm;
+                case (opcode)
+                    `OP_SW:
+                        alu_out = rs1_data + s_imm_sext;
+                    `OP_LW:
+                        alu_out = rs1_data + i_imm_sext;
+                endcase
 
                 stage <= ST_ACCESS;
             end
 
             ST_ACCESS: begin
                 reg_raddr = alu_out;
-                reg_wen = opcode == 7'b0100011;
+                reg_wen = opcode == `OP_SW;
                 reg_wdata = rs2_data;
 
                 stage <= ST_WB;
             end
 
             ST_WB: begin
-                pc <= pc_p4;
+
-                reg_wen <= 0;
+                if (opcode == `OP_LW)
-                reg_raddr = 4;
+                    register[rd] <= rdata;
+
+                pc = pc_p4;
+                alu_out = 0;
+                reg_wen = 0;
+                reg_iaddr = pc_p4;
 
                 stage <= ST_IF;
             end
@@ -132,6 +141,9 @@ module CORE(
     assign rs1_data = register[rs1];
     assign rs2_data = register[rs2];
 
+    assign i_imm_sext = { {20{i_imm[11]}}, i_imm[10:0] };
+    assign s_imm_sext = { {20{s_imm[11]}}, s_imm[10:0] };
+
     assign tx_start = reg_tx_start;
     assign tx_data = reg_tx_data;
 

src/defs.vh

@@ -0,0 +1,2 @@
+`define OP_SW 7'b0100011
+`define OP_LW 7'b0000011

src/memory.v

@@ -10,7 +10,7 @@ module MEMORY(
     output [31:0] rdata
 );
 
-    reg [7:0] mem [512:0];
+    reg [7:0] mem [32:0];
     
     reg [31:0] reg_raddr;