Files
tangprimer-riscv/impl/gwsynthesis/cpu_syn_rsc.xml
2023-05-18 14:53:59 +09:00

7 lines
269 B
XML

<?xml version="1.0" encoding="UTF-8"?>
<Module name="TOP">
<SubModule name="uart0" Register="58" Alu="31" Lut="39"/>
<SubModule name="mem0" Register="512" Alu="78" Lut="4036"/>
<SubModule name="core0" Register="185" Alu="62" Lut="125" Bsram="2"/>
</Module>