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https://github.com/mii443/tangprimer-riscv.git
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23884 lines
378 KiB
HTML
23884 lines
378 KiB
HTML
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html>
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<head>
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<title>Timing Analysis Report</title>
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<style type="text/css">
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body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
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div#content { width: 100%; margin: }
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hr { margin-top: 30px; margin-bottom: 30px; }
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h1, h3 { text-align: center; }
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h1 {margin-top: 50px; }
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table, th, td {white-space:pre; border: 1px solid #aaa; }
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table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
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th, td { padding: 5px 5px 5px 5px; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
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table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
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table.detail_table th.label { min-width: 8%; width: 8%; }
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</style>
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</head>
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<body>
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<div id="content">
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<h1><a name="Message">Timing Messages</a></h1>
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<table class="summary_table">
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<tr>
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<td class="label">Report Title</td>
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<td>Timing Analysis Report</td>
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</tr>
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<tr>
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<td class="label">Design File</td>
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<td>C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg</td>
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</tr>
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<tr>
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<td class="label">Physical Constraints File</td>
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<td>C:\Users\kuroc\Downloads\cpu\src\cpu.cst</td>
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</tr>
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<tr>
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<td class="label">Timing Constraint File</td>
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<td>---</td>
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</tr>
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<tr>
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<td class="label">Version</td>
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<td>V1.9.8.09 Education</td>
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</tr>
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<tr>
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<td class="label">Part Number</td>
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<td>GW2A-LV18PG256C8/I7</td>
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</tr>
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<tr>
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<td class="label">Device</td>
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<td>GW2A-18C</td>
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Thu May 18 14:32:04 2023
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</td>
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</tr>
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<tr>
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<td class="label">Legal Announcement</td>
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<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
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</tr>
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</table>
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<h1><a name="Summary">Timing Summaries</a></h1>
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<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
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<table class="summary_table">
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<tr>
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<td class="label">Setup Delay Model</td>
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<td>Slow 0.95V 85C C8/I7</td>
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</tr>
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<tr>
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<td class="label">Hold Delay Model</td>
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<td>Fast 1.05V 0C C8/I7</td>
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</tr>
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<tr>
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<td class="label">Numbers of Paths Analyzed</td>
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<td>1619</td>
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</tr>
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<tr>
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<td class="label">Numbers of Endpoints Analyzed</td>
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<td>1590</td>
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</tr>
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<tr>
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<td class="label">Numbers of Falling Endpoints</td>
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<td>0</td>
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</tr>
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<tr>
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<td class="label">Numbers of Setup Violated Endpoints</td>
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<td>1027</td>
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</tr>
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<tr>
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<td class="label">Numbers of Hold Violated Endpoints</td>
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<td>0</td>
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</tr>
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</table>
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<h2><a name="Clock_Report">Clock Summary:</a></h2>
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<table class="detail_table">
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<tr>
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<th class="label">Clock Name</th>
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<th class="label">Type</th>
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<th class="label">Period</th>
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<th class="label">Frequency(MHz)</th>
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<th class="label">Rise</th>
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<th class="label">Fall</th>
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<th class="label">Source</th>
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<th class="label">Master</th>
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<th class="label">Objects</th>
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</tr>
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<tr>
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<td>clock</td>
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<td>Base</td>
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<td>10.000</td>
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<td>100.000
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<td>0.000</td>
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<td>5.000</td>
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<td></td>
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<td></td>
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<td>clock_ibuf/I </td>
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</tr>
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</table>
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<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
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<table>
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<tr>
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<th>NO.</th>
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<th>Clock Name</th>
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<th>Constraint</th>
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<th>Actual Fmax</th>
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<th>Logic Level</th>
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<th>Entity</th>
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</tr>
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<tr>
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<td>1</td>
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<td>clock</td>
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<td>100.000(MHz)</td>
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<td style="color: #FF0000;">68.477(MHz)</td>
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<td>13</td>
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<td>TOP</td>
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</tr>
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</table>
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<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
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<table class="detail_table">
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<tr>
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<th class="label">Clock Name</th>
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<th class="label">Analysis Type</th>
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<th class="label">Endpoints TNS</th>
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<th class="label">Number of Endpoints</th>
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</tr>
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<tr>
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<td>clock</td>
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<td>Setup</td>
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<td>-3052.220</td>
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<td>1027</td>
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</tr>
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<tr>
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<td>clock</td>
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<td>Hold</td>
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<td>0.000</td>
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<td>0</td>
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</tr>
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</table>
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<h1><a name="Detail">Timing Details</a></h1>
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<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
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<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
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<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
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<table class="detail_table">
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<tr>
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<th class="label">Path Number</th>
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<th class="label">Path Slack</th>
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<th class="label">From Node</th>
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<th class="label">To Node</th>
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<th class="label">From Clock</th>
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<th class="label">To Clock</th>
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<th class="label">Relation</th>
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<th class="label">Clock Skew</th>
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<th class="label">Data Delay</th>
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</tr>
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<tr style="color: #FF0000;">
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<td>1</td>
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<td>-4.604</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_15_G[7]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.569</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>2</td>
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<td>-4.604</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_15_G[6]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.569</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>3</td>
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<td>-4.604</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_15_G[5]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.569</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>4</td>
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<td>-4.604</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_15_G[2]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.569</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>5</td>
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<td>-4.604</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_15_G[1]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.569</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>6</td>
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<td>-4.604</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_15_G[0]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.569</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>7</td>
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<td>-4.537</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_24_G[2]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.502</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>8</td>
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<td>-4.482</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_18_G[5]_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.447</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>9</td>
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<td>-4.448</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_18_G[5]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.413</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>10</td>
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<td>-4.448</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_18_G[1]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.413</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>11</td>
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<td>-4.434</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_19_G[6]_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.399</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>12</td>
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<td>-4.395</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_24_G[1]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.360</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>13</td>
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<td>-4.315</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_30_G[1]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.280</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>14</td>
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<td>-4.291</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_44_G[3]_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.256</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>15</td>
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<td>-4.262</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_51_G[7]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.227</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>16</td>
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<td>-4.262</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_51_G[3]_s0/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>14.227</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>17</td>
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<td>-4.258</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_51_G[5]_s0/CE</td>
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<td>clock:[R]</td>
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|
<td>clock:[R]</td>
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|
<td>10.000</td>
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|
<td>0.000</td>
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<td>14.223</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>18</td>
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<td>-4.254</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_22_G[0]_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>14.219</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>19</td>
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<td>-4.249</td>
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<td>core0/reg_raddr_4_s0/Q</td>
|
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<td>mem0/mem_mem_RAMREG_40_G[7]_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
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|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>14.214</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>20</td>
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<td>-4.226</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_13_G[5]_s0/CE</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>14.191</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>21</td>
|
|
<td>-4.226</td>
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|
<td>core0/reg_raddr_4_s0/Q</td>
|
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<td>mem0/mem_mem_RAMREG_13_G[3]_s0/CE</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>14.191</td>
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</tr>
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<tr style="color: #FF0000;">
|
|
<td>22</td>
|
|
<td>-4.226</td>
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|
<td>core0/reg_raddr_4_s0/Q</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[0]_s0/CE</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>14.191</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>23</td>
|
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<td>-4.204</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_15_G[4]_s0/CE</td>
|
|
<td>clock:[R]</td>
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|
<td>clock:[R]</td>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
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<td>14.169</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>24</td>
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<td>-4.198</td>
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<td>core0/reg_raddr_4_s0/Q</td>
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<td>mem0/mem_mem_RAMREG_51_G[6]_s0/CE</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>14.163</td>
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</tr>
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<tr style="color: #FF0000;">
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<td>25</td>
|
|
<td>-4.185</td>
|
|
<td>core0/reg_raddr_4_s0/Q</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[5]_s0/CE</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>14.150</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">Path Number</th>
|
|
<th class="label">Path Slack</th>
|
|
<th class="label">From Node</th>
|
|
<th class="label">To Node</th>
|
|
<th class="label">From Clock</th>
|
|
<th class="label">To Clock</th>
|
|
<th class="label">Relation</th>
|
|
<th class="label">Clock Skew</th>
|
|
<th class="label">Data Delay</th>
|
|
</tr>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>0.346</td>
|
|
<td>core0/rs2_4_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/ADB[9]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.464</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2</td>
|
|
<td>0.359</td>
|
|
<td>core0/rd_0_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/ADA[5]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.477</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_0_s1/Q</td>
|
|
<td>core0/alu_out_0_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_3_s1/Q</td>
|
|
<td>core0/alu_out_3_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_5_s1/Q</td>
|
|
<td>core0/alu_out_5_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_6_s1/Q</td>
|
|
<td>core0/alu_out_6_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_7_s1/Q</td>
|
|
<td>core0/alu_out_7_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_9_s1/Q</td>
|
|
<td>core0/alu_out_9_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_11_s1/Q</td>
|
|
<td>core0/alu_out_11_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_12_s1/Q</td>
|
|
<td>core0/alu_out_12_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_13_s1/Q</td>
|
|
<td>core0/alu_out_13_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_14_s1/Q</td>
|
|
<td>core0/alu_out_14_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_23_s1/Q</td>
|
|
<td>core0/alu_out_23_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_25_s1/Q</td>
|
|
<td>core0/alu_out_25_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15</td>
|
|
<td>0.425</td>
|
|
<td>core0/alu_out_27_s1/Q</td>
|
|
<td>core0/alu_out_27_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16</td>
|
|
<td>0.425</td>
|
|
<td>uart0/led_flag_s1/Q</td>
|
|
<td>uart0/led_flag_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>17</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_2_s0/Q</td>
|
|
<td>uart0/clock_count_2_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_6_s0/Q</td>
|
|
<td>uart0/clock_count_6_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>19</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_8_s0/Q</td>
|
|
<td>uart0/clock_count_8_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_12_s0/Q</td>
|
|
<td>uart0/clock_count_12_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_14_s0/Q</td>
|
|
<td>uart0/clock_count_14_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_18_s0/Q</td>
|
|
<td>uart0/clock_count_18_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_20_s0/Q</td>
|
|
<td>uart0/clock_count_20_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_24_s0/Q</td>
|
|
<td>uart0/clock_count_24_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_26_s0/Q</td>
|
|
<td>uart0/clock_count_26_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>Nothing to report!</h4>
|
|
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>Nothing to report!</h4>
|
|
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">Number</th>
|
|
<th class="label">Slack</th>
|
|
<th class="label">Actual Width</th>
|
|
<th class="label">Required Width</th>
|
|
<th class="label">Type</th>
|
|
<th class="label">Clock</th>
|
|
<th class="label">Objects</th>
|
|
</tr>
|
|
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_30_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_28_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_16_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_0_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>mem0/mem_mem_RAMREG_0_G[4]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>mem0/mem_mem_RAMREG_8_G[4]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[4]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>mem0/mem_mem_RAMREG_56_G[4]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>mem0/mem_mem_RAMREG_56_G[3]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
|
|
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
|
<h3>Path1</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.604</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.494</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[7]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.531</td>
|
|
<td>2.002</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td>mem0/mem_s5264/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.086</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5264/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.623</td>
|
|
<td>0.537</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td>mem0/mem_s5923/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.193</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5923/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.195</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td>mem0/mem_s4983/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.765</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4983/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.494</td>
|
|
<td>0.730</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C36[1][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_15_G[7]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C36[1][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[7]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C36[1][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[7]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path2</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.604</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.494</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[6]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.531</td>
|
|
<td>2.002</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td>mem0/mem_s5264/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.086</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5264/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.623</td>
|
|
<td>0.537</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td>mem0/mem_s5923/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.193</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5923/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.195</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td>mem0/mem_s4983/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.765</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4983/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.494</td>
|
|
<td>0.730</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C35[0][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_15_G[6]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C35[0][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[6]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C35[0][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[6]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path3</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.604</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.494</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[5]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.531</td>
|
|
<td>2.002</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td>mem0/mem_s5264/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.086</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5264/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.623</td>
|
|
<td>0.537</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td>mem0/mem_s5923/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.193</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5923/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.195</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td>mem0/mem_s4983/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.765</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4983/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.494</td>
|
|
<td>0.730</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C35[0][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_15_G[5]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C35[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[5]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C35[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[5]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path4</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.604</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.494</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[2]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.531</td>
|
|
<td>2.002</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td>mem0/mem_s5264/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.086</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5264/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.623</td>
|
|
<td>0.537</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td>mem0/mem_s5923/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.193</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5923/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.195</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td>mem0/mem_s4983/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.765</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4983/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.494</td>
|
|
<td>0.730</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C36[0][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_15_G[2]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C36[0][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[2]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C36[0][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[2]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path5</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.604</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.494</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[1]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.531</td>
|
|
<td>2.002</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td>mem0/mem_s5264/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.086</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5264/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.623</td>
|
|
<td>0.537</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td>mem0/mem_s5923/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.193</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5923/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.195</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td>mem0/mem_s4983/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.765</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4983/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.494</td>
|
|
<td>0.730</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C36[0][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_15_G[1]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C36[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[1]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C36[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[1]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path6</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.604</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.494</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[0]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.531</td>
|
|
<td>2.002</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td>mem0/mem_s5264/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.086</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5264/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.623</td>
|
|
<td>0.537</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td>mem0/mem_s5923/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.193</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5923/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.195</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td>mem0/mem_s4983/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.765</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4983/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.494</td>
|
|
<td>0.730</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C35[1][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_15_G[0]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C35[1][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[0]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C35[1][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[0]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path7</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.537</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.428</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[2]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.252</td>
|
|
<td>0.722</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C24[1][B]</td>
|
|
<td>mem0/mem_s5401/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.769</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R15C24[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5401/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.705</td>
|
|
<td>1.936</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C27[3][A]</td>
|
|
<td>mem0/mem_s5937/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.275</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C27[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5937/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.276</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C27[3][B]</td>
|
|
<td>mem0/mem_s4992/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.738</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R32C27[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4992/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.428</td>
|
|
<td>0.690</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C25[2][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_24_G[2]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C25[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[2]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R29C25[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[2]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.403, 37.256%; route: 8.867, 61.144%; tC2Q: 0.232, 1.600%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path8</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.482</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.372</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_18_G[5]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.391</td>
|
|
<td>1.510</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td>mem0/n65_s4/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.946</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>26</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n65_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.412</td>
|
|
<td>0.466</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td>mem0/n54_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.929</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>8</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n54_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.383</td>
|
|
<td>0.454</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td>mem0/n53_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.938</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n53_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.335</td>
|
|
<td>0.397</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td>mem0/n52_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n52_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td>mem0/n51_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n51_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td>mem0/n50_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n50_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td>mem0/n49_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n49_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td>mem0/n48_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n48_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td>mem0/n47_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n47_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td>mem0/n46_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>44</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n46_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.584</td>
|
|
<td>2.467</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td>mem0/mem_s6339/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.139</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>64</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6339/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.224</td>
|
|
<td>1.085</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C28[2][A]</td>
|
|
<td>mem0/mem_s6061/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.595</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R15C28[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6061/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.015</td>
|
|
<td>0.420</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C30[1][A]</td>
|
|
<td>mem0/mem_s5309/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.532</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C30[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5309/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.823</td>
|
|
<td>1.291</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C33[1][B]</td>
|
|
<td>mem0/mem_s4605/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.372</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R15C33[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4605/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.372</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C33[1][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_18_G[5]_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C33[1][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_18_G[5]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C33[1][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_18_G[5]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>12</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 4.955, 34.300%; route: 9.259, 64.094%; tC2Q: 0.232, 1.606%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path9</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.448</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.339</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_18_G[5]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.391</td>
|
|
<td>1.510</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td>mem0/n65_s4/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.946</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>26</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n65_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.412</td>
|
|
<td>0.466</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td>mem0/n54_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.929</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>8</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n54_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.383</td>
|
|
<td>0.454</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td>mem0/n53_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.938</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n53_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.335</td>
|
|
<td>0.397</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td>mem0/n52_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n52_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td>mem0/n51_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n51_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td>mem0/n50_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n50_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td>mem0/n49_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n49_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td>mem0/n48_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n48_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td>mem0/n47_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n47_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td>mem0/n46_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>44</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n46_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.584</td>
|
|
<td>2.467</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td>mem0/mem_s6339/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.139</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>64</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6339/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.224</td>
|
|
<td>1.085</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C28[2][A]</td>
|
|
<td>mem0/mem_s6061/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.595</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R15C28[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6061/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.517</td>
|
|
<td>0.922</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R17C29[3][A]</td>
|
|
<td>mem0/mem_s5929/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.888</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R17C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5929/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.892</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R17C29[3][B]</td>
|
|
<td>mem0/mem_s4986/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.354</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>8</td>
|
|
<td>R17C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4986/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.339</td>
|
|
<td>0.985</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C33[1][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_18_G[5]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C33[1][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_18_G[5]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C33[1][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_18_G[5]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>12</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 4.722, 32.763%; route: 9.459, 65.628%; tC2Q: 0.232, 1.610%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path10</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.448</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.339</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_18_G[1]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.391</td>
|
|
<td>1.510</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td>mem0/n65_s4/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.946</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>26</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n65_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.412</td>
|
|
<td>0.466</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td>mem0/n54_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.929</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>8</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n54_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.383</td>
|
|
<td>0.454</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td>mem0/n53_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.938</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n53_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.335</td>
|
|
<td>0.397</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td>mem0/n52_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n52_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td>mem0/n51_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n51_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td>mem0/n50_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n50_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td>mem0/n49_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n49_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td>mem0/n48_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n48_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td>mem0/n47_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n47_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td>mem0/n46_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>44</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n46_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.584</td>
|
|
<td>2.467</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td>mem0/mem_s6339/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.139</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>64</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6339/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.224</td>
|
|
<td>1.085</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C28[2][A]</td>
|
|
<td>mem0/mem_s6061/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.595</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R15C28[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6061/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.517</td>
|
|
<td>0.922</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R17C29[3][A]</td>
|
|
<td>mem0/mem_s5929/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.888</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R17C29[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5929/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.892</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R17C29[3][B]</td>
|
|
<td>mem0/mem_s4986/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.354</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>8</td>
|
|
<td>R17C29[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4986/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.339</td>
|
|
<td>0.985</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C33[2][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_18_G[1]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C33[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_18_G[1]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C33[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_18_G[1]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>12</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 4.722, 32.763%; route: 9.459, 65.628%; tC2Q: 0.232, 1.610%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path11</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.434</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.324</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_19_G[6]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.391</td>
|
|
<td>1.510</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td>mem0/n65_s4/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.946</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>26</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n65_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.412</td>
|
|
<td>0.466</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td>mem0/n54_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.929</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>8</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n54_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.383</td>
|
|
<td>0.454</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td>mem0/n53_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.938</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n53_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.335</td>
|
|
<td>0.397</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td>mem0/n52_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n52_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td>mem0/n51_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n51_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td>mem0/n50_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n50_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td>mem0/n49_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n49_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td>mem0/n48_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n48_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td>mem0/n47_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n47_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td>mem0/n46_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>44</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n46_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.584</td>
|
|
<td>2.467</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td>mem0/mem_s6339/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.139</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>64</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6339/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.718</td>
|
|
<td>1.579</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C24[3][A]</td>
|
|
<td>mem0/mem_s6063/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.273</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R36C24[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6063/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.488</td>
|
|
<td>0.215</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C25[3][B]</td>
|
|
<td>mem0/mem_s5328/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.043</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C25[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5328/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.775</td>
|
|
<td>0.733</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R35C25[2][A]</td>
|
|
<td>mem0/mem_s4614/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.324</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R35C25[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4614/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.324</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R35C25[2][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_19_G[6]_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R35C25[2][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_19_G[6]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R35C25[2][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_19_G[6]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>12</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.177, 35.956%; route: 8.989, 62.432%; tC2Q: 0.232, 1.611%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path12</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.395</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.285</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[1]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.252</td>
|
|
<td>0.722</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C24[1][B]</td>
|
|
<td>mem0/mem_s5401/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.769</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R15C24[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5401/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.705</td>
|
|
<td>1.936</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C27[3][A]</td>
|
|
<td>mem0/mem_s5937/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.275</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C27[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5937/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.276</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C27[3][B]</td>
|
|
<td>mem0/mem_s4992/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.738</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R32C27[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4992/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.285</td>
|
|
<td>0.547</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C28[0][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_24_G[1]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C28[0][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[1]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R29C28[0][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[1]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.403, 37.627%; route: 8.725, 60.758%; tC2Q: 0.232, 1.616%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path13</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.315</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.206</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_30_G[1]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.252</td>
|
|
<td>0.722</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C24[1][A]</td>
|
|
<td>mem0/mem_s5463/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.769</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R15C24[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5463/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.541</td>
|
|
<td>1.772</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C38[1][B]</td>
|
|
<td>mem0/mem_s5944/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.090</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R40C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5944/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.091</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R40C38[0][B]</td>
|
|
<td>mem0/mem_s4998/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.661</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R40C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4998/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.206</td>
|
|
<td>0.545</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R39C35[2][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_30_G[1]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R39C35[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_30_G[1]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R39C35[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_30_G[1]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.490, 38.445%; route: 8.558, 59.931%; tC2Q: 0.232, 1.625%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path14</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.291</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.182</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_44_G[3]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.391</td>
|
|
<td>1.510</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td>mem0/n65_s4/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.946</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>26</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n65_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.412</td>
|
|
<td>0.466</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td>mem0/n54_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.929</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>8</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n54_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.383</td>
|
|
<td>0.454</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td>mem0/n53_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.938</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n53_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.335</td>
|
|
<td>0.397</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td>mem0/n52_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n52_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td>mem0/n51_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n51_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td>mem0/n50_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n50_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td>mem0/n49_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n49_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td>mem0/n48_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n48_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td>mem0/n47_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n47_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td>mem0/n46_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>44</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n46_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.852</td>
|
|
<td>1.736</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[0][A]</td>
|
|
<td>mem0/mem_s6342/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.369</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>80</td>
|
|
<td>R13C17[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6342/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.679</td>
|
|
<td>1.310</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R22C35[1][B]</td>
|
|
<td>mem0/mem_s6203/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.234</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R22C35[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6203/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.947</td>
|
|
<td>0.712</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R21C42[3][B]</td>
|
|
<td>mem0/mem_s5648/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.464</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R21C42[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5648/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.633</td>
|
|
<td>1.170</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R24C33[1][A]</td>
|
|
<td>mem0/mem_s4811/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.182</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R24C33[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4811/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.182</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C33[1][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_44_G[3]_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R24C33[1][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_44_G[3]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R24C33[1][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_44_G[3]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>12</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.101, 35.782%; route: 8.923, 62.590%; tC2Q: 0.232, 1.627%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path15</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.262</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.153</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[7]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.425</td>
|
|
<td>2.075</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C23[0][A]</td>
|
|
<td>mem0/mem_s6068/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.796</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R15C23[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6068/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.918</td>
|
|
<td>1.121</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C21[1][B]</td>
|
|
<td>mem0/mem_s5725/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.289</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R27C21[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5725/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.538</td>
|
|
<td>1.250</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C27[3][A]</td>
|
|
<td>mem0/mem_s5974/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.108</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R39C27[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5974/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.110</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R39C27[2][B]</td>
|
|
<td>mem0/mem_s5019/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.572</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R39C27[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5019/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.153</td>
|
|
<td>0.581</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R40C21[2][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_51_G[7]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R40C21[2][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[7]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R40C21[2][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[7]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.175, 36.375%; route: 8.820, 61.994%; tC2Q: 0.232, 1.631%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path16</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.262</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.153</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[3]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.425</td>
|
|
<td>2.075</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C23[0][A]</td>
|
|
<td>mem0/mem_s6068/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.796</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R15C23[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6068/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.918</td>
|
|
<td>1.121</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C21[1][B]</td>
|
|
<td>mem0/mem_s5725/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.289</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R27C21[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5725/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.538</td>
|
|
<td>1.250</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C27[3][A]</td>
|
|
<td>mem0/mem_s5974/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.108</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R39C27[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5974/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.110</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R39C27[2][B]</td>
|
|
<td>mem0/mem_s5019/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.572</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R39C27[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5019/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.153</td>
|
|
<td>0.581</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R40C21[0][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_51_G[3]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R40C21[0][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[3]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R40C21[0][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[3]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.175, 36.375%; route: 8.820, 61.994%; tC2Q: 0.232, 1.631%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path17</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.258</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.149</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[5]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.425</td>
|
|
<td>2.075</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C23[0][A]</td>
|
|
<td>mem0/mem_s6068/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.796</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R15C23[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6068/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.918</td>
|
|
<td>1.121</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C21[1][B]</td>
|
|
<td>mem0/mem_s5725/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.289</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R27C21[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5725/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.538</td>
|
|
<td>1.250</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C27[3][A]</td>
|
|
<td>mem0/mem_s5974/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.108</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R39C27[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5974/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.110</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R39C27[2][B]</td>
|
|
<td>mem0/mem_s5019/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.572</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R39C27[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5019/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.149</td>
|
|
<td>0.577</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R38C21[0][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_51_G[5]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R38C21[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[5]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R38C21[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[5]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.175, 36.385%; route: 8.816, 61.984%; tC2Q: 0.232, 1.631%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path18</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.254</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.145</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_22_G[0]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.391</td>
|
|
<td>1.510</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td>mem0/n65_s4/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.946</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>26</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n65_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.412</td>
|
|
<td>0.466</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td>mem0/n54_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.929</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>8</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n54_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.383</td>
|
|
<td>0.454</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td>mem0/n53_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.938</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n53_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.335</td>
|
|
<td>0.397</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td>mem0/n52_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n52_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td>mem0/n51_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n51_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td>mem0/n50_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n50_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td>mem0/n49_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n49_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td>mem0/n48_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n48_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td>mem0/n47_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n47_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td>mem0/n46_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>44</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n46_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.584</td>
|
|
<td>2.467</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td>mem0/mem_s6339/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.139</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>64</td>
|
|
<td>R13C36[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6339/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.794</td>
|
|
<td>1.656</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R18C24[2][B]</td>
|
|
<td>mem0/mem_s6071/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.165</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R18C24[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6071/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.874</td>
|
|
<td>0.709</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C21[3][B]</td>
|
|
<td>mem0/mem_s5366/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.423</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R14C21[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5366/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.596</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C20[0][A]</td>
|
|
<td>mem0/mem_s4632/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.145</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C20[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4632/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.145</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C20[0][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_22_G[0]_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C20[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_22_G[0]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C20[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_22_G[0]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>12</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 4.987, 35.075%; route: 9.000, 63.293%; tC2Q: 0.232, 1.632%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path19</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.249</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.140</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_40_G[7]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.391</td>
|
|
<td>1.510</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td>mem0/n65_s4/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.946</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>26</td>
|
|
<td>R40C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n65_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.412</td>
|
|
<td>0.466</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td>mem0/n54_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.929</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>8</td>
|
|
<td>R38C14[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n54_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.383</td>
|
|
<td>0.454</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td>mem0/n53_s4/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.938</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n53_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.335</td>
|
|
<td>0.397</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td>mem0/n52_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n52_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td>mem0/n51_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R36C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n51_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td>mem0/n50_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n50_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.976</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td>mem0/n49_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C14[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n49_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td>mem0/n48_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n48_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td>mem0/n47_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C15[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n47_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td>mem0/n46_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>44</td>
|
|
<td>R36C15[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n46_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9.852</td>
|
|
<td>1.736</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[0][A]</td>
|
|
<td>mem0/mem_s6342/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.369</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>80</td>
|
|
<td>R13C17[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6342/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.492</td>
|
|
<td>2.122</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C38[1][A]</td>
|
|
<td>mem0/mem_s6173/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.047</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R34C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6173/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.482</td>
|
|
<td>0.435</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C41[0][B]</td>
|
|
<td>mem0/mem_s5608/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.935</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5608/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.591</td>
|
|
<td>0.656</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C39[0][A]</td>
|
|
<td>mem0/mem_s4783/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.140</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R31C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4783/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.140</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C39[0][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_40_G[7]_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C39[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_40_G[7]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R31C39[0][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_40_G[7]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>12</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.037, 35.438%; route: 8.945, 62.930%; tC2Q: 0.232, 1.632%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path20</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.226</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.117</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[5]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.251</td>
|
|
<td>1.722</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C35[1][A]</td>
|
|
<td>mem0/mem_s5246/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.622</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R32C35[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5246/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.835</td>
|
|
<td>1.212</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C40[1][A]</td>
|
|
<td>mem0/mem_s5920/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.206</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5920/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.210</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C40[0][B]</td>
|
|
<td>mem0/mem_s4981/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.537</td>
|
|
<td>0.327</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>8</td>
|
|
<td>R39C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4981/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.117</td>
|
|
<td>0.580</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C41[2][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_13_G[5]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C41[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[5]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R30C41[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[5]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 4.923, 34.692%; route: 9.036, 63.673%; tC2Q: 0.232, 1.635%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path21</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.226</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.117</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[3]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.251</td>
|
|
<td>1.722</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C35[1][A]</td>
|
|
<td>mem0/mem_s5246/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.622</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R32C35[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5246/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.835</td>
|
|
<td>1.212</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C40[1][A]</td>
|
|
<td>mem0/mem_s5920/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.206</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5920/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.210</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C40[0][B]</td>
|
|
<td>mem0/mem_s4981/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.537</td>
|
|
<td>0.327</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>8</td>
|
|
<td>R39C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4981/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.117</td>
|
|
<td>0.580</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C41[1][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_13_G[3]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C41[1][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[3]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R30C41[1][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[3]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 4.923, 34.692%; route: 9.036, 63.673%; tC2Q: 0.232, 1.635%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path22</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.226</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.117</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[0]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.251</td>
|
|
<td>1.722</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C35[1][A]</td>
|
|
<td>mem0/mem_s5246/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.622</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R32C35[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5246/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.835</td>
|
|
<td>1.212</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C40[1][A]</td>
|
|
<td>mem0/mem_s5920/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.206</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5920/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.210</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C40[0][B]</td>
|
|
<td>mem0/mem_s4981/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.537</td>
|
|
<td>0.327</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>8</td>
|
|
<td>R39C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4981/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.117</td>
|
|
<td>0.580</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C41[1][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_13_G[0]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C41[1][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[0]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R30C41[1][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_13_G[0]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 4.923, 34.692%; route: 9.036, 63.673%; tC2Q: 0.232, 1.635%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path23</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.204</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.095</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[4]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.531</td>
|
|
<td>2.002</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td>mem0/mem_s5264/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.086</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R38C35[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5264/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.623</td>
|
|
<td>0.537</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td>mem0/mem_s5923/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.193</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R36C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5923/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.195</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td>mem0/mem_s4983/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.765</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R36C39[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4983/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.095</td>
|
|
<td>0.331</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R35C39[2][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_15_G[4]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R35C39[2][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[4]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R35C39[2][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_15_G[4]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.549, 39.162%; route: 8.388, 59.200%; tC2Q: 0.232, 1.637%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path24</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.198</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.089</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[6]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.425</td>
|
|
<td>2.075</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C23[0][A]</td>
|
|
<td>mem0/mem_s6068/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.796</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>11</td>
|
|
<td>R15C23[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s6068/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.918</td>
|
|
<td>1.121</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R27C21[1][B]</td>
|
|
<td>mem0/mem_s5725/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12.289</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R27C21[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5725/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.538</td>
|
|
<td>1.250</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R39C27[3][A]</td>
|
|
<td>mem0/mem_s5974/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.108</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R39C27[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5974/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.110</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R39C27[2][B]</td>
|
|
<td>mem0/mem_s5019/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.572</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R39C27[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5019/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.089</td>
|
|
<td>0.517</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R38C25[2][A]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_51_G[6]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R38C25[2][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[6]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R38C25[2][A]</td>
|
|
<td>mem0/mem_mem_RAMREG_51_G[6]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.175, 36.540%; route: 8.756, 61.822%; tC2Q: 0.232, 1.638%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path25</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>-4.185</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>15.076</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_raddr_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[5]_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td>core0/reg_raddr_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>190</td>
|
|
<td>R32C18[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_raddr_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.326</td>
|
|
<td>1.168</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td>mem0/mem_s5980/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.881</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>17</td>
|
|
<td>R13C17[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5980/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.580</td>
|
|
<td>1.699</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td>mem0/n107_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.033</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>4</td>
|
|
<td>R40C12[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n107_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.606</td>
|
|
<td>0.573</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td>mem0/n104_s5/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.155</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>4</td>
|
|
<td>R40C9[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n104_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.333</td>
|
|
<td>0.178</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td>mem0/n102_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C9[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n102_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.076</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td>mem0/n101_s3/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n101_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.646</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td>mem0/n100_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R41C10[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n100_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.681</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td>mem0/n99_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n99_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.716</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td>mem0/n98_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n98_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.751</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td>mem0/n97_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n97_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.786</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td>mem0/n96_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C10[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n96_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.822</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td>mem0/n95_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n95_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.857</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td>mem0/n94_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n94_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.892</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td>mem0/n93_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n93_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.927</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td>mem0/n92_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n92_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.962</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td>mem0/n91_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n91_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td>mem0/n90_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C11[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n90_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.033</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td>mem0/n89_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n89_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.068</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td>mem0/n88_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n88_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.103</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td>mem0/n87_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n87_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.138</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td>mem0/n86_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n86_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.174</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td>mem0/n85_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n85_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.209</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td>mem0/n84_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C12[2][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n84_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.244</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td>mem0/n83_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n83_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.279</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td>mem0/n82_s3/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R41C13[0][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/n82_s3/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.314</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td>mem0/n81_s2/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.350</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>16</td>
|
|
<td>R41C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/n81_s2/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.077</td>
|
|
<td>1.727</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td>mem0/mem_s5990/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.530</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>24</td>
|
|
<td>R15C14[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5990/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.252</td>
|
|
<td>0.722</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C24[1][B]</td>
|
|
<td>mem0/mem_s5401/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11.769</td>
|
|
<td>0.517</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>9</td>
|
|
<td>R15C24[1][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5401/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13.705</td>
|
|
<td>1.936</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C27[3][A]</td>
|
|
<td>mem0/mem_s5937/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.275</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R32C27[3][A]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s5937/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.276</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C27[3][B]</td>
|
|
<td>mem0/mem_s4992/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14.738</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R32C27[3][B]</td>
|
|
<td style=" background: #97FFFF;">mem0/mem_s4992/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15.076</td>
|
|
<td>0.338</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[2][B]</td>
|
|
<td style=" font-weight:bold;">mem0/mem_mem_RAMREG_24_G[5]_s0/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C26[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[5]_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R32C26[2][B]</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[5]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>13</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 5.403, 38.183%; route: 8.515, 60.177%; tC2Q: 0.232, 1.640%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
|
<h3>Path1</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.346</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.978</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/rs2_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R30C18[1][B]</td>
|
|
<td>core0/rs2_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R30C18[1][B]</td>
|
|
<td style=" font-weight:bold;">core0/rs2_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.323</td>
|
|
<td>0.262</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[5]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/ADB[9]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[5]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.978</td>
|
|
<td>0.118</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[5]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path2</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.359</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.337</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.978</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/rd_0_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R27C22[2][A]</td>
|
|
<td>core0/rd_0_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>4</td>
|
|
<td>R27C22[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/rd_0_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.337</td>
|
|
<td>0.275</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[5]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/ADA[5]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[5]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.978</td>
|
|
<td>0.118</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R28[5]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.275, 57.645%; tC2Q: 0.202, 42.355%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path3</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_0_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_0_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[0][A]</td>
|
|
<td>core0/alu_out_0_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R32C18[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_0_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[0][A]</td>
|
|
<td>core0/n586_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C18[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n586_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C18[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_0_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[0][A]</td>
|
|
<td>core0/alu_out_0_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R32C18[0][A]</td>
|
|
<td>core0/alu_out_0_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path4</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_3_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_3_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[1][A]</td>
|
|
<td>core0/alu_out_3_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R32C18[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_3_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[1][A]</td>
|
|
<td>core0/n580_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C18[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n580_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C18[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_3_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C18[1][A]</td>
|
|
<td>core0/alu_out_3_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R32C18[1][A]</td>
|
|
<td>core0/alu_out_3_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path5</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_5_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_5_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C17[0][A]</td>
|
|
<td>core0/alu_out_5_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R29C17[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_5_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C17[0][A]</td>
|
|
<td>core0/n576_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R29C17[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n576_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C17[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_5_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C17[0][A]</td>
|
|
<td>core0/alu_out_5_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R29C17[0][A]</td>
|
|
<td>core0/alu_out_5_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path6</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_6_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_6_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C15[0][A]</td>
|
|
<td>core0/alu_out_6_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R32C15[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_6_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C15[0][A]</td>
|
|
<td>core0/n574_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C15[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n574_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C15[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_6_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C15[0][A]</td>
|
|
<td>core0/alu_out_6_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R32C15[0][A]</td>
|
|
<td>core0/alu_out_6_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path7</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_7_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_7_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C13[0][A]</td>
|
|
<td>core0/alu_out_7_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R34C13[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_7_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C13[0][A]</td>
|
|
<td>core0/n572_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R34C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n572_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R34C13[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_7_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R34C13[0][A]</td>
|
|
<td>core0/alu_out_7_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R34C13[0][A]</td>
|
|
<td>core0/alu_out_7_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path8</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_9_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_9_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C12[1][A]</td>
|
|
<td>core0/alu_out_9_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R33C12[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_9_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C12[1][A]</td>
|
|
<td>core0/n568_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R33C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n568_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C12[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_9_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C12[1][A]</td>
|
|
<td>core0/alu_out_9_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C12[1][A]</td>
|
|
<td>core0/alu_out_9_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path9</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_11_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_11_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C12[0][A]</td>
|
|
<td>core0/alu_out_11_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R33C12[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_11_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C12[0][A]</td>
|
|
<td>core0/n564_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R33C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n564_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C12[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_11_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C12[0][A]</td>
|
|
<td>core0/alu_out_11_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C12[0][A]</td>
|
|
<td>core0/alu_out_11_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path10</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_12_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_12_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C13[0][A]</td>
|
|
<td>core0/alu_out_12_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R33C13[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_12_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C13[0][A]</td>
|
|
<td>core0/n562_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R33C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n562_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C13[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_12_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C13[0][A]</td>
|
|
<td>core0/alu_out_12_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C13[0][A]</td>
|
|
<td>core0/alu_out_12_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path11</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_13_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_13_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C13[0][A]</td>
|
|
<td>core0/alu_out_13_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R29C13[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_13_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C13[0][A]</td>
|
|
<td>core0/n560_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R29C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n560_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R29C13[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_13_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R29C13[0][A]</td>
|
|
<td>core0/alu_out_13_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R29C13[0][A]</td>
|
|
<td>core0/alu_out_13_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path12</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_14_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_14_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C13[1][A]</td>
|
|
<td>core0/alu_out_14_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R33C13[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_14_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C13[1][A]</td>
|
|
<td>core0/n558_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R33C13[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n558_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R33C13[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_14_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R33C13[1][A]</td>
|
|
<td>core0/alu_out_14_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R33C13[1][A]</td>
|
|
<td>core0/alu_out_14_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path13</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_23_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_23_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C12[0][A]</td>
|
|
<td>core0/alu_out_23_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R31C12[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_23_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C12[0][A]</td>
|
|
<td>core0/n540_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R31C12[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n540_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C12[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_23_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C12[0][A]</td>
|
|
<td>core0/alu_out_23_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R31C12[0][A]</td>
|
|
<td>core0/alu_out_23_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path14</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_25_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_25_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C12[1][A]</td>
|
|
<td>core0/alu_out_25_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R31C12[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_25_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C12[1][A]</td>
|
|
<td>core0/n536_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R31C12[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n536_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R31C12[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_25_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R31C12[1][A]</td>
|
|
<td>core0/alu_out_25_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R31C12[1][A]</td>
|
|
<td>core0/alu_out_25_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path15</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/alu_out_27_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_27_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C13[0][A]</td>
|
|
<td>core0/alu_out_27_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R32C13[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_27_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C13[0][A]</td>
|
|
<td>core0/n532_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R32C13[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n532_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R32C13[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_27_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R32C13[0][A]</td>
|
|
<td>core0/alu_out_27_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R32C13[0][A]</td>
|
|
<td>core0/alu_out_27_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path16</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/led_flag_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/led_flag_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R21C27[0][A]</td>
|
|
<td>uart0/led_flag_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R21C27[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/led_flag_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R21C27[0][A]</td>
|
|
<td>uart0/n79_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R21C27[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n79_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R21C27[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/led_flag_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R21C27[0][A]</td>
|
|
<td>uart0/led_flag_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R21C27[0][A]</td>
|
|
<td>uart0/led_flag_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path17</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C27[1][A]</td>
|
|
<td>uart0/clock_count_2_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C27[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_2_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C27[1][A]</td>
|
|
<td>uart0/n44_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R23C27[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n44_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R23C27[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_2_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C27[1][A]</td>
|
|
<td>uart0/clock_count_2_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R23C27[1][A]</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path18</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C28[0][A]</td>
|
|
<td>uart0/clock_count_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>3</td>
|
|
<td>R23C28[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_6_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C28[0][A]</td>
|
|
<td>uart0/n40_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R23C28[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n40_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R23C28[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_6_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C28[0][A]</td>
|
|
<td>uart0/clock_count_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R23C28[0][A]</td>
|
|
<td>uart0/clock_count_6_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path19</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C28[1][A]</td>
|
|
<td>uart0/clock_count_8_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C28[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_8_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C28[1][A]</td>
|
|
<td>uart0/n38_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R23C28[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n38_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R23C28[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_8_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C28[1][A]</td>
|
|
<td>uart0/clock_count_8_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R23C28[1][A]</td>
|
|
<td>uart0/clock_count_8_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path20</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_12_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_12_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C29[0][A]</td>
|
|
<td>uart0/clock_count_12_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C29[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_12_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C29[0][A]</td>
|
|
<td>uart0/n34_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R23C29[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n34_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R23C29[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_12_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C29[0][A]</td>
|
|
<td>uart0/clock_count_12_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R23C29[0][A]</td>
|
|
<td>uart0/clock_count_12_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path21</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_14_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_14_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C29[1][A]</td>
|
|
<td>uart0/clock_count_14_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C29[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_14_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C29[1][A]</td>
|
|
<td>uart0/n32_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R23C29[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n32_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R23C29[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_14_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C29[1][A]</td>
|
|
<td>uart0/clock_count_14_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R23C29[1][A]</td>
|
|
<td>uart0/clock_count_14_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path22</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_18_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_18_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C30[0][A]</td>
|
|
<td>uart0/clock_count_18_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C30[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_18_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C30[0][A]</td>
|
|
<td>uart0/n28_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R23C30[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n28_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R23C30[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_18_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C30[0][A]</td>
|
|
<td>uart0/clock_count_18_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R23C30[0][A]</td>
|
|
<td>uart0/clock_count_18_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path23</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_20_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_20_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C30[1][A]</td>
|
|
<td>uart0/clock_count_20_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C30[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_20_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C30[1][A]</td>
|
|
<td>uart0/n26_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R23C30[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n26_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R23C30[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_20_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C30[1][A]</td>
|
|
<td>uart0/clock_count_20_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R23C30[1][A]</td>
|
|
<td>uart0/clock_count_20_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path24</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C31[0][A]</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C31[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_24_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C31[0][A]</td>
|
|
<td>uart0/n22_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R23C31[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n22_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R23C31[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_24_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C31[0][A]</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R23C31[0][A]</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path25</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_26_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_26_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C31[1][A]</td>
|
|
<td>uart0/clock_count_26_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C31[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_26_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R23C31[1][A]</td>
|
|
<td>uart0/n20_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R23C31[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n20_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R23C31[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_26_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>759</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R23C31[1][A]</td>
|
|
<td>uart0/clock_count_26_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R23C31[1][A]</td>
|
|
<td>uart0/clock_count_26_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>No recovery paths to report!</h4>
|
|
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>No removal paths to report!</h4>
|
|
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
|
|
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
<h3>MPW1</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_30_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_30_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_30_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW2</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_28_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_28_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_28_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW3</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW4</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_16_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_16_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_16_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW5</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_0_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_0_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_0_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW6</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>mem0/mem_mem_RAMREG_0_G[4]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>mem0/mem_mem_RAMREG_0_G[4]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>mem0/mem_mem_RAMREG_0_G[4]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW7</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>mem0/mem_mem_RAMREG_8_G[4]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>mem0/mem_mem_RAMREG_8_G[4]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>mem0/mem_mem_RAMREG_8_G[4]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW8</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[4]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[4]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>mem0/mem_mem_RAMREG_24_G[4]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW9</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>mem0/mem_mem_RAMREG_56_G[4]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>mem0/mem_mem_RAMREG_56_G[4]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>mem0/mem_mem_RAMREG_56_G[4]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW10</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>mem0/mem_mem_RAMREG_56_G[3]_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>mem0/mem_mem_RAMREG_56_G[3]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>mem0/mem_mem_RAMREG_56_G[3]_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
|
|
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">NET NAME</th>
|
|
<th class="label">WORST SLACK</th>
|
|
<th class="label">MAX DELAY</th>
|
|
</tr>
|
|
<tr>
|
|
<td>759</td>
|
|
<td>clock_d</td>
|
|
<td>-4.604</td>
|
|
<td>0.261</td>
|
|
</tr>
|
|
<tr>
|
|
<td>558</td>
|
|
<td>raddr[5]</td>
|
|
<td>-4.197</td>
|
|
<td>1.942</td>
|
|
</tr>
|
|
<tr>
|
|
<td>260</td>
|
|
<td>pc[5]</td>
|
|
<td>3.634</td>
|
|
<td>2.206</td>
|
|
</tr>
|
|
<tr>
|
|
<td>257</td>
|
|
<td>n36_15</td>
|
|
<td>1.639</td>
|
|
<td>2.760</td>
|
|
</tr>
|
|
<tr>
|
|
<td>256</td>
|
|
<td>n155_9</td>
|
|
<td>2.875</td>
|
|
<td>2.261</td>
|
|
</tr>
|
|
<tr>
|
|
<td>256</td>
|
|
<td>n36_7</td>
|
|
<td>1.639</td>
|
|
<td>2.471</td>
|
|
</tr>
|
|
<tr>
|
|
<td>256</td>
|
|
<td>n107_7</td>
|
|
<td>-0.070</td>
|
|
<td>2.596</td>
|
|
</tr>
|
|
<tr>
|
|
<td>256</td>
|
|
<td>n236_6</td>
|
|
<td>2.990</td>
|
|
<td>1.907</td>
|
|
</tr>
|
|
<tr>
|
|
<td>190</td>
|
|
<td>raddr[4]</td>
|
|
<td>-4.604</td>
|
|
<td>1.840</td>
|
|
</tr>
|
|
<tr>
|
|
<td>160</td>
|
|
<td>n196_6</td>
|
|
<td>3.511</td>
|
|
<td>1.495</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
|
|
<h4>Report Command:report_route_congestion -max_grids 10</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">GRID LOC</th>
|
|
<th class="label">ROUTE CONGESTIONS</th>
|
|
</tr>
|
|
<tr>
|
|
<td>R31C39</td>
|
|
<td>94.44%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R24C33</td>
|
|
<td>90.28%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R18C35</td>
|
|
<td>88.89%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R32C18</td>
|
|
<td>87.50%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R33C38</td>
|
|
<td>87.50%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R34C35</td>
|
|
<td>87.50%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R32C20</td>
|
|
<td>87.50%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R32C27</td>
|
|
<td>87.50%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R29C39</td>
|
|
<td>86.11%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R30C18</td>
|
|
<td>86.11%</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
|
|
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">SDC Command Type</th>
|
|
<th class="label">State</th>
|
|
<th class="label">Detail Command</th>
|
|
</tr>
|
|
</table>
|
|
</div><!-- content -->
|
|
</body>
|
|
</html>
|