mirror of
https://github.com/mii443/tangprimer-riscv.git
synced 2025-08-22 16:25:39 +00:00
39 lines
2.1 KiB
Plaintext
39 lines
2.1 KiB
Plaintext
GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\memory.v'
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Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\top.v'
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Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\uart.v'
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Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\core.v'
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Analyzing included file 'C:\Users\kuroc\Downloads\cpu\src\defs.vh'("C:\Users\kuroc\Downloads\cpu\src\core.v":1)
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Back to file 'C:\Users\kuroc\Downloads\cpu\src\core.v'("C:\Users\kuroc\Downloads\cpu\src\core.v":1)
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Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\defs.vh'
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Compiling module 'TOP'("C:\Users\kuroc\Downloads\cpu\src\top.v":1)
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Compiling module 'UART'("C:\Users\kuroc\Downloads\cpu\src\uart.v":1)
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WARN (EX3791) : Expression size 5 truncated to fit in target size 4("C:\Users\kuroc\Downloads\cpu\src\uart.v":98)
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Compiling module 'MEMORY'("C:\Users\kuroc\Downloads\cpu\src\memory.v":1)
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Extracting RAM for identifier 'mem'("C:\Users\kuroc\Downloads\cpu\src\memory.v":13)
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WARN (EX3784) : Index 33 is out of range [32:0] for 'mem'("C:\Users\kuroc\Downloads\cpu\src\memory.v":19)
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Compiling module 'CORE'("C:\Users\kuroc\Downloads\cpu\src\core.v":3)
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Extracting RAM for identifier 'register'("C:\Users\kuroc\Downloads\cpu\src\core.v":19)
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WARN (EX3791) : Expression size 32 truncated to fit in target size 21("C:\Users\kuroc\Downloads\cpu\src\core.v":101)
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NOTE (EX0101) : Current top module is "TOP"
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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[95%] Generate netlist file "C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg" completed
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[100%] Generate report file "C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu_syn.rpt.html" completed
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GowinSynthesis finish
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