tangprimer-riscv/impl/temp/rtl_parser_arg.json

{
 "Files" : [
  {
   "Path" : "C:/Users/kuroc/Downloads/cpu/src/memory.v",
   "Type" : "verilog"
  },
  {
   "Path" : "C:/Users/kuroc/Downloads/cpu/src/top.v",
   "Type" : "verilog"
  },
  {
   "Path" : "C:/Users/kuroc/Downloads/cpu/src/uart.v",
   "Type" : "verilog"
  },
  {
   "Path" : "C:/Users/kuroc/Downloads/cpu/src/core.v",
   "Type" : "verilog"
  },
  {
   "Path" : "C:/Users/kuroc/Downloads/cpu/src/defs.vh",
   "Type" : "verilog"
  }
 ],
 "IncludePath" : [

 ],
 "LoopLimit" : 2000,
 "ResultFile" : "C:/Users/kuroc/Downloads/cpu/impl/temp/rtl_parser.result",
 "Top" : "",
 "VerilogStd" : "verilog_2001",
 "VhdlStd" : "vhdl_93"
}