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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\kuroc\Downloads\cpu\src\memory.v<br>
C:\Users\kuroc\Downloads\cpu\src\top.v<br>
C:\Users\kuroc\Downloads\cpu\src\uart.v<br>
C:\Users\kuroc\Downloads\cpu\src\core.v<br>
C:\Users\kuroc\Downloads\cpu\src\defs.vh<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>GowinSynthesis V1.9.8.09 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu May 18 14:31:16 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>TOP</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.155s, Peak memory usage = 327.422MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 327.422MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 327.422MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 327.422MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 327.422MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 327.422MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 327.422MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 327.422MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.192s, Peak memory usage = 327.422MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 327.422MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 327.422MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 12s, Elapsed time = 0h 0m 12s, Peak memory usage = 327.422MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.444s, Peak memory usage = 327.422MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.265s, Elapsed time = 0h 0m 0.285s, Peak memory usage = 327.422MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 13s, Elapsed time = 0h 0m 13s, Peak memory usage = 327.422MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>755</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>58</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>657</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>32</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>4197</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>153</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>2489</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>1555</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>171</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>171</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>2</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>4371(4200 LUTs, 171 ALUs) / 20736</td>
<td>21%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>755 / 16173</td>
<td>5%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>755 / 16173</td>
<td>5%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>2 / 46</td>
<td>4%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clock</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>clock_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clock</td>
<td>100.0(MHz)</td>
<td>122.4(MHz)</td>
<td>13</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.830</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.998</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/reg_raddr_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mem0/mem_mem_RAMREG_37_G[7]_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_raddr_3_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>111</td>
<td>core0/reg_raddr_3_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5980/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>17</td>
<td>mem0/mem_s5980/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n36_s7/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>mem0/n36_s7/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n33_s7/I0</td>
</tr>
<tr>
<td>3.433</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>mem0/n33_s7/F</td>
</tr>
<tr>
<td>3.670</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/I1</td>
</tr>
<tr>
<td>4.225</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/F</td>
</tr>
<tr>
<td>4.462</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n31_s3/I1</td>
</tr>
<tr>
<td>5.032</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>mem0/n31_s3/COUT</td>
</tr>
<tr>
<td>5.032</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>mem0/n30_s3/CIN</td>
</tr>
<tr>
<td>5.067</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>mem0/n30_s3/COUT</td>
</tr>
<tr>
<td>5.067</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n29_s3/CIN</td>
</tr>
<tr>
<td>5.102</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n29_s3/COUT</td>
</tr>
<tr>
<td>5.102</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n28_s3/CIN</td>
</tr>
<tr>
<td>5.137</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n28_s3/COUT</td>
</tr>
<tr>
<td>5.137</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n27_s3/CIN</td>
</tr>
<tr>
<td>5.172</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n27_s3/COUT</td>
</tr>
<tr>
<td>5.172</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n26_s3/CIN</td>
</tr>
<tr>
<td>5.208</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n26_s3/COUT</td>
</tr>
<tr>
<td>5.208</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n25_s3/CIN</td>
</tr>
<tr>
<td>5.243</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n25_s3/COUT</td>
</tr>
<tr>
<td>5.243</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n24_s3/CIN</td>
</tr>
<tr>
<td>5.278</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n24_s3/COUT</td>
</tr>
<tr>
<td>5.278</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n23_s3/CIN</td>
</tr>
<tr>
<td>5.313</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n23_s3/COUT</td>
</tr>
<tr>
<td>5.313</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n22_s3/CIN</td>
</tr>
<tr>
<td>5.348</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n22_s3/COUT</td>
</tr>
<tr>
<td>5.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n21_s3/CIN</td>
</tr>
<tr>
<td>5.384</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n21_s3/COUT</td>
</tr>
<tr>
<td>5.384</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n20_s3/CIN</td>
</tr>
<tr>
<td>5.419</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n20_s3/COUT</td>
</tr>
<tr>
<td>5.419</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n19_s3/CIN</td>
</tr>
<tr>
<td>5.454</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n19_s3/COUT</td>
</tr>
<tr>
<td>5.454</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n18_s3/CIN</td>
</tr>
<tr>
<td>5.489</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n18_s3/COUT</td>
</tr>
<tr>
<td>5.489</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n17_s3/CIN</td>
</tr>
<tr>
<td>5.524</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n17_s3/COUT</td>
</tr>
<tr>
<td>5.524</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n16_s3/CIN</td>
</tr>
<tr>
<td>5.560</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n16_s3/COUT</td>
</tr>
<tr>
<td>5.560</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n15_s3/CIN</td>
</tr>
<tr>
<td>5.595</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n15_s3/COUT</td>
</tr>
<tr>
<td>5.595</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n14_s3/CIN</td>
</tr>
<tr>
<td>5.630</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n14_s3/COUT</td>
</tr>
<tr>
<td>5.630</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n13_s3/CIN</td>
</tr>
<tr>
<td>5.665</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n13_s3/COUT</td>
</tr>
<tr>
<td>5.665</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n12_s3/CIN</td>
</tr>
<tr>
<td>5.700</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n12_s3/COUT</td>
</tr>
<tr>
<td>5.700</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n11_s3/CIN</td>
</tr>
<tr>
<td>5.736</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n11_s3/COUT</td>
</tr>
<tr>
<td>5.736</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n10_s2/CIN</td>
</tr>
<tr>
<td>5.771</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>mem0/n10_s2/COUT</td>
</tr>
<tr>
<td>6.008</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5954/I1</td>
</tr>
<tr>
<td>6.563</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>mem0/mem_s5954/F</td>
</tr>
<tr>
<td>6.800</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6167/I2</td>
</tr>
<tr>
<td>7.253</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6167/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5565/I0</td>
</tr>
<tr>
<td>8.007</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5565/F</td>
</tr>
<tr>
<td>8.244</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4759/I0</td>
</tr>
<tr>
<td>8.761</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4759/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[7]_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[7]_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[7]_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>13</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.533, 68.015%; route: 2.370, 29.133%; tC2Q: 0.232, 2.852%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.830</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.998</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/reg_raddr_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mem0/mem_mem_RAMREG_37_G[6]_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_raddr_3_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>111</td>
<td>core0/reg_raddr_3_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5980/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>17</td>
<td>mem0/mem_s5980/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n36_s7/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>mem0/n36_s7/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n33_s7/I0</td>
</tr>
<tr>
<td>3.433</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>mem0/n33_s7/F</td>
</tr>
<tr>
<td>3.670</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/I1</td>
</tr>
<tr>
<td>4.225</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/F</td>
</tr>
<tr>
<td>4.462</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n31_s3/I1</td>
</tr>
<tr>
<td>5.032</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>mem0/n31_s3/COUT</td>
</tr>
<tr>
<td>5.032</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>mem0/n30_s3/CIN</td>
</tr>
<tr>
<td>5.067</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>mem0/n30_s3/COUT</td>
</tr>
<tr>
<td>5.067</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n29_s3/CIN</td>
</tr>
<tr>
<td>5.102</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n29_s3/COUT</td>
</tr>
<tr>
<td>5.102</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n28_s3/CIN</td>
</tr>
<tr>
<td>5.137</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n28_s3/COUT</td>
</tr>
<tr>
<td>5.137</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n27_s3/CIN</td>
</tr>
<tr>
<td>5.172</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n27_s3/COUT</td>
</tr>
<tr>
<td>5.172</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n26_s3/CIN</td>
</tr>
<tr>
<td>5.208</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n26_s3/COUT</td>
</tr>
<tr>
<td>5.208</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n25_s3/CIN</td>
</tr>
<tr>
<td>5.243</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n25_s3/COUT</td>
</tr>
<tr>
<td>5.243</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n24_s3/CIN</td>
</tr>
<tr>
<td>5.278</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n24_s3/COUT</td>
</tr>
<tr>
<td>5.278</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n23_s3/CIN</td>
</tr>
<tr>
<td>5.313</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n23_s3/COUT</td>
</tr>
<tr>
<td>5.313</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n22_s3/CIN</td>
</tr>
<tr>
<td>5.348</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n22_s3/COUT</td>
</tr>
<tr>
<td>5.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n21_s3/CIN</td>
</tr>
<tr>
<td>5.384</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n21_s3/COUT</td>
</tr>
<tr>
<td>5.384</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n20_s3/CIN</td>
</tr>
<tr>
<td>5.419</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n20_s3/COUT</td>
</tr>
<tr>
<td>5.419</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n19_s3/CIN</td>
</tr>
<tr>
<td>5.454</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n19_s3/COUT</td>
</tr>
<tr>
<td>5.454</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n18_s3/CIN</td>
</tr>
<tr>
<td>5.489</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n18_s3/COUT</td>
</tr>
<tr>
<td>5.489</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n17_s3/CIN</td>
</tr>
<tr>
<td>5.524</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n17_s3/COUT</td>
</tr>
<tr>
<td>5.524</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n16_s3/CIN</td>
</tr>
<tr>
<td>5.560</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n16_s3/COUT</td>
</tr>
<tr>
<td>5.560</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n15_s3/CIN</td>
</tr>
<tr>
<td>5.595</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n15_s3/COUT</td>
</tr>
<tr>
<td>5.595</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n14_s3/CIN</td>
</tr>
<tr>
<td>5.630</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n14_s3/COUT</td>
</tr>
<tr>
<td>5.630</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n13_s3/CIN</td>
</tr>
<tr>
<td>5.665</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n13_s3/COUT</td>
</tr>
<tr>
<td>5.665</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n12_s3/CIN</td>
</tr>
<tr>
<td>5.700</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n12_s3/COUT</td>
</tr>
<tr>
<td>5.700</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n11_s3/CIN</td>
</tr>
<tr>
<td>5.736</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n11_s3/COUT</td>
</tr>
<tr>
<td>5.736</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n10_s2/CIN</td>
</tr>
<tr>
<td>5.771</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>mem0/n10_s2/COUT</td>
</tr>
<tr>
<td>6.008</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5954/I1</td>
</tr>
<tr>
<td>6.563</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>mem0/mem_s5954/F</td>
</tr>
<tr>
<td>6.800</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6166/I2</td>
</tr>
<tr>
<td>7.253</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6166/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5564/I0</td>
</tr>
<tr>
<td>8.007</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5564/F</td>
</tr>
<tr>
<td>8.244</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4758/I0</td>
</tr>
<tr>
<td>8.761</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4758/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[6]_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[6]_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[6]_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>13</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.533, 68.015%; route: 2.370, 29.133%; tC2Q: 0.232, 2.852%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.830</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.998</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/reg_raddr_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mem0/mem_mem_RAMREG_37_G[5]_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_raddr_3_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>111</td>
<td>core0/reg_raddr_3_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5980/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>17</td>
<td>mem0/mem_s5980/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n36_s7/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>mem0/n36_s7/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n33_s7/I0</td>
</tr>
<tr>
<td>3.433</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>mem0/n33_s7/F</td>
</tr>
<tr>
<td>3.670</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/I1</td>
</tr>
<tr>
<td>4.225</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/F</td>
</tr>
<tr>
<td>4.462</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n31_s3/I1</td>
</tr>
<tr>
<td>5.032</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>mem0/n31_s3/COUT</td>
</tr>
<tr>
<td>5.032</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>mem0/n30_s3/CIN</td>
</tr>
<tr>
<td>5.067</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>mem0/n30_s3/COUT</td>
</tr>
<tr>
<td>5.067</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n29_s3/CIN</td>
</tr>
<tr>
<td>5.102</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n29_s3/COUT</td>
</tr>
<tr>
<td>5.102</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n28_s3/CIN</td>
</tr>
<tr>
<td>5.137</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n28_s3/COUT</td>
</tr>
<tr>
<td>5.137</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n27_s3/CIN</td>
</tr>
<tr>
<td>5.172</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n27_s3/COUT</td>
</tr>
<tr>
<td>5.172</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n26_s3/CIN</td>
</tr>
<tr>
<td>5.208</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n26_s3/COUT</td>
</tr>
<tr>
<td>5.208</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n25_s3/CIN</td>
</tr>
<tr>
<td>5.243</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n25_s3/COUT</td>
</tr>
<tr>
<td>5.243</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n24_s3/CIN</td>
</tr>
<tr>
<td>5.278</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n24_s3/COUT</td>
</tr>
<tr>
<td>5.278</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n23_s3/CIN</td>
</tr>
<tr>
<td>5.313</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n23_s3/COUT</td>
</tr>
<tr>
<td>5.313</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n22_s3/CIN</td>
</tr>
<tr>
<td>5.348</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n22_s3/COUT</td>
</tr>
<tr>
<td>5.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n21_s3/CIN</td>
</tr>
<tr>
<td>5.384</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n21_s3/COUT</td>
</tr>
<tr>
<td>5.384</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n20_s3/CIN</td>
</tr>
<tr>
<td>5.419</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n20_s3/COUT</td>
</tr>
<tr>
<td>5.419</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n19_s3/CIN</td>
</tr>
<tr>
<td>5.454</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n19_s3/COUT</td>
</tr>
<tr>
<td>5.454</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n18_s3/CIN</td>
</tr>
<tr>
<td>5.489</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n18_s3/COUT</td>
</tr>
<tr>
<td>5.489</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n17_s3/CIN</td>
</tr>
<tr>
<td>5.524</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n17_s3/COUT</td>
</tr>
<tr>
<td>5.524</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n16_s3/CIN</td>
</tr>
<tr>
<td>5.560</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n16_s3/COUT</td>
</tr>
<tr>
<td>5.560</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n15_s3/CIN</td>
</tr>
<tr>
<td>5.595</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n15_s3/COUT</td>
</tr>
<tr>
<td>5.595</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n14_s3/CIN</td>
</tr>
<tr>
<td>5.630</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n14_s3/COUT</td>
</tr>
<tr>
<td>5.630</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n13_s3/CIN</td>
</tr>
<tr>
<td>5.665</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n13_s3/COUT</td>
</tr>
<tr>
<td>5.665</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n12_s3/CIN</td>
</tr>
<tr>
<td>5.700</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n12_s3/COUT</td>
</tr>
<tr>
<td>5.700</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n11_s3/CIN</td>
</tr>
<tr>
<td>5.736</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n11_s3/COUT</td>
</tr>
<tr>
<td>5.736</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n10_s2/CIN</td>
</tr>
<tr>
<td>5.771</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>mem0/n10_s2/COUT</td>
</tr>
<tr>
<td>6.008</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5954/I1</td>
</tr>
<tr>
<td>6.563</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>mem0/mem_s5954/F</td>
</tr>
<tr>
<td>6.800</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6165/I2</td>
</tr>
<tr>
<td>7.253</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6165/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5563/I0</td>
</tr>
<tr>
<td>8.007</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5563/F</td>
</tr>
<tr>
<td>8.244</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4757/I0</td>
</tr>
<tr>
<td>8.761</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4757/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[5]_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[5]_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[5]_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>13</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.533, 68.015%; route: 2.370, 29.133%; tC2Q: 0.232, 2.852%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.830</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.998</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/reg_raddr_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mem0/mem_mem_RAMREG_37_G[4]_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_raddr_3_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>111</td>
<td>core0/reg_raddr_3_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5980/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>17</td>
<td>mem0/mem_s5980/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n36_s7/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>mem0/n36_s7/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n33_s7/I0</td>
</tr>
<tr>
<td>3.433</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>mem0/n33_s7/F</td>
</tr>
<tr>
<td>3.670</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/I1</td>
</tr>
<tr>
<td>4.225</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/F</td>
</tr>
<tr>
<td>4.462</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n31_s3/I1</td>
</tr>
<tr>
<td>5.032</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>mem0/n31_s3/COUT</td>
</tr>
<tr>
<td>5.032</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>mem0/n30_s3/CIN</td>
</tr>
<tr>
<td>5.067</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>mem0/n30_s3/COUT</td>
</tr>
<tr>
<td>5.067</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n29_s3/CIN</td>
</tr>
<tr>
<td>5.102</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n29_s3/COUT</td>
</tr>
<tr>
<td>5.102</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n28_s3/CIN</td>
</tr>
<tr>
<td>5.137</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n28_s3/COUT</td>
</tr>
<tr>
<td>5.137</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n27_s3/CIN</td>
</tr>
<tr>
<td>5.172</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n27_s3/COUT</td>
</tr>
<tr>
<td>5.172</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n26_s3/CIN</td>
</tr>
<tr>
<td>5.208</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n26_s3/COUT</td>
</tr>
<tr>
<td>5.208</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n25_s3/CIN</td>
</tr>
<tr>
<td>5.243</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n25_s3/COUT</td>
</tr>
<tr>
<td>5.243</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n24_s3/CIN</td>
</tr>
<tr>
<td>5.278</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n24_s3/COUT</td>
</tr>
<tr>
<td>5.278</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n23_s3/CIN</td>
</tr>
<tr>
<td>5.313</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n23_s3/COUT</td>
</tr>
<tr>
<td>5.313</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n22_s3/CIN</td>
</tr>
<tr>
<td>5.348</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n22_s3/COUT</td>
</tr>
<tr>
<td>5.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n21_s3/CIN</td>
</tr>
<tr>
<td>5.384</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n21_s3/COUT</td>
</tr>
<tr>
<td>5.384</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n20_s3/CIN</td>
</tr>
<tr>
<td>5.419</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n20_s3/COUT</td>
</tr>
<tr>
<td>5.419</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n19_s3/CIN</td>
</tr>
<tr>
<td>5.454</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n19_s3/COUT</td>
</tr>
<tr>
<td>5.454</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n18_s3/CIN</td>
</tr>
<tr>
<td>5.489</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n18_s3/COUT</td>
</tr>
<tr>
<td>5.489</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n17_s3/CIN</td>
</tr>
<tr>
<td>5.524</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n17_s3/COUT</td>
</tr>
<tr>
<td>5.524</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n16_s3/CIN</td>
</tr>
<tr>
<td>5.560</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n16_s3/COUT</td>
</tr>
<tr>
<td>5.560</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n15_s3/CIN</td>
</tr>
<tr>
<td>5.595</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n15_s3/COUT</td>
</tr>
<tr>
<td>5.595</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n14_s3/CIN</td>
</tr>
<tr>
<td>5.630</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n14_s3/COUT</td>
</tr>
<tr>
<td>5.630</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n13_s3/CIN</td>
</tr>
<tr>
<td>5.665</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n13_s3/COUT</td>
</tr>
<tr>
<td>5.665</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n12_s3/CIN</td>
</tr>
<tr>
<td>5.700</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n12_s3/COUT</td>
</tr>
<tr>
<td>5.700</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n11_s3/CIN</td>
</tr>
<tr>
<td>5.736</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n11_s3/COUT</td>
</tr>
<tr>
<td>5.736</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n10_s2/CIN</td>
</tr>
<tr>
<td>5.771</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>mem0/n10_s2/COUT</td>
</tr>
<tr>
<td>6.008</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5954/I1</td>
</tr>
<tr>
<td>6.563</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>mem0/mem_s5954/F</td>
</tr>
<tr>
<td>6.800</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6164/I2</td>
</tr>
<tr>
<td>7.253</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6164/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5562/I0</td>
</tr>
<tr>
<td>8.007</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5562/F</td>
</tr>
<tr>
<td>8.244</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4756/I0</td>
</tr>
<tr>
<td>8.761</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4756/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[4]_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[4]_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[4]_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>13</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.533, 68.015%; route: 2.370, 29.133%; tC2Q: 0.232, 2.852%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>1.830</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>8.998</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/reg_raddr_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>mem0/mem_mem_RAMREG_37_G[3]_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_raddr_3_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>111</td>
<td>core0/reg_raddr_3_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5980/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>17</td>
<td>mem0/mem_s5980/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n36_s7/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>mem0/n36_s7/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n33_s7/I0</td>
</tr>
<tr>
<td>3.433</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>mem0/n33_s7/F</td>
</tr>
<tr>
<td>3.670</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/I1</td>
</tr>
<tr>
<td>4.225</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n32_s4/F</td>
</tr>
<tr>
<td>4.462</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n31_s3/I1</td>
</tr>
<tr>
<td>5.032</td>
<td>0.570</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>mem0/n31_s3/COUT</td>
</tr>
<tr>
<td>5.032</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>mem0/n30_s3/CIN</td>
</tr>
<tr>
<td>5.067</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>mem0/n30_s3/COUT</td>
</tr>
<tr>
<td>5.067</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n29_s3/CIN</td>
</tr>
<tr>
<td>5.102</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n29_s3/COUT</td>
</tr>
<tr>
<td>5.102</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n28_s3/CIN</td>
</tr>
<tr>
<td>5.137</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n28_s3/COUT</td>
</tr>
<tr>
<td>5.137</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n27_s3/CIN</td>
</tr>
<tr>
<td>5.172</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n27_s3/COUT</td>
</tr>
<tr>
<td>5.172</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n26_s3/CIN</td>
</tr>
<tr>
<td>5.208</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n26_s3/COUT</td>
</tr>
<tr>
<td>5.208</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n25_s3/CIN</td>
</tr>
<tr>
<td>5.243</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n25_s3/COUT</td>
</tr>
<tr>
<td>5.243</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n24_s3/CIN</td>
</tr>
<tr>
<td>5.278</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n24_s3/COUT</td>
</tr>
<tr>
<td>5.278</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n23_s3/CIN</td>
</tr>
<tr>
<td>5.313</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n23_s3/COUT</td>
</tr>
<tr>
<td>5.313</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n22_s3/CIN</td>
</tr>
<tr>
<td>5.348</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n22_s3/COUT</td>
</tr>
<tr>
<td>5.348</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n21_s3/CIN</td>
</tr>
<tr>
<td>5.384</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n21_s3/COUT</td>
</tr>
<tr>
<td>5.384</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n20_s3/CIN</td>
</tr>
<tr>
<td>5.419</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n20_s3/COUT</td>
</tr>
<tr>
<td>5.419</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n19_s3/CIN</td>
</tr>
<tr>
<td>5.454</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n19_s3/COUT</td>
</tr>
<tr>
<td>5.454</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n18_s3/CIN</td>
</tr>
<tr>
<td>5.489</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n18_s3/COUT</td>
</tr>
<tr>
<td>5.489</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n17_s3/CIN</td>
</tr>
<tr>
<td>5.524</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n17_s3/COUT</td>
</tr>
<tr>
<td>5.524</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n16_s3/CIN</td>
</tr>
<tr>
<td>5.560</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n16_s3/COUT</td>
</tr>
<tr>
<td>5.560</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n15_s3/CIN</td>
</tr>
<tr>
<td>5.595</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n15_s3/COUT</td>
</tr>
<tr>
<td>5.595</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n14_s3/CIN</td>
</tr>
<tr>
<td>5.630</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n14_s3/COUT</td>
</tr>
<tr>
<td>5.630</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n13_s3/CIN</td>
</tr>
<tr>
<td>5.665</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n13_s3/COUT</td>
</tr>
<tr>
<td>5.665</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n12_s3/CIN</td>
</tr>
<tr>
<td>5.700</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n12_s3/COUT</td>
</tr>
<tr>
<td>5.700</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n11_s3/CIN</td>
</tr>
<tr>
<td>5.736</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/n11_s3/COUT</td>
</tr>
<tr>
<td>5.736</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>mem0/n10_s2/CIN</td>
</tr>
<tr>
<td>5.771</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>mem0/n10_s2/COUT</td>
</tr>
<tr>
<td>6.008</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5954/I1</td>
</tr>
<tr>
<td>6.563</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>91</td>
<td>mem0/mem_s5954/F</td>
</tr>
<tr>
<td>6.800</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6163/I2</td>
</tr>
<tr>
<td>7.253</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s6163/F</td>
</tr>
<tr>
<td>7.490</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5561/I0</td>
</tr>
<tr>
<td>8.007</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s5561/F</td>
</tr>
<tr>
<td>8.244</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4755/I0</td>
</tr>
<tr>
<td>8.761</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_s4755/F</td>
</tr>
<tr>
<td>8.998</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[3]_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>759</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[3]_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>mem0/mem_mem_RAMREG_37_G[3]_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>13</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 5.533, 68.015%; route: 2.370, 29.133%; tC2Q: 0.232, 2.852%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
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