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2023-05-18 11:45:32 +09:00
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/core.v" type="file.verilog" enable="1"/>
<File path="src/memory.v" type="file.verilog" enable="1"/>
<File path="src/top.v" type="file.verilog" enable="1"/>
<File path="src/uart.v" type="file.verilog" enable="1"/>
<File path="src/uart_tb.v" type="file.verilog" enable="0"/>
<File path="src/cpu.cst" type="file.cst" enable="1"/>
</FileList>
</Project>

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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/cpu.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/cpu.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/cpu.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/cpu.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/cpu.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/cpu.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/cpu.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/cpu.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/cpu_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/cpu_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd0000000200000000000000e1000002e0fc0200000002fc00000037000001290000006200fffffffa000000000200000001fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006200fffffffc00000164000001b30000009301000016fa000000010200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005e00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007c00ffffff0000000300000780000000c2fc0100000003fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000000007800000009b00fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0000000000ffffffff0000005100fffffffc000005050000063b0000000000fffffffa000000000100000001fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff00000000000000000000069b000002e000000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000ffffffff0100000226ffffffff0000000000000000</Ui>
</UserConfig>

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GowinSynthesis start
Running parser ...
Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\memory.v'
Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\top.v'
Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\uart.v'
Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\core.v'
Compiling module 'TOP'("C:\Users\kuroc\Downloads\cpu\src\top.v":1)
Compiling module 'UART'("C:\Users\kuroc\Downloads\cpu\src\uart.v":1)
WARN (EX3791) : Expression size 5 truncated to fit in target size 4("C:\Users\kuroc\Downloads\cpu\src\uart.v":98)
Compiling module 'MEMORY'("C:\Users\kuroc\Downloads\cpu\src\memory.v":1)
Extracting RAM for identifier 'mem'("C:\Users\kuroc\Downloads\cpu\src\memory.v":13)
Compiling module 'CORE'("C:\Users\kuroc\Downloads\cpu\src\core.v":1)
Extracting RAM for identifier 'register'("C:\Users\kuroc\Downloads\cpu\src\core.v":17)
WARN (EX3791) : Expression size 32 truncated to fit in target size 21("C:\Users\kuroc\Downloads\cpu\src\core.v":102)
NOTE (EX0101) : Current top module is "TOP"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg" completed
[100%] Generate report file "C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu_syn.rpt.html" completed
GowinSynthesis finish

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="C:\Users\kuroc\Downloads\cpu\src\memory.v" type="verilog"/>
<File path="C:\Users\kuroc\Downloads\cpu\src\top.v" type="verilog"/>
<File path="C:\Users\kuroc\Downloads\cpu\src\uart.v" type="verilog"/>
<File path="C:\Users\kuroc\Downloads\cpu\src\core.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="dsp_balance" value="0"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="1"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
</tr>
<tr>
<td class="label">TOP (C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--uart0
(C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
<td align = "center">52</td>
<td align = "center">31</td>
<td align = "center">36</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--mem0
(C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
<td align = "center">156</td>
<td align = "center">-</td>
<td align = "center">931</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--core0
(C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
<td align = "center">92</td>
<td align = "center">7</td>
<td align = "center">27</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<Module name="TOP">
<SubModule name="uart0" Register="52" Alu="31" Lut="36"/>
<SubModule name="mem0" Register="156" Lut="931"/>
<SubModule name="core0" Register="92" Alu="7" Lut="27"/>
</Module>

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-d C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg
-p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7
-cst C:\Users\kuroc\Downloads\cpu\src\cpu.cst
-cfg C:\Users\kuroc\Downloads\cpu\impl\pnr\device.cfg
-bit
-tr
-ph
-timing
-cst_error
-route_maxfan 23

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Reading netlist file: "C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg"
Parsing netlist file "C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg" completed
Processing netlist completed
Reading constraint file: "C:\Users\kuroc\Downloads\cpu\src\cpu.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.power.html" completed
Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.pin.html" completed
Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.rpt.html" completed
Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.rpt.txt" completed
Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.tr.html" completed
Thu May 18 11:35:38 2023

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Power Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td {white-space:pre; border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\kuroc\Downloads\cpu\src\cpu.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.09 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu May 18 11:35:38 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>163.969</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>160.429</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>3.540</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>30.250</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>79.750</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Use Vectorless Estimation</td>
<td>false</td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>1.873</td>
<td>101.834</td>
<td>103.707</td>
</tr>
<tr>
<td>VCCX</td>
<td>2.500</td>
<td>0.432</td>
<td>23.366</td>
<td>59.493</td>
</tr>
<tr>
<td>VCCO12</td>
<td>1.200</td>
<td>0.315</td>
<td>0.012</td>
<td>0.393</td>
</tr>
<tr>
<td>VCCO18</td>
<td>1.800</td>
<td>0.116</td>
<td>0.093</td>
<td>0.376</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>Logic</td>
<td>1.432</td>
<td>NA</td>
<td>12.500</td>
</tr>
<tr>
<td>IO</td>
<td>2.651
<td>0.550
<td>41.667
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>TOP</td>
<td>1.432</td>
<td>1.432(1.432)</td>
<tr>
<td>TOP/core0/</td>
<td>0.126</td>
<td>0.126(0.000)</td>
<tr>
<td>TOP/mem0/</td>
<td>1.003</td>
<td>1.003(0.000)</td>
<tr>
<td>TOP/uart0/</td>
<td>0.303</td>
<td>0.303(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>clock</td>
<td>100.000</td>
<td>1.439</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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//Copyright (C)2014-2022 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg
<Physical Constraints File>: C:\Users\kuroc\Downloads\cpu\src\cpu.cst
<Timing Constraints File>: ---
<PnR Version>: V1.9.8.09 Education
<Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18C
<Created Time>:Thu May 18 11:35:38 2023
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.054s, Elapsed time = 0h 0m 0.055s
Placement Phase 1: CPU time = 0h 0m 0.297s, Elapsed time = 0h 0m 0.296s
Placement Phase 2: CPU time = 0h 0m 0.092s, Elapsed time = 0h 0m 0.092s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s
Routing Phase 1: CPU time = 0h 0m 0.153s, Elapsed time = 0h 0m 0.153s
Routing Phase 2: CPU time = 0h 0m 0.926s, Elapsed time = 0h 0m 0.926s
Total Routing: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Generate output files:
CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Total Time and Memory Usage: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 317MB
3. Resource Usage Summary
----------------------------------------------------------
Resources | Usage
----------------------------------------------------------
Logic | 1034/20736 4%
--LUT,ALU,ROM16 | 1034(994 LUT, 40 ALU, 0 ROM16)
--SSRAM(RAM16) | 0
Register | 300/16173 1%
--Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 300/15552 1%
--I/O Register as Latch | 0/621 0%
--I/O Register as FF | 0/621 0%
CLS | 612/10368 5%
I/O Port | 3
I/O Buf | 3
--Input Buf | 1
--Output Buf | 2
--Inout Buf | 0
IOLOGIC | 0%
BSRAM | 0%
DSP | 0%
PLL | 0/4 0%
DCS | 0/8 0%
DQCE | 0/24 0%
OSC | 0/1 0%
CLKDIV | 0/8 0%
DLLDLY | 0/8 0%
DQS | 0/9 0%
DHCEN | 0/16 0%
==========================================================
4. I/O Bank Usage Summary
-----------------------
I/O Bank | Usage
-----------------------
bank 0 | 1/29(3%)
bank 1 | 1/20(5%)
bank 2 | 1/20(5%)
bank 3 | 0/32(0%)
bank 4 | 0/36(0%)
bank 5 | 0/36(0%)
bank 6 | 0/18(0%)
bank 7 | 0/16(0%)
=======================
5. Global Clock Usage Summary
-------------------------------
Global Clock | Usage
-------------------------------
PRIMARY | 1/8(12%)
LW | 0/8(0%)
GCLK_PIN | 1/8(12%)
PLL | 0/4(0%)
CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%)
===============================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
clock_d | PRIMARY | TR
===========================================
7. Pinout by Port Name
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Slew Rate | Vref | Single Resistor | Diff Resistor | BankVccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
clock | | H11/0 | Y | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
LED | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | FAST | NA | NA | NA | 1.8
tx | | M11/2 | Y | out | IOR27[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | FAST | NA | OFF | NA | 1.8
==================================================================================================================================================================================================================
8. All Package Pins
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Slew Rate | Vref | Single Resistor | Diff Resistor | Bank Vccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
H11/0 | clock | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.2
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
L16/1 | - | in | IOT34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
L14/1 | LED | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | FAST | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | - | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A15/7 | - | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B12/7 | - | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | FAST | NA | NA | NA | 1.8
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | 1.8
M11/2 | tx | out | IOR27[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | FAST | NA | OFF | NA | 1.8
T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | NA | -
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
====================================================================================================================================================================================

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<title>Timing Analysis Report</title>
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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impl/pnr/device.cfg Normal file
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set JTAG regular_io = false
set SSPI regular_io = false
set MSPI regular_io = false
set READY regular_io = false
set DONE regular_io = false
set RECONFIG_N regular_io = false
set I2C regular_io = false
set CRC_check = true
set compress = false
set encryption = false
set security_bit_enable = true
set bsram_init_fuse_print = true
set background_programming = off
set secure_mode = false
set program_done_bypass = false
set wake_up = 0
set spi_flash_address = 0x00000000
set format = binary
set power_on_reset_monitor = true
set unused_pin = default

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impl/project_process_config.json Normal file
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{
"Allow_Duplicate_Modules" : false,
"Annotated_Properties_for_Analyst" : true,
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CRC_CHECK" : true,
"Clock_Conversion" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Default_Enum_Encoding" : "default",
"Disable_Insert_Pad" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"FORMAT" : "binary",
"FSM Compiler" : true,
"Fanout_Guide" : 10000,
"Frequency" : "Auto",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"Implicit_Initial_Value_Support" : false,
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"Multiple_File_Compilation_Unit" : true,
"Number_of_Critical_Paths" : "",
"Number_of_Start/End_Points" : "",
"OUTPUT_BASE_NAME" : "cpu",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"Pipelining" : true,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"Push_Tristates" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : true,
"Report_Auto-Placed_Io_Information" : false,
"Resolve_Mixed_Drivers" : false,
"Resource_Sharing" : true,
"Retiming" : false,
"Route_Maxfan" : "23",
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SPI_FLASH_ADDR" : "00000000",
"SSPI" : false,
"Show_All_Warnings" : false,
"Synthesis On/Off Implemented as Translate On/Off" : false,
"Synthesize_tool" : "GowinSyn",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"Update_Compile_Point_Timing_Data" : false,
"Use_Clock_Period_for_Unconstrainted IO" : false,
"Use_SCF" : false,
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"Write_Vendor_Constraint_File" : true,
"dsp_balance" : false,
"show_all_warnings" : false,
"turn_off_bg" : false
}

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impl/temp/rtl_parser.result Normal file
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[
{
"InstFile" : "C:/Users/kuroc/Downloads/cpu/src/top.v",
"InstLine" : 1,
"InstName" : "TOP",
"ModuleFile" : "C:/Users/kuroc/Downloads/cpu/src/top.v",
"ModuleLine" : 1,
"ModuleName" : "TOP",
"SubInsts" : [
{
"InstFile" : "C:/Users/kuroc/Downloads/cpu/src/top.v",
"InstLine" : 11,
"InstName" : "uart0",
"ModuleFile" : "C:/Users/kuroc/Downloads/cpu/src/uart.v",
"ModuleLine" : 1,
"ModuleName" : "UART"
},
{
"InstFile" : "C:/Users/kuroc/Downloads/cpu/src/top.v",
"InstLine" : 26,
"InstName" : "mem0",
"ModuleFile" : "C:/Users/kuroc/Downloads/cpu/src/memory.v",
"ModuleLine" : 1,
"ModuleName" : "MEMORY"
},
{
"InstFile" : "C:/Users/kuroc/Downloads/cpu/src/top.v",
"InstLine" : 36,
"InstName" : "core0",
"ModuleFile" : "C:/Users/kuroc/Downloads/cpu/src/core.v",
"ModuleLine" : 1,
"ModuleName" : "CORE"
}
]
}
]

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impl/temp/rtl_parser_arg.json Normal file
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{
"Files" : [
{
"Path" : "C:/Users/kuroc/Downloads/cpu/src/memory.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/kuroc/Downloads/cpu/src/top.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/kuroc/Downloads/cpu/src/uart.v",
"Type" : "verilog"
},
{
"Path" : "C:/Users/kuroc/Downloads/cpu/src/core.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "C:/Users/kuroc/Downloads/cpu/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

143
src/core.v Normal file
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module CORE(
input clock,
// UART
output tx_start,
output [7:0] tx_data,
// Memory
output [31:0] raddr,
output [31:0] iaddr,
output wen,
output [31:0] wdata,
input [31:0] inst,
input [31:0] rdata
);
reg [31:0] register [31:0];
reg [31:0] REGISTER_TEST;
reg [7:0] reg_tx_data;
reg reg_tx_start;
reg [31:0] pc;
reg [31:0] pc_p4;
reg [31:0] reg_inst;
reg [31:0] reg_iaddr;
reg [31:0] reg_raddr;
reg [31:0] reg_wdata;
reg reg_wen;
reg [6:0] opcode;
reg [4:0] rd;
reg [2:0] funct3;
reg [4:0] rs1;
reg [4:0] rs2;
reg [6:0] funct7;
wire [31:0] rs1_data;
wire [31:0] rs2_data;
reg [11:0] i_imm;
reg [31:0] i_imm_sext;
reg [11:0] s_imm;
reg [31:0] s_imm_sext;
reg [12:0] b_imm;
reg [31:0] u_imm;
reg [20:0] j_imm;
reg [31:0] alu_out;
localparam ST_IF = 0;
localparam ST_ID = 1;
localparam ST_EX = 2;
localparam ST_ACCESS = 3;
localparam ST_WB = 4;
reg [3:0] stage;
integer i;
initial begin
for (i=0;i<32;i=i+1) register[i] <= 31'b0;
register[0] <= 32'b00000000000000000000000000000000;
register[1] <= 32'b00000000000000000000000000000000;
register[2] <= 32'b00000000000000000000000001000001;
pc = 0;
reg_inst = 0;
reg_iaddr = 0;
reg_raddr = 0;
reg_wdata = 0;
reg_wen = 0;
alu_out = 0;
stage = ST_IF;
end
always @(posedge clock) begin
case (stage)
ST_IF: begin
reg_tx_start <= 1;
reg_tx_data <= rdata[31:24];
REGISTER_TEST <= register[1][31:0];
reg_iaddr <= pc;
reg_inst <= inst;
pc_p4 <= pc + 4;
stage <= ST_ID;
end
ST_ID: begin
opcode = reg_inst[0+:7];
rd = reg_inst[7+:5];
funct3 = reg_inst[12+:3];
rs1 <= reg_inst[19:15];
rs2 <= reg_inst[24:20];
funct7 = reg_inst[25+:7];
i_imm <= reg_inst[20+:12];
i_imm_sext <= { {20{i_imm[11]}}, i_imm[10:0] };
s_imm <= { reg_inst[31:25], reg_inst[11:7] };
s_imm_sext <= { {20{s_imm[11]}}, s_imm[10:0] };
b_imm = { reg_inst[25+:7], reg_inst[7+:5] };
u_imm[31:12] = reg_inst[31:12];
j_imm = {{12{reg_inst[31]}}, reg_inst[19:12], reg_inst[20], reg_inst[30:25], reg_inst[24:21], 1'b0};
stage <= ST_EX;
end
ST_EX: begin
alu_out = rs1_data + s_imm;
stage <= ST_ACCESS;
end
ST_ACCESS: begin
reg_raddr = alu_out;
reg_wen = opcode == 7'b0100011;
reg_wdata = rs2_data;
stage <= ST_WB;
end
ST_WB: begin
pc <= pc_p4;
reg_wen <= 0;
reg_raddr = 4;
stage <= ST_IF;
end
endcase
end
assign rs1_data = register[rs1];
assign rs2_data = register[rs2];
assign tx_start = reg_tx_start;
assign tx_data = reg_tx_data;
assign iaddr = reg_iaddr;
assign raddr = reg_raddr;
assign wdata = reg_wdata;
assign wen = reg_wen;
endmodule

14
src/cpu.cst Normal file
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@ -0,0 +1,14 @@
//Copyright (C)2014-2022 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//GOWIN Version: 1.9.8.09 Education
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18C
//Created Time: Mon 05 01 15:09:32 2023
IO_LOC "tx" M11;
IO_PORT "tx" PULL_MODE=UP DRIVE=8;
IO_LOC "LED" L14;
IO_PORT "LED" PULL_MODE=UP DRIVE=8;
IO_LOC "clock" H11;
IO_PORT "clock" PULL_MODE=UP;

55
src/memory.v Normal file
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module MEMORY(
input clock,
input [31:0] raddr,
input [31:0] iaddr,
input wen,
input [31:0] wdata,
output [31:0] inst,
output [31:0] rdata
);
reg [7:0] mem [512:0];
reg [31:0] reg_raddr;
integer i;
initial begin
for (i=0;i<64;i=i+1) mem[i] <= 0;
mem[0] <= 8'b00000000;
mem[1] <= 8'b00100000;
mem[2] <= 8'b10100010;
mem[3] <= 8'b00100011;
mem[0] <= 8'b00000000;
mem[1] <= 8'b00100000;
mem[2] <= 8'b10100010;
mem[3] <= 8'b00100011;
reg_raddr <= 32'b0;
end
always @(posedge clock) begin
if (wen == 1'b1) begin
mem[raddr] = wdata[0 +:8];
mem[raddr+1] = wdata[8 +:8];
mem[raddr+2] = wdata[16 +:8];
mem[raddr+3] = wdata[24 +:8];
end
end
assign inst = {
mem[iaddr+0],
mem[iaddr+1],
mem[iaddr+2],
mem[iaddr+3]
};
assign rdata = {
mem[raddr+0],
mem[raddr+1],
mem[raddr+2],
mem[raddr+3]
};
endmodule

3
src/simulate.bat Normal file
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@ -0,0 +1,3 @@
iverilog -o tb_memory.o uart_tb.v top.v core.v memory.v uart.v
vvp tb_memory.o
gtkwave tb_memory.vcd

705
src/tb_memory.o Normal file
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@ -0,0 +1,705 @@
#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_0000019f8c6f34f0 .scope module, "memory_tb" "memory_tb" 2 1;
.timescale 0 0;
P_0000019f8c6eb620 .param/l "RATE" 0 2 3, +C4<00000000000000000000000000000001>;
v0000019f8c74e980_0 .net "LED", 0 0, L_0000019f8c6e4470; 1 drivers
v0000019f8c74ec00_0 .net "TX", 0 0, L_0000019f8c6e3980; 1 drivers
v0000019f8c74eca0_0 .var "clk", 0 0;
S_0000019f8c6c76a0 .scope module, "top" "TOP" 2 17, 3 1 0, S_0000019f8c6f34f0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /OUTPUT 1 "LED";
.port_info 2 /OUTPUT 1 "tx";
v0000019f8c74eb60_0 .net "LED", 0 0, L_0000019f8c6e4470; alias, 1 drivers
v0000019f8c74d4e0_0 .net "clock", 0 0, v0000019f8c74eca0_0; 1 drivers
v0000019f8c74d940_0 .net "iaddr", 31 0, v0000019f8c74b390_0; 1 drivers
v0000019f8c74de40_0 .net "inst", 31 0, L_0000019f8c7b8af0; 1 drivers
v0000019f8c74d120_0 .net "raddr", 31 0, v0000019f8c74b7f0_0; 1 drivers
v0000019f8c74ee80_0 .net "rdata", 31 0, L_0000019f8c7b8230; 1 drivers
v0000019f8c74d9e0_0 .net "tx", 0 0, L_0000019f8c6e3980; alias, 1 drivers
v0000019f8c74e020_0 .net "tx_busy", 0 0, L_0000019f8c7b9270; 1 drivers
v0000019f8c74e8e0_0 .net "tx_data", 7 0, L_0000019f8c6e39f0; 1 drivers
v0000019f8c74e160_0 .net "tx_start", 0 0, L_0000019f8c6e3c90; 1 drivers
v0000019f8c74da80_0 .net "wdata", 31 0, L_0000019f8c6e3a60; 1 drivers
v0000019f8c74e2a0_0 .net "wen", 0 0, L_0000019f8c6e4400; 1 drivers
S_0000019f8c6c7830 .scope module, "core0" "CORE" 3 36, 4 1 0, S_0000019f8c6c76a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /OUTPUT 1 "tx_start";
.port_info 2 /OUTPUT 8 "tx_data";
.port_info 3 /OUTPUT 32 "raddr";
.port_info 4 /OUTPUT 32 "iaddr";
.port_info 5 /OUTPUT 1 "wen";
.port_info 6 /OUTPUT 32 "wdata";
.port_info 7 /INPUT 32 "inst";
.port_info 8 /INPUT 32 "rdata";
P_0000019f8c6e6290 .param/l "ST_ACCESS" 1 4 54, +C4<00000000000000000000000000000011>;
P_0000019f8c6e62c8 .param/l "ST_EX" 1 4 53, +C4<00000000000000000000000000000010>;
P_0000019f8c6e6300 .param/l "ST_ID" 1 4 52, +C4<00000000000000000000000000000001>;
P_0000019f8c6e6338 .param/l "ST_IF" 1 4 51, +C4<00000000000000000000000000000000>;
P_0000019f8c6e6370 .param/l "ST_WB" 1 4 55, +C4<00000000000000000000000000000100>;
L_0000019f8c6e3bb0 .functor BUFZ 32, L_0000019f8c7b8a50, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
L_0000019f8c6e3ec0 .functor BUFZ 32, L_0000019f8c7b8730, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
L_0000019f8c6e3c90 .functor BUFZ 1, v0000019f8c74cf10_0, C4<0>, C4<0>, C4<0>;
L_0000019f8c6e39f0 .functor BUFZ 8, v0000019f8c74c790_0, C4<00000000>, C4<00000000>, C4<00000000>;
L_0000019f8c6e3a60 .functor BUFZ 32, v0000019f8c74ba70_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
L_0000019f8c6e4400 .functor BUFZ 1, v0000019f8c74b4d0_0, C4<0>, C4<0>, C4<0>;
v0000019f8c6df580_0 .var "REGISTER_TEST", 31 0;
v0000019f8c6de860_0 .net *"_ivl_0", 31 0, L_0000019f8c7b8a50; 1 drivers
v0000019f8c6def40_0 .net *"_ivl_10", 6 0, L_0000019f8c7b8550; 1 drivers
L_0000019f8c7603e8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000019f8c6de900_0 .net *"_ivl_13", 1 0, L_0000019f8c7603e8; 1 drivers
v0000019f8c6deea0_0 .net *"_ivl_2", 6 0, L_0000019f8c7b9a90; 1 drivers
L_0000019f8c7603a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
v0000019f8c6decc0_0 .net *"_ivl_5", 1 0, L_0000019f8c7603a0; 1 drivers
v0000019f8c6df620_0 .net *"_ivl_8", 31 0, L_0000019f8c7b8730; 1 drivers
v0000019f8c6df080_0 .var "alu_out", 31 0;
v0000019f8c6de9a0_0 .var "b_imm", 12 0;
v0000019f8c6deb80_0 .net "clock", 0 0, v0000019f8c74eca0_0; alias, 1 drivers
v0000019f8c6dea40_0 .var "funct3", 2 0;
v0000019f8c6dec20_0 .var "funct7", 6 0;
v0000019f8c74b9d0_0 .var/i "i", 31 0;
v0000019f8c74b250_0 .var "i_imm", 11 0;
v0000019f8c74c330_0 .var "i_imm_sext", 31 0;
v0000019f8c74c6f0_0 .net "iaddr", 31 0, v0000019f8c74b390_0; alias, 1 drivers
v0000019f8c74b6b0_0 .net "inst", 31 0, L_0000019f8c7b8af0; alias, 1 drivers
v0000019f8c74b070_0 .var "j_imm", 20 0;
v0000019f8c74cbf0_0 .var "opcode", 6 0;
v0000019f8c74cc90_0 .var "pc", 31 0;
v0000019f8c74cdd0_0 .var "pc_p4", 31 0;
v0000019f8c74ca10_0 .net "raddr", 31 0, v0000019f8c74b7f0_0; alias, 1 drivers
v0000019f8c74b430_0 .var "rd", 4 0;
v0000019f8c74ce70_0 .net "rdata", 31 0, L_0000019f8c7b8230; alias, 1 drivers
v0000019f8c74b390_0 .var "reg_iaddr", 31 0;
v0000019f8c74c5b0_0 .var "reg_inst", 31 0;
v0000019f8c74b7f0_0 .var "reg_raddr", 31 0;
v0000019f8c74c790_0 .var "reg_tx_data", 7 0;
v0000019f8c74cf10_0 .var "reg_tx_start", 0 0;
v0000019f8c74ba70_0 .var "reg_wdata", 31 0;
v0000019f8c74b4d0_0 .var "reg_wen", 0 0;
v0000019f8c74b750 .array "register", 0 31, 31 0;
v0000019f8c74cab0_0 .var "rs1", 4 0;
v0000019f8c74bf70_0 .net "rs1_data", 31 0, L_0000019f8c6e3bb0; 1 drivers
v0000019f8c74bcf0_0 .var "rs2", 4 0;
v0000019f8c74be30_0 .net "rs2_data", 31 0, L_0000019f8c6e3ec0; 1 drivers
v0000019f8c74c510_0 .var "s_imm", 11 0;
v0000019f8c74c830_0 .var "s_imm_sext", 31 0;
v0000019f8c74b890_0 .var "stage", 3 0;
v0000019f8c74b930_0 .net "tx_data", 7 0, L_0000019f8c6e39f0; alias, 1 drivers
v0000019f8c74bb10_0 .net "tx_start", 0 0, L_0000019f8c6e3c90; alias, 1 drivers
v0000019f8c74c8d0_0 .var "u_imm", 31 0;
v0000019f8c74c970_0 .net "wdata", 31 0, L_0000019f8c6e3a60; alias, 1 drivers
v0000019f8c74c0b0_0 .net "wen", 0 0, L_0000019f8c6e4400; alias, 1 drivers
E_0000019f8c6ebb20 .event posedge, v0000019f8c6deb80_0;
L_0000019f8c7b8a50 .array/port v0000019f8c74b750, L_0000019f8c7b9a90;
L_0000019f8c7b9a90 .concat [ 5 2 0 0], v0000019f8c74cab0_0, L_0000019f8c7603a0;
L_0000019f8c7b8730 .array/port v0000019f8c74b750, L_0000019f8c7b8550;
L_0000019f8c7b8550 .concat [ 5 2 0 0], v0000019f8c74bcf0_0, L_0000019f8c7603e8;
S_0000019f8c6a6d00 .scope module, "mem0" "MEMORY" 3 26, 5 1 0, S_0000019f8c6c76a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /INPUT 32 "raddr";
.port_info 2 /INPUT 32 "iaddr";
.port_info 3 /INPUT 1 "wen";
.port_info 4 /INPUT 32 "wdata";
.port_info 5 /OUTPUT 32 "inst";
.port_info 6 /OUTPUT 32 "rdata";
v0000019f8c74bed0_0 .net *"_ivl_0", 7 0, L_0000019f8c7b8d70; 1 drivers
v0000019f8c74bd90_0 .net *"_ivl_10", 31 0, L_0000019f8c7b96d0; 1 drivers
v0000019f8c74cb50_0 .net *"_ivl_12", 7 0, L_0000019f8c7b8870; 1 drivers
L_0000019f8c7601f0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
v0000019f8c74cd30_0 .net/2u *"_ivl_14", 31 0, L_0000019f8c7601f0; 1 drivers
v0000019f8c74b110_0 .net *"_ivl_16", 31 0, L_0000019f8c7b9770; 1 drivers
v0000019f8c74c010_0 .net *"_ivl_18", 7 0, L_0000019f8c7b9450; 1 drivers
L_0000019f8c760160 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000019f8c74bbb0_0 .net/2u *"_ivl_2", 31 0, L_0000019f8c760160; 1 drivers
L_0000019f8c760238 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>;
v0000019f8c74c150_0 .net/2u *"_ivl_20", 31 0, L_0000019f8c760238; 1 drivers
v0000019f8c74b1b0_0 .net *"_ivl_22", 31 0, L_0000019f8c7b9b30; 1 drivers
v0000019f8c74c1f0_0 .net *"_ivl_26", 7 0, L_0000019f8c7b98b0; 1 drivers
L_0000019f8c760280 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000019f8c74b2f0_0 .net/2u *"_ivl_28", 31 0, L_0000019f8c760280; 1 drivers
v0000019f8c74c290_0 .net *"_ivl_30", 31 0, L_0000019f8c7b93b0; 1 drivers
v0000019f8c74b570_0 .net *"_ivl_32", 7 0, L_0000019f8c7b87d0; 1 drivers
L_0000019f8c7602c8 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
v0000019f8c74bc50_0 .net/2u *"_ivl_34", 31 0, L_0000019f8c7602c8; 1 drivers
v0000019f8c74b610_0 .net *"_ivl_36", 31 0, L_0000019f8c7b8b90; 1 drivers
v0000019f8c74c3d0_0 .net *"_ivl_38", 7 0, L_0000019f8c7b9810; 1 drivers
v0000019f8c74c470_0 .net *"_ivl_4", 31 0, L_0000019f8c7b9c70; 1 drivers
L_0000019f8c760310 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
v0000019f8c74c650_0 .net/2u *"_ivl_40", 31 0, L_0000019f8c760310; 1 drivers
v0000019f8c74d260_0 .net *"_ivl_42", 31 0, L_0000019f8c7b89b0; 1 drivers
v0000019f8c74eac0_0 .net *"_ivl_44", 7 0, L_0000019f8c7b91d0; 1 drivers
L_0000019f8c760358 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>;
v0000019f8c74d6c0_0 .net/2u *"_ivl_46", 31 0, L_0000019f8c760358; 1 drivers
v0000019f8c74d800_0 .net *"_ivl_48", 31 0, L_0000019f8c7b8190; 1 drivers
v0000019f8c74dee0_0 .net *"_ivl_6", 7 0, L_0000019f8c7b8e10; 1 drivers
L_0000019f8c7601a8 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
v0000019f8c74db20_0 .net/2u *"_ivl_8", 31 0, L_0000019f8c7601a8; 1 drivers
v0000019f8c74e480_0 .net "clock", 0 0, v0000019f8c74eca0_0; alias, 1 drivers
v0000019f8c74ede0_0 .var/i "i", 31 0;
v0000019f8c74e200_0 .net "iaddr", 31 0, v0000019f8c74b390_0; alias, 1 drivers
v0000019f8c74d3a0_0 .net "inst", 31 0, L_0000019f8c7b8af0; alias, 1 drivers
v0000019f8c74ed40 .array "mem", 0 64, 7 0;
v0000019f8c74e520_0 .net "raddr", 31 0, v0000019f8c74b7f0_0; alias, 1 drivers
v0000019f8c74dbc0_0 .net "rdata", 31 0, L_0000019f8c7b8230; alias, 1 drivers
v0000019f8c74d580_0 .var "reg_raddr", 31 0;
v0000019f8c74dc60_0 .net "wdata", 31 0, L_0000019f8c6e3a60; alias, 1 drivers
v0000019f8c74dd00_0 .net "wen", 0 0, L_0000019f8c6e4400; alias, 1 drivers
L_0000019f8c7b8d70 .array/port v0000019f8c74ed40, L_0000019f8c7b9c70;
L_0000019f8c7b9c70 .arith/sum 32, v0000019f8c74b390_0, L_0000019f8c760160;
L_0000019f8c7b8e10 .array/port v0000019f8c74ed40, L_0000019f8c7b96d0;
L_0000019f8c7b96d0 .arith/sum 32, v0000019f8c74b390_0, L_0000019f8c7601a8;
L_0000019f8c7b8870 .array/port v0000019f8c74ed40, L_0000019f8c7b9770;
L_0000019f8c7b9770 .arith/sum 32, v0000019f8c74b390_0, L_0000019f8c7601f0;
L_0000019f8c7b9450 .array/port v0000019f8c74ed40, L_0000019f8c7b9b30;
L_0000019f8c7b9b30 .arith/sum 32, v0000019f8c74b390_0, L_0000019f8c760238;
L_0000019f8c7b8af0 .concat [ 8 8 8 8], L_0000019f8c7b9450, L_0000019f8c7b8870, L_0000019f8c7b8e10, L_0000019f8c7b8d70;
L_0000019f8c7b98b0 .array/port v0000019f8c74ed40, L_0000019f8c7b93b0;
L_0000019f8c7b93b0 .arith/sum 32, v0000019f8c74b7f0_0, L_0000019f8c760280;
L_0000019f8c7b87d0 .array/port v0000019f8c74ed40, L_0000019f8c7b8b90;
L_0000019f8c7b8b90 .arith/sum 32, v0000019f8c74b7f0_0, L_0000019f8c7602c8;
L_0000019f8c7b9810 .array/port v0000019f8c74ed40, L_0000019f8c7b89b0;
L_0000019f8c7b89b0 .arith/sum 32, v0000019f8c74b7f0_0, L_0000019f8c760310;
L_0000019f8c7b91d0 .array/port v0000019f8c74ed40, L_0000019f8c7b8190;
L_0000019f8c7b8190 .arith/sum 32, v0000019f8c74b7f0_0, L_0000019f8c760358;
L_0000019f8c7b8230 .concat [ 8 8 8 8], L_0000019f8c7b91d0, L_0000019f8c7b9810, L_0000019f8c7b87d0, L_0000019f8c7b98b0;
S_0000019f8c6bf0e0 .scope module, "uart0" "UART" 3 11, 6 1 0, S_0000019f8c6c76a0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /INPUT 8 "data_in";
.port_info 2 /INPUT 1 "start";
.port_info 3 /OUTPUT 1 "tx_busy";
.port_info 4 /OUTPUT 1 "tx";
.port_info 5 /OUTPUT 1 "LED";
P_0000019f8c6a6fd0 .param/l "FPGA_FREQ" 1 6 13, +C4<00000000000000000000000000011011>;
P_0000019f8c6a7008 .param/l "S_END" 1 6 43, +C4<00000000000000000000000000000100>;
P_0000019f8c6a7040 .param/l "S_IDLE" 1 6 39, +C4<00000000000000000000000000000000>;
P_0000019f8c6a7078 .param/l "S_P" 1 6 42, +C4<00000000000000000000000000000011>;
P_0000019f8c6a70b0 .param/l "S_SEND" 1 6 41, +C4<00000000000000000000000000000010>;
P_0000019f8c6a70e8 .param/l "S_START" 1 6 40, +C4<00000000000000000000000000000001>;
P_0000019f8c6a7120 .param/l "TX_CLOCK_COUNT_MAX" 1 6 15, +C4<00000000000000000000000000000000000000000000000000000000011101001>;
P_0000019f8c6a7158 .param/l "UART_FREQ" 1 6 14, +C4<00000000000000011100001000000000>;
L_0000019f8c6e4470 .functor BUFZ 1, v0000019f8c74d8a0_0, C4<0>, C4<0>, C4<0>;
L_0000019f8c6e3980 .functor BUFZ 1, v0000019f8c74d440_0, C4<0>, C4<0>, C4<0>;
v0000019f8c74e5c0_0 .net "LED", 0 0, L_0000019f8c6e4470; alias, 1 drivers
L_0000019f8c7600d0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000019f8c74df80_0 .net *"_ivl_11", 26 0, L_0000019f8c7600d0; 1 drivers
L_0000019f8c760118 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000019f8c74d300_0 .net/2u *"_ivl_12", 31 0, L_0000019f8c760118; 1 drivers
L_0000019f8c760088 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
v0000019f8c74e0c0_0 .net/2u *"_ivl_2", 31 0, L_0000019f8c760088; 1 drivers
v0000019f8c74e7a0_0 .net *"_ivl_8", 31 0, L_0000019f8c7b9130; 1 drivers
v0000019f8c74ea20_0 .net "clock", 0 0, v0000019f8c74eca0_0; alias, 1 drivers
v0000019f8c74e660_0 .var "clock_count", 31 0;
v0000019f8c74e700_0 .var "data", 7 0;
v0000019f8c74e840_0 .net "data_in", 7 0, L_0000019f8c6e39f0; alias, 1 drivers
v0000019f8c74d8a0_0 .var "led_flag", 0 0;
v0000019f8c74d620_0 .var "local_in", 7 0;
v0000019f8c74d080_0 .var "local_start", 0 0;
v0000019f8c74d1c0_0 .var "send_count", 3 0;
v0000019f8c74d760_0 .net "start", 0 0, L_0000019f8c6e3c90; alias, 1 drivers
v0000019f8c74e340_0 .var "state", 4 0;
v0000019f8c74e3e0_0 .net "tx", 0 0, L_0000019f8c6e3980; alias, 1 drivers
v0000019f8c74ef20_0 .net "tx_busy", 0 0, L_0000019f8c7b9270; alias, 1 drivers
v0000019f8c74dda0_0 .net "tx_clock", 0 0, L_0000019f8c7b99f0; 1 drivers
v0000019f8c74d440_0 .var "tx_reg", 0 0;
L_0000019f8c7b99f0 .cmp/eq 32, v0000019f8c74e660_0, L_0000019f8c760088;
L_0000019f8c7b9130 .concat [ 5 27 0 0], v0000019f8c74e340_0, L_0000019f8c7600d0;
L_0000019f8c7b9270 .cmp/ne 32, L_0000019f8c7b9130, L_0000019f8c760118;
.scope S_0000019f8c6bf0e0;
T_0 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000019f8c74e660_0, 0, 32;
%end;
.thread T_0;
.scope S_0000019f8c6bf0e0;
T_1 ;
%wait E_0000019f8c6ebb20;
%load/vec4 v0000019f8c74e660_0;
%pad/u 65;
%cmpi/e 233, 0, 65;
%jmp/0xz T_1.0, 4;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0000019f8c74e660_0, 0;
%load/vec4 v0000019f8c74d8a0_0;
%inv;
%assign/vec4 v0000019f8c74d8a0_0, 0;
%jmp T_1.1;
T_1.0 ;
%load/vec4 v0000019f8c74e660_0;
%addi 1, 0, 32;
%assign/vec4 v0000019f8c74e660_0, 0;
T_1.1 ;
%jmp T_1;
.thread T_1;
.scope S_0000019f8c6bf0e0;
T_2 ;
%wait E_0000019f8c6ebb20;
%load/vec4 v0000019f8c74e840_0;
%assign/vec4 v0000019f8c74d620_0, 0;
%load/vec4 v0000019f8c74d760_0;
%assign/vec4 v0000019f8c74d080_0, 0;
%jmp T_2;
.thread T_2;
.scope S_0000019f8c6bf0e0;
T_3 ;
%pushi/vec4 0, 0, 5;
%store/vec4 v0000019f8c74e340_0, 0, 5;
%pushi/vec4 0, 0, 4;
%store/vec4 v0000019f8c74d1c0_0, 0, 4;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000019f8c74d440_0, 0, 1;
%end;
.thread T_3;
.scope S_0000019f8c6bf0e0;
T_4 ;
%wait E_0000019f8c6ebb20;
%load/vec4 v0000019f8c74e340_0;
%dup/vec4;
%pushi/vec4 0, 0, 5;
%cmp/u;
%jmp/1 T_4.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 5;
%cmp/u;
%jmp/1 T_4.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 5;
%cmp/u;
%jmp/1 T_4.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 5;
%cmp/u;
%jmp/1 T_4.3, 6;
%dup/vec4;
%pushi/vec4 4, 0, 5;
%cmp/u;
%jmp/1 T_4.4, 6;
%jmp T_4.5;
T_4.0 ;
%load/vec4 v0000019f8c74dda0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.6, 8;
%load/vec4 v0000019f8c74d080_0;
%flag_set/vec4 8;
%jmp/0xz T_4.8, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%pushi/vec4 1, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
%jmp T_4.9;
T_4.8 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%pushi/vec4 0, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
T_4.9 ;
T_4.6 ;
%jmp T_4.5;
T_4.1 ;
%load/vec4 v0000019f8c74dda0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.10, 8;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%load/vec4 v0000019f8c74d620_0;
%assign/vec4 v0000019f8c74e700_0, 0;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0000019f8c74d1c0_0, 0;
%pushi/vec4 2, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
%jmp T_4.11;
T_4.10 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%pushi/vec4 1, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
T_4.11 ;
%jmp T_4.5;
T_4.2 ;
%load/vec4 v0000019f8c74dda0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.12, 8;
%load/vec4 v0000019f8c74e700_0;
%load/vec4 v0000019f8c74d1c0_0;
%part/u 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%load/vec4 v0000019f8c74d1c0_0;
%cmpi/e 7, 0, 4;
%jmp/0xz T_4.14, 4;
%pushi/vec4 3, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
%jmp T_4.15;
T_4.14 ;
%load/vec4 v0000019f8c74d1c0_0;
%addi 1, 0, 4;
%assign/vec4 v0000019f8c74d1c0_0, 0;
%pushi/vec4 2, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
T_4.15 ;
%jmp T_4.13;
T_4.12 ;
%load/vec4 v0000019f8c74e700_0;
%load/vec4 v0000019f8c74d1c0_0;
%part/u 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%pushi/vec4 2, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
T_4.13 ;
%jmp T_4.5;
T_4.3 ;
%load/vec4 v0000019f8c74dda0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.16, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%pushi/vec4 4, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
%jmp T_4.17;
T_4.16 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%pushi/vec4 3, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
T_4.17 ;
%jmp T_4.5;
T_4.4 ;
%load/vec4 v0000019f8c74dda0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.18, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%pushi/vec4 0, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
%jmp T_4.19;
T_4.18 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000019f8c74d440_0, 0;
%pushi/vec4 4, 0, 5;
%assign/vec4 v0000019f8c74e340_0, 0;
T_4.19 ;
%jmp T_4.5;
T_4.5 ;
%pop/vec4 1;
%jmp T_4;
.thread T_4;
.scope S_0000019f8c6a6d00;
T_5 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000019f8c74ede0_0, 0, 32;
T_5.0 ;
%load/vec4 v0000019f8c74ede0_0;
%cmpi/s 64, 0, 32;
%jmp/0xz T_5.1, 5;
%pushi/vec4 0, 0, 8;
%ix/getv/s 3, v0000019f8c74ede0_0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000019f8c74ed40, 0, 4;
%load/vec4 v0000019f8c74ede0_0;
%addi 1, 0, 32;
%store/vec4 v0000019f8c74ede0_0, 0, 32;
%jmp T_5.0;
T_5.1 ;
%pushi/vec4 0, 0, 8;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000019f8c74ed40, 0, 4;
%pushi/vec4 32, 0, 8;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000019f8c74ed40, 0, 4;
%pushi/vec4 162, 0, 8;
%ix/load 3, 2, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000019f8c74ed40, 0, 4;
%pushi/vec4 35, 0, 8;
%ix/load 3, 3, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000019f8c74ed40, 0, 4;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0000019f8c74d580_0, 0;
%end;
.thread T_5;
.scope S_0000019f8c6a6d00;
T_6 ;
%wait E_0000019f8c6ebb20;
%load/vec4 v0000019f8c74dd00_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_6.0, 4;
%load/vec4 v0000019f8c74dc60_0;
%parti/s 8, 0, 2;
%ix/getv 4, v0000019f8c74e520_0;
%store/vec4a v0000019f8c74ed40, 4, 0;
%load/vec4 v0000019f8c74dc60_0;
%parti/s 8, 8, 5;
%load/vec4 v0000019f8c74e520_0;
%addi 1, 0, 32;
%ix/vec4 4;
%store/vec4a v0000019f8c74ed40, 4, 0;
%load/vec4 v0000019f8c74dc60_0;
%parti/s 8, 16, 6;
%load/vec4 v0000019f8c74e520_0;
%addi 2, 0, 32;
%ix/vec4 4;
%store/vec4a v0000019f8c74ed40, 4, 0;
%load/vec4 v0000019f8c74dc60_0;
%parti/s 8, 24, 6;
%load/vec4 v0000019f8c74e520_0;
%addi 3, 0, 32;
%ix/vec4 4;
%store/vec4a v0000019f8c74ed40, 4, 0;
T_6.0 ;
%jmp T_6;
.thread T_6;
.scope S_0000019f8c6c7830;
T_7 ;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000019f8c74b9d0_0, 0, 32;
T_7.0 ;
%load/vec4 v0000019f8c74b9d0_0;
%cmpi/s 32, 0, 32;
%jmp/0xz T_7.1, 5;
%pushi/vec4 0, 0, 32;
%ix/getv/s 3, v0000019f8c74b9d0_0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000019f8c74b750, 0, 4;
%load/vec4 v0000019f8c74b9d0_0;
%addi 1, 0, 32;
%store/vec4 v0000019f8c74b9d0_0, 0, 32;
%jmp T_7.0;
T_7.1 ;
%pushi/vec4 0, 0, 32;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000019f8c74b750, 0, 4;
%pushi/vec4 0, 0, 32;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000019f8c74b750, 0, 4;
%pushi/vec4 65, 0, 32;
%ix/load 3, 2, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
%assign/vec4/a/d v0000019f8c74b750, 0, 4;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000019f8c74cc90_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000019f8c74c5b0_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000019f8c74b390_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000019f8c74b7f0_0, 0, 32;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000019f8c74ba70_0, 0, 32;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000019f8c74b4d0_0, 0, 1;
%pushi/vec4 0, 0, 32;
%store/vec4 v0000019f8c6df080_0, 0, 32;
%pushi/vec4 0, 0, 4;
%store/vec4 v0000019f8c74b890_0, 0, 4;
%end;
.thread T_7;
.scope S_0000019f8c6c7830;
T_8 ;
%wait E_0000019f8c6ebb20;
%load/vec4 v0000019f8c74b890_0;
%dup/vec4;
%pushi/vec4 0, 0, 4;
%cmp/u;
%jmp/1 T_8.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 4;
%cmp/u;
%jmp/1 T_8.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_8.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 4;
%cmp/u;
%jmp/1 T_8.3, 6;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_8.4, 6;
%jmp T_8.5;
T_8.0 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0000019f8c74cf10_0, 0;
%load/vec4 v0000019f8c74ce70_0;
%parti/s 8, 24, 6;
%assign/vec4 v0000019f8c74c790_0, 0;
%ix/load 4, 1, 0;
%flag_set/imm 4, 0;
%load/vec4a v0000019f8c74b750, 4;
%assign/vec4 v0000019f8c6df580_0, 0;
%load/vec4 v0000019f8c74cc90_0;
%assign/vec4 v0000019f8c74b390_0, 0;
%load/vec4 v0000019f8c74b6b0_0;
%assign/vec4 v0000019f8c74c5b0_0, 0;
%load/vec4 v0000019f8c74cc90_0;
%addi 4, 0, 32;
%assign/vec4 v0000019f8c74cdd0_0, 0;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0000019f8c74b890_0, 0;
%jmp T_8.5;
T_8.1 ;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 7, 0, 2;
%store/vec4 v0000019f8c74cbf0_0, 0, 7;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 5, 7, 4;
%store/vec4 v0000019f8c74b430_0, 0, 5;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 3, 12, 5;
%store/vec4 v0000019f8c6dea40_0, 0, 3;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 5, 15, 5;
%assign/vec4 v0000019f8c74cab0_0, 0;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 5, 20, 6;
%assign/vec4 v0000019f8c74bcf0_0, 0;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 7, 25, 6;
%store/vec4 v0000019f8c6dec20_0, 0, 7;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 12, 20, 6;
%assign/vec4 v0000019f8c74b250_0, 0;
%load/vec4 v0000019f8c74b250_0;
%parti/s 1, 11, 5;
%replicate 20;
%load/vec4 v0000019f8c74b250_0;
%parti/s 11, 0, 2;
%concat/vec4; draw_concat_vec4
%pad/u 32;
%assign/vec4 v0000019f8c74c330_0, 0;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 7, 25, 6;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 5, 7, 4;
%concat/vec4; draw_concat_vec4
%assign/vec4 v0000019f8c74c510_0, 0;
%load/vec4 v0000019f8c74c510_0;
%parti/s 1, 11, 5;
%replicate 20;
%load/vec4 v0000019f8c74c510_0;
%parti/s 11, 0, 2;
%concat/vec4; draw_concat_vec4
%pad/u 32;
%assign/vec4 v0000019f8c74c830_0, 0;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 7, 25, 6;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 5, 7, 4;
%concat/vec4; draw_concat_vec4
%pad/u 13;
%store/vec4 v0000019f8c6de9a0_0, 0, 13;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 20, 12, 5;
%ix/load 4, 12, 0;
%flag_set/imm 4, 0;
%store/vec4 v0000019f8c74c8d0_0, 4, 20;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 1, 31, 6;
%replicate 12;
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 8, 12, 5;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 1, 20, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 6, 25, 6;
%concat/vec4; draw_concat_vec4
%load/vec4 v0000019f8c74c5b0_0;
%parti/s 4, 21, 6;
%concat/vec4; draw_concat_vec4
%concati/vec4 0, 0, 1;
%pad/u 21;
%store/vec4 v0000019f8c74b070_0, 0, 21;
%pushi/vec4 2, 0, 4;
%assign/vec4 v0000019f8c74b890_0, 0;
%jmp T_8.5;
T_8.2 ;
%load/vec4 v0000019f8c74bf70_0;
%load/vec4 v0000019f8c74c510_0;
%pad/u 32;
%add;
%store/vec4 v0000019f8c6df080_0, 0, 32;
%pushi/vec4 3, 0, 4;
%assign/vec4 v0000019f8c74b890_0, 0;
%jmp T_8.5;
T_8.3 ;
%load/vec4 v0000019f8c6df080_0;
%store/vec4 v0000019f8c74b7f0_0, 0, 32;
%load/vec4 v0000019f8c74cbf0_0;
%pushi/vec4 35, 0, 7;
%cmp/e;
%flag_get/vec4 4;
%store/vec4 v0000019f8c74b4d0_0, 0, 1;
%load/vec4 v0000019f8c74be30_0;
%store/vec4 v0000019f8c74ba70_0, 0, 32;
%pushi/vec4 4, 0, 4;
%assign/vec4 v0000019f8c74b890_0, 0;
%jmp T_8.5;
T_8.4 ;
%load/vec4 v0000019f8c74cdd0_0;
%assign/vec4 v0000019f8c74cc90_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0000019f8c74b4d0_0, 0;
%pushi/vec4 4, 0, 32;
%store/vec4 v0000019f8c74b7f0_0, 0, 32;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0000019f8c74b890_0, 0;
%jmp T_8.5;
T_8.5 ;
%pop/vec4 1;
%jmp T_8;
.thread T_8;
.scope S_0000019f8c6f34f0;
T_9 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000019f8c74eca0_0, 0, 1;
%end;
.thread T_9;
.scope S_0000019f8c6f34f0;
T_10 ;
%vpi_call 2 6 "$dumpfile", "tb_memory.vcd" {0 0 0};
%vpi_call 2 7 "$dumpvars", 32'sb00000000000000000000000000000011, S_0000019f8c6f34f0 {0 0 0};
%delay 10000, 0;
%vpi_call 2 9 "$finish" {0 0 0};
%end;
.thread T_10;
.scope S_0000019f8c6f34f0;
T_11 ;
%delay 1, 0;
%load/vec4 v0000019f8c74eca0_0;
%nor/r;
%store/vec4 v0000019f8c74eca0_0, 0, 1;
%jmp T_11;
.thread T_11;
# The file index is used to find the file name in the following table.
:file_names 7;
"N/A";
"<interactive>";
"uart_tb.v";
"top.v";
"core.v";
"memory.v";
"uart.v";

54300
src/tb_memory.vcd Normal file
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97
src/top.v Normal file
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@ -0,0 +1,97 @@
module TOP(
input clock,
output LED,
output tx
);
wire tx_busy;
wire tx_start;
wire [7:0] tx_data;
UART uart0(
.clock(clock),
.tx(tx),
.tx_busy(tx_busy),
.start(tx_start),
.data_in(tx_data),
.LED(LED)
);
wire [31:0] inst;
wire [31:0] rdata;
wire [31:0] raddr;
wire [31:0] iaddr;
wire [31:0] wdata;
wire wen;
MEMORY mem0(
.clock(clock),
.raddr(raddr),
.iaddr(iaddr),
.wen(wen),
.wdata(wdata),
.inst(inst),
.rdata(rdata)
);
CORE core0(
.clock(clock),
.tx_start(tx_start),
.tx_data(tx_data),
.raddr(raddr),
.iaddr(iaddr),
.wen(wen),
.wdata(wdata),
.inst(inst),
.rdata(rdata)
);
/*
localparam MEM_WRITE = 0;
localparam MEM_READ = 1;
localparam MEM_IDLE = 2;
localparam WAIT_TIME = 200000;
reg [31:0] clock_count;
reg [7:0] send_count;
reg [3:0] state;
wire [4 * 8:0] str = "test";
initial begin
clock_count = WAIT_TIME;
send_count = 0;
state = MEM_WRITE;
tx_start = 1'b0;
tx_data = 8'b0;
end
always @(posedge clock) begin
if (clock_count == WAIT_TIME) begin
case (state)
MEM_WRITE: begin
raddr <= 32'b0;
wdata <= "C";
wen <= 1'b1;
state <= MEM_READ;
end
MEM_READ: begin
wen <= 1'b0;
raddr <= 32'b0;
if (tx_busy == 1'b0) begin
tx_data <= rdata[0 +:8];
tx_start <= 1'b1;
end
state <= MEM_IDLE;
end
MEM_IDLE:
state <= MEM_WRITE;
endcase
clock_count <= 0;
end else begin
clock_count <= clock_count + 1;
tx_start <= 1'b1;
end
end*/
endmodule

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module UART(
input clock,
input [7:0] data_in,
input start,
output tx_busy,
output tx,
output LED
);
// UART Clock
localparam FPGA_FREQ = 27; // MHz
localparam UART_FREQ = 115200;
localparam TX_CLOCK_COUNT_MAX = FPGA_FREQ * 1000000 / UART_FREQ - 1;
reg [31:0] clock_count;
reg led_flag;
assign LED = led_flag;
wire tx_clock = (clock_count == 0);
initial begin
clock_count = 0;
end
always @(posedge clock) begin
if (clock_count == TX_CLOCK_COUNT_MAX) begin
clock_count <= 0;
led_flag <= ~led_flag;
end else begin
clock_count <= clock_count + 1;
end
end
// State Machine
localparam S_IDLE = 0;
localparam S_START = 1;
localparam S_SEND = 2;
localparam S_P = 3;
localparam S_END = 4;
reg [4:0] state;
reg [3:0] send_count;
reg tx_reg;
reg [7:0] data;
reg [7:0] local_in;
reg local_start;
assign tx = tx_reg;
always @(posedge clock) begin
local_in <= data_in;
local_start <= start;
end
assign tx_busy = (state != S_IDLE);
initial begin
state = S_IDLE;
send_count = 0;
tx_reg = 1'b1;
end
always @(posedge clock) begin
case (state)
S_IDLE:
if (tx_clock) begin
if (local_start) begin
tx_reg <= 1'b1;
state <= S_START;
end else begin
tx_reg <= 1'b1;
state <= S_IDLE;
end
end
S_START:
if (tx_clock) begin
tx_reg <= 1'b0;
data <= local_in;
send_count <= 0;
state <= S_SEND;
end else begin
tx_reg <= 1'b0;
state <= S_START;
end
S_SEND:
if (tx_clock) begin
tx_reg <= data[send_count];
if (send_count == 3'd7) begin
state <= S_P;
end else begin
send_count <= send_count + 1;
state <= S_SEND;
end
end else begin
tx_reg <= data[send_count];
state <= S_SEND;
end
S_P:
if (tx_clock) begin
tx_reg <= 1'b1;
state <= S_END;
end else begin
tx_reg <= 1'b1;
state <= S_P;
end
S_END:
if (tx_clock) begin
tx_reg <= 1'b1;
state <= S_IDLE;
end else begin
tx_reg <= 1'b1;
state <= S_END;
end
endcase
end
endmodule

23
src/uart_tb.v Normal file
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@ -0,0 +1,23 @@
module memory_tb;
parameter RATE = 1;
initial begin
$dumpfile("tb_memory.vcd");
$dumpvars(3, memory_tb);
# (10000) $finish;
end
reg clk = 0;
always #(RATE) clk = !clk;
wire LED;
wire TX;
TOP top(
.clock(clk),
.LED(LED),
.tx(TX)
);
endmodule