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https://github.com/mii443/tangprimer-riscv.git
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24 lines
1.1 KiB
XML
24 lines
1.1 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="C:\Users\kuroc\Downloads\cpu\src\memory.v" type="verilog"/>
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<File path="C:\Users\kuroc\Downloads\cpu\src\top.v" type="verilog"/>
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<File path="C:\Users\kuroc\Downloads\cpu\src\uart.v" type="verilog"/>
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<File path="C:\Users\kuroc\Downloads\cpu\src\core.v" type="verilog"/>
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<File path="C:\Users\kuroc\Downloads\cpu\src\defs.vh" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="dsp_balance" value="0"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="1"/>
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<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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