addi

cpu.gprj.user

@@ -20,5 +20,5 @@
         <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/cpu_syn.rpt.html"/>
         <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/cpu_syn_rsc.xml"/>
     </ResultFileList>
-    <Ui>000000ff00000001fd0000000200000000000000e1000002e0fc0200000002fc00000037000001290000006200fffffffa000000000200000001fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006200fffffffc00000164000001b30000009301000016fa000000010200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005e00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007c00ffffff0000000300000780000000c2fc0100000003fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000000007800000009b00fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0000000000ffffffff0000005100fffffffc000005050000063b0000000000fffffffa000000000100000001fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff00000000000000000000069b000002e000000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000ffffffff0100000226ffffffff0000000000000000</Ui>
+    <Ui>000000ff00000001fd0000000200000000000000e1000002e0fc0200000002fc00000037000001290000000000fffffffaffffffff0200000001fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fc00000164000001b30000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff00000000000000000000000300000780000000c2fc0100000003fb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000000007800000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0000000000ffffffff0000000000000000fc000005050000063b0000000000fffffffa000000000100000001fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff00000000000000000000069b000002e000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000adffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c0073010000017fffffffff0000000000000000</Ui>
 </UserConfig>

impl/gwsynthesis/cpu.log

@@ -15,7 +15,7 @@ Extracting RAM for identifier 'mem'("C:\Users\kuroc\Downloads\cpu\src\memory.v":
 WARN  (EX3784) : Index 33 is out of range [32:0] for 'mem'("C:\Users\kuroc\Downloads\cpu\src\memory.v":19)
 Compiling module 'CORE'("C:\Users\kuroc\Downloads\cpu\src\core.v":3)
 Extracting RAM for identifier 'register'("C:\Users\kuroc\Downloads\cpu\src\core.v":19)
-WARN  (EX3791) : Expression size 32 truncated to fit in target size 21("C:\Users\kuroc\Downloads\cpu\src\core.v":101)
+WARN  (EX3791) : Expression size 32 truncated to fit in target size 21("C:\Users\kuroc\Downloads\cpu\src\core.v":107)
 NOTE  (EX0101) : Current top module is "TOP"
 [5%] Running netlist conversion ...
 Running device independent optimization ...

impl/gwsynthesis/cpu_syn_resource.html

@@ -39,29 +39,29 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
 </tr>
 <td class="label">&nbsp&nbsp&nbsp&nbsp|--uart0
  (C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
-<td align = "center">58</td>
+<td align = "center">54</td>
 <td align = "center">31</td>
-<td align = "center">39</td>
+<td align = "center">41</td>
 <td align = "center">-</td>
 <td align = "center">-</td>
 <td align = "center">-</td>
 </tr>
 <td class="label">&nbsp&nbsp&nbsp&nbsp|--mem0
  (C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
-<td align = "center">512</td>
+<td align = "center">-</td>
-<td align = "center">78</td>
+<td align = "center">-</td>
-<td align = "center">4036</td>
+<td align = "center">37</td>
 <td align = "center">-</td>
 <td align = "center">-</td>
 <td align = "center">-</td>
 </tr>
 <td class="label">&nbsp&nbsp&nbsp&nbsp|--core0
  (C:/Users/kuroc/Downloads/cpu/src/top.v)</td>
-<td align = "center">185</td>
+<td align = "center">150</td>
-<td align = "center">62</td>
+<td align = "center">37</td>
-<td align = "center">125</td>
+<td align = "center">92</td>
 <td align = "center">-</td>
-<td align = "center">2</td>
+<td align = "center">1</td>
 <td align = "center">-</td>
 </tr>
 </table>

impl/gwsynthesis/cpu_syn_rsc.xml

@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <Module name="TOP">
-    <SubModule name="uart0" Register="58" Alu="31" Lut="39"/>
+    <SubModule name="uart0" Register="54" Alu="31" Lut="41"/>
-    <SubModule name="mem0" Register="512" Alu="78" Lut="4036"/>
+    <SubModule name="mem0" Lut="37"/>
-    <SubModule name="core0" Register="185" Alu="62" Lut="125" Bsram="2"/>
+    <SubModule name="core0" Register="150" Alu="37" Lut="92" Bsram="1"/>
 </Module>

impl/pnr/cpu.log

@@ -25,5 +25,5 @@ Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.pin.html" completed
 Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.rpt.html" completed
 Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.rpt.txt" completed
 Generate file "C:\Users\kuroc\Downloads\cpu\impl\pnr\cpu.tr.html" completed
-Thu May 18 14:32:04 2023
+Mon May 22 14:29:38 2023
 

impl/pnr/cpu.pin.html

@@ -74,7 +74,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Created Time</td>
-<td>Thu May 18 14:32:04 2023
+<td>Mon May 22 14:29:38 2023
 </td>
 </tr>
 <tr>

impl/pnr/cpu.power.html

@@ -83,7 +83,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Created Time</td>
-<td>Thu May 18 14:32:04 2023
+<td>Mon May 22 14:29:38 2023
 </td>
 </tr>
 <tr>
@@ -96,7 +96,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 <table class="summary_table">
 <tr>
 <td class="label">Total Power (mW)</td>
-<td>200.003</td>
+<td>179.270</td>
 </tr>
 <tr>
 <td class="label">Quiescent Power (mW)</td>
@@ -104,14 +104,14 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Dynamic Power (mW)</td>
-<td>39.574</td>
+<td>18.841</td>
 </tr>
 </table>
 <h2><a name="Thermal_Info">Thermal Information:</a></h2>
 <table class="summary_table">
 <tr>
 <td class="label">Junction Temperature</td>
-<td>31.404</td>
+<td>30.740</td>
 </tr>
 <tr>
 <td class="label">Theta JA</td>
@@ -119,7 +119,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Max Allowed Ambient Temperature</td>
-<td>78.596</td>
+<td>79.260</td>
 </tr>
 </table>
 <h2><a name="Configure_Info">Configure Information:</a></h2>
@@ -188,9 +188,9 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 <tr>
 <td>VCC</td>
 <td>1.000</td>
-<td>37.908</td>
+<td>17.174</td>
 <td>101.834</td>
-<td>139.742</td>
+<td>119.008</td>
 </tr>
 <tr>
 <td>VCCX</td>
@@ -225,7 +225,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td>Logic</td>
-<td>5.586</td>
+<td>0.803</td>
 <td>NA</td>
 <td>12.500</td>
 </tr>
@@ -237,7 +237,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td>BSRAM</td>
-<td>31.860
+<td>15.930
 <td>NA</td>
 <td>NA</td>
 </tr>
@@ -251,16 +251,16 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td>TOP</td>
-<td>37.446</td>
+<td>16.733</td>
-<td>37.446(37.446)</td>
+<td>16.733(16.733)</td>
 <tr>
 <td>TOP/core0/</td>
-<td>32.569</td>
+<td>16.387</td>
-<td>32.569(0.000)</td>
+<td>16.387(0.000)</td>
 <tr>
 <td>TOP/mem0/</td>
-<td>4.567</td>
+<td>0.037</td>
-<td>4.567(0.000)</td>
+<td>0.037(0.000)</td>
 <tr>
 <td>TOP/uart0/</td>
 <td>0.309</td>
@@ -276,7 +276,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 <tr>
 <td>clock</td>
 <td>100.000</td>
-<td>37.473</td>
+<td>16.740</td>
 </tr>
 </table>
 </div><!-- content -->

impl/pnr/cpu.rpt.html

@@ -79,7 +79,7 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 </tr>
 <tr>
 <td class="label">Created Time</td>
-<td>Thu May 18 14:32:04 2023
+<td>Mon May 22 14:29:38 2023
 </td>
 </tr>
 <tr>
@@ -93,23 +93,23 @@ table.detail_table th.label {  min-width: 8%; width: 8%; }
 <tr>
 <td class="label">Place & Route Process</td>
 <td>Running placement:
-   Placement Phase 0: CPU time = 0h 0m 0.329s, Elapsed time = 0h 0m 0.33s
+   Placement Phase 0: CPU time = 0h 0m 0.025s, Elapsed time = 0h 0m 0.026s
-   Placement Phase 1: CPU time = 0h 0m 0.575s, Elapsed time = 0h 0m 0.575s
+   Placement Phase 1: CPU time = 0h 0m 0.362s, Elapsed time = 0h 0m 0.361s
-   Placement Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
+   Placement Phase 2: CPU time = 0h 0m 0.033s, Elapsed time = 0h 0m 0.033s
-   Placement Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s
+   Placement Phase 3: CPU time = 0h 0m 0.9s, Elapsed time = 0h 0m 0.901s
-   Total Placement: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s
+   Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
 Running routing:
-   Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
+   Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
-   Routing Phase 1: CPU time = 0h 0m 0.229s, Elapsed time = 0h 0m 0.229s
+   Routing Phase 1: CPU time = 0h 0m 0.159s, Elapsed time = 0h 0m 0.159s
-   Routing Phase 2: CPU time = 0h 0m 32s, Elapsed time = 0h 0m 32s
+   Routing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.202s
-   Total Routing: CPU time = 0h 0m 33s, Elapsed time = 0h 0m 33s
+   Total Routing: CPU time = 0h 0m 0.362s, Elapsed time = 0h 0m 0.361s
 Generate output files:
    CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
 </td>
 </tr>
 <tr>
 <td class="label">Total Time and Memory Usage</td>
-<td>CPU time = 0h 0m 47s, Elapsed time = 0h 0m 47s, Peak memory usage = 370MB</td>
+<td>CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 394MB</td>
 </tr>
 </table>
 <br/>
@@ -124,12 +124,12 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">Logic</td>
-<td>4382/20736</td>
+<td>242/20736</td>
-<td>21%</td>
+<td>1%</td>
 </tr>
 <tr>
 <td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
-<td>4382(4200 LUT, 182 ALU, 0 ROM16)</td>
+<td>242(170 LUT, 72 ALU, 0 ROM16)</td>
 <td>-</td>
 </tr>
 <tr>
@@ -139,8 +139,8 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">Register</td>
-<td>755/16173</td>
+<td>204/16173</td>
-<td>4%</td>
+<td>1%</td>
 </tr>
 <tr>
 <td class="label">&nbsp &nbsp --Logic Register as Latch</td>
@@ -149,8 +149,8 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">&nbsp &nbsp --Logic Register as FF</td>
-<td>755/15552</td>
+<td>204/15552</td>
-<td>4%</td>
+<td>1%</td>
 </tr>
 <tr>
 <td class="label">&nbsp &nbsp --I/O Register as Latch</td>
@@ -164,8 +164,8 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">CLS</td>
-<td>2410/10368</td>
+<td>187/10368</td>
-<td>23%</td>
+<td>1%</td>
 </tr>
 <tr>
 <td class="label">I/O Port</td>
@@ -199,8 +199,8 @@ Generate output files:
 </tr>
 <tr>
 <td class="label">BSRAM</td>
-<td>2 SDPB<br/></td>
+<td>1 SDPB<br/></td>
-<td>4%</td>
+<td>2%</td>
 </tr>
 <tr>
 <td class="label">DSP</td>
@@ -329,7 +329,7 @@ Generate output files:
 <tr>
 <td class="label">clock_d</td>
 <td>PRIMARY</td>
-<td> TR TL BR BL</td>
+<td> TR</td>
 </tr>
 </table>
 <br/>

impl/pnr/cpu.rpt.txt

@@ -11,26 +11,26 @@
   <PnR Version>: V1.9.8.09 Education
   <Part Number>: GW2A-LV18PG256C8/I7
   <Device>: GW2A-18C
-  <Created Time>:Thu May 18 14:32:04 2023
+  <Created Time>:Mon May 22 14:29:38 2023
 
 
 2. PnR Details
 
   Running placement:
-    Placement Phase 0: CPU time = 0h 0m 0.329s, Elapsed time = 0h 0m 0.33s
+    Placement Phase 0: CPU time = 0h 0m 0.025s, Elapsed time = 0h 0m 0.026s
-    Placement Phase 1: CPU time = 0h 0m 0.575s, Elapsed time = 0h 0m 0.575s
+    Placement Phase 1: CPU time = 0h 0m 0.362s, Elapsed time = 0h 0m 0.361s
-    Placement Phase 2: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
+    Placement Phase 2: CPU time = 0h 0m 0.033s, Elapsed time = 0h 0m 0.033s
-    Placement Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s
+    Placement Phase 3: CPU time = 0h 0m 0.9s, Elapsed time = 0h 0m 0.901s
-    Total Placement: CPU time = 0h 0m 11s, Elapsed time = 0h 0m 11s
+    Total Placement: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
  Running routing:
-    Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s
+    Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
-    Routing Phase 1: CPU time = 0h 0m 0.229s, Elapsed time = 0h 0m 0.229s
+    Routing Phase 1: CPU time = 0h 0m 0.159s, Elapsed time = 0h 0m 0.159s
-    Routing Phase 2: CPU time = 0h 0m 32s, Elapsed time = 0h 0m 32s
+    Routing Phase 2: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.202s
-    Total Routing: CPU time = 0h 0m 33s, Elapsed time = 0h 0m 33s
+    Total Routing: CPU time = 0h 0m 0.362s, Elapsed time = 0h 0m 0.361s
  Generate output files:
     CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
 
- Total Time and Memory Usage: CPU time = 0h 0m 47s, Elapsed time = 0h 0m 47s, Peak memory usage = 370MB
+ Total Time and Memory Usage: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s, Peak memory usage = 394MB
 
 
 3. Resource Usage Summary
@@ -38,23 +38,23 @@
   ----------------------------------------------------------
   Resources                   | Usage
   ----------------------------------------------------------
-  Logic                       | 4382/20736  21%
+  Logic                       | 242/20736  1%
-    --LUT,ALU,ROM16           | 4382(4200 LUT, 182 ALU, 0 ROM16)
+    --LUT,ALU,ROM16           | 242(170 LUT, 72 ALU, 0 ROM16)
     --SSRAM(RAM16)            | 0
-  Register                    | 755/16173  4%
+  Register                    | 204/16173  1%
     --Logic Register as Latch | 0/15552  0%
-    --Logic Register as FF    | 755/15552  4%
+    --Logic Register as FF    | 204/15552  1%
     --I/O Register as Latch   | 0/621  0%
     --I/O Register as FF      | 0/621  0%
-  CLS                         | 2410/10368  23%
+  CLS                         | 187/10368  1%
   I/O Port                    | 3
   I/O Buf                     | 3
     --Input Buf               | 1
     --Output Buf              | 2
     --Inout Buf               | 0
   IOLOGIC                     | 0%
-  BSRAM                       | 4%
+  BSRAM                       | 2%
-    --SDPB                    | 2
+    --SDPB                    | 1
   DSP                         | 0%
   PLL                         | 0/4  0%
   DCS                         | 0/8  0%
@@ -103,7 +103,7 @@
   -------------------------------------------
   Signal         | Global Clock   | Location
   -------------------------------------------
-  clock_d        | PRIMARY        |  TR TL BR BL
+  clock_d        | PRIMARY        |  TR
   ===========================================
 
 

impl/pnr/cpu_tr_cata.html

@@ -31,7 +31,7 @@ function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.
 <ul>
 <li><div class="triangle_fake"></div><a href="cpu_tr_content.html#STA_Tool_Run_Summary" style=" font-size: 14px;" target="mainFrame">STA Tool Run Summary</a></li>
 <li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Clock_Report" style=" font-size: 14px;" target="mainFrame">Clock Summary</a></li>
-<li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;color: #FF0000;" target="mainFrame">Max Frequency Summary</a></li>
+<li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;" target="mainFrame">Max Frequency Summary</a></li>
 <li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Total_Negative_Slack_Report" style=" font-size: 14px;" target="mainFrame">Total Negative Slack Summary</a></li>
 </ul>
 </li>
@@ -43,7 +43,7 @@ function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.
 <li><div class="triangle" onclick="onClick(this)"></div><a href="cpu_tr_content.html#All_Path_Slack_Table" style=" font-size: 14px;" target="mainFrame">Path Slacks Table</a>
 <ul>
 <!--Setup_Slack_Table begin-->
-<li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;color: #FF0000;" target="mainFrame">Setup Paths Table</a>
+<li><div class="triangle_fake"></div><a href="cpu_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;" target="mainFrame">Setup Paths Table</a>
 </li>
 <!--Setup_Slack_Table end-->
 <!--Hold_Slack_Table begin-->

src/core.v

@@ -30,6 +30,9 @@ module CORE(
     reg [31:0] reg_wdata;
     reg reg_wen;
 
+    reg [31:0] reg_wb_data;
+    reg reg_wb_wen;
+
     reg [6:0] opcode;
     reg [4:0] rd;
     reg [2:0] funct3;
@@ -62,7 +65,10 @@ module CORE(
         for (i=0;i<32;i=i+1) register[i] <= 31'b0;
         register[0] <= 32'b00000000000000000000000000000000;
         register[1] <= 32'b00000000000000000000000000000000;
-        register[2] <= 32'b00000000000000000000000001000001;
+        register[2] <= 32'b00000000000000000000000000000000;
+    
+        reg_wb_data = 0;
+        reg_wb_wen = 0;
 
         pc = 0;
         reg_inst = 0;
@@ -79,7 +85,7 @@ module CORE(
             ST_IF: begin
                 reg_tx_start <= 1;
                 reg_tx_data <= rdata[31:24];
-                REGISTER_TEST <= register[1][31:0];
+                REGISTER_TEST <= register[4][31:0];
                 reg_inst <= inst;
                 pc_p4 <= pc + 4;
 
@@ -104,13 +110,18 @@ module CORE(
             end
 
             ST_EX: begin
-
+                if ((reg_inst & `MASK_OP_SW) == `OP_SW)
-                case (opcode)
+                    alu_out = rs1_data + s_imm_sext;
-                    `OP_SW:
+                if ((reg_inst & `MASK_OP_LW) == `OP_LW)
-                        alu_out = rs1_data + s_imm_sext;
+                    alu_out = rs1_data + i_imm_sext;
-                    `OP_LW:
+                if ((reg_inst & `MASK_OP_LUI) == `OP_LUI) begin
-                        alu_out = rs1_data + i_imm_sext;
+                    reg_wb_data[31:12] = u_imm[31:12];
-                endcase
+                    reg_wb_wen = 1;
+                end
+                if ((reg_inst & `MASK_OP_ADDI) == `OP_ADDI) begin
+                    reg_wb_data = rs1_data + i_imm_sext;
+                    reg_wb_wen = 1;
+                end
 
                 stage <= ST_ACCESS;
             end
@@ -127,7 +138,10 @@ module CORE(
 
                 if (opcode == `OP_LW)
                     register[rd] <= rdata;
+                if (reg_wb_wen == 1)
+                    register[rd] <= reg_wb_data;
 
+                reg_wb_wen = 0;
                 pc = pc_p4;
                 alu_out = 0;
                 reg_wen = 0;

src/defs.vh

@@ -1,2 +1,11 @@
-`define OP_SW 7'b0100011
+`define OP_SW      32'b00000000000000000010000000100011
-`define OP_LW 7'b0000011
+`define MASK_OP_SW 32'b00000000000000000111000001111111
+
+`define OP_LW      32'b00000000000000000010000000000011
+`define MASK_OP_LW 32'b00000000000000000111000001111111
+
+`define OP_LUI      32'b00000000000000000000000000110111
+`define MASK_OP_LUI 32'b00000000000000000000000001111111
+
+`define OP_ADDI      32'b00000000000000000000000000010011
+`define MASK_OP_ADDI 32'b00000000000000000111000001111111

src/memory.v

@@ -17,15 +17,17 @@ module MEMORY(
     integer i;
     initial begin
         for (i=0;i<64;i=i+1) mem[i] <= 0;
-        mem[0] <= 8'b00000000;
-        mem[1] <= 8'b00100000;
-        mem[2] <= 8'b10100010;
-        mem[3] <= 8'b00100011;
 
-        mem[0] <= 8'b00000000;
+        mem[0] <= 8'b1101_1101;
-        mem[1] <= 8'b00100000;
+        mem[1] <= 8'b0000_0000;
-        mem[2] <= 8'b10100010;
+        mem[2] <= 8'b0000_0010;
-        mem[3] <= 8'b00100011;
+        mem[3] <= 8'b0011_0111;
+
+        mem[4] <= 8'b0000_0011;
+        mem[5] <= 8'b0011_0010;
+        mem[6] <= 8'b0000_0010;
+        mem[7] <= 8'b0001_0011;
+
         reg_raddr <= 32'b0;
     end