Files
tangprimer-riscv/impl/gwsynthesis/cpu_syn_rsc.xml
2023-05-25 14:39:16 +09:00

7 lines
242 B
XML

<?xml version="1.0" encoding="UTF-8"?>
<Module name="TOP">
<SubModule name="uart0" Register="54" Alu="31" Lut="41"/>
<SubModule name="mem0" Lut="37"/>
<SubModule name="core0" Register="150" Alu="37" Lut="92" Bsram="1"/>
</Module>