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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\kuroc\Downloads\cpu\src\memory.v<br>
C:\Users\kuroc\Downloads\cpu\src\top.v<br>
C:\Users\kuroc\Downloads\cpu\src\uart.v<br>
C:\Users\kuroc\Downloads\cpu\src\core.v<br>
C:\Users\kuroc\Downloads\cpu\src\defs.vh<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>GowinSynthesis V1.9.8.09 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Mon May 22 14:29:32 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>TOP</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.317s, Peak memory usage = 394.379MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 394.379MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 394.379MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 394.379MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 394.379MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 394.379MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 394.379MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 394.379MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 394.379MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 394.379MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 394.379MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.578s, Elapsed time = 0h 0m 0.64s, Peak memory usage = 394.379MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 394.379MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 394.379MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 0.87s, Elapsed time = 0h 0m 1s, Peak memory usage = 394.379MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>204</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>57</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>114</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>32</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>168</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>9</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>100</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>59</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>68</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>68</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>238(170 LUTs, 68 ALUs) / 20736</td>
<td>1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>204 / 16173</td>
<td>1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>204 / 16173</td>
<td>1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>1 / 46</td>
<td>2%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clock</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>clock_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clock</td>
<td>100.0(MHz)</td>
<td>152.2(MHz)</td>
<td>12</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.430</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.398</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>core0/reg_wb_data_31_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/I2</td>
</tr>
<tr>
<td>2.577</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/F</td>
</tr>
<tr>
<td>2.814</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/I3</td>
</tr>
<tr>
<td>3.185</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/F</td>
</tr>
<tr>
<td>3.422</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/I2</td>
</tr>
<tr>
<td>3.875</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/F</td>
</tr>
<tr>
<td>4.112</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n174_s/I0</td>
</tr>
<tr>
<td>4.661</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>core0/n174_s/COUT</td>
</tr>
<tr>
<td>4.661</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>core0/n173_s/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>core0/n173_s/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n172_s/CIN</td>
</tr>
<tr>
<td>4.731</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n172_s/COUT</td>
</tr>
<tr>
<td>4.731</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n171_s/CIN</td>
</tr>
<tr>
<td>4.766</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n171_s/COUT</td>
</tr>
<tr>
<td>4.766</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n170_s/CIN</td>
</tr>
<tr>
<td>4.801</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n170_s/COUT</td>
</tr>
<tr>
<td>4.801</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n169_s/CIN</td>
</tr>
<tr>
<td>4.837</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n169_s/COUT</td>
</tr>
<tr>
<td>4.837</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n168_s/CIN</td>
</tr>
<tr>
<td>4.872</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n168_s/COUT</td>
</tr>
<tr>
<td>4.872</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n167_s/CIN</td>
</tr>
<tr>
<td>4.907</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n167_s/COUT</td>
</tr>
<tr>
<td>4.907</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n166_s/CIN</td>
</tr>
<tr>
<td>4.942</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n166_s/COUT</td>
</tr>
<tr>
<td>4.942</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n165_s/CIN</td>
</tr>
<tr>
<td>4.977</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n165_s/COUT</td>
</tr>
<tr>
<td>4.977</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n164_s/CIN</td>
</tr>
<tr>
<td>5.013</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n164_s/COUT</td>
</tr>
<tr>
<td>5.013</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n163_s/CIN</td>
</tr>
<tr>
<td>5.048</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n163_s/COUT</td>
</tr>
<tr>
<td>5.048</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n162_s/CIN</td>
</tr>
<tr>
<td>5.083</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n162_s/COUT</td>
</tr>
<tr>
<td>5.083</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n161_s/CIN</td>
</tr>
<tr>
<td>5.118</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n161_s/COUT</td>
</tr>
<tr>
<td>5.118</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n160_s/CIN</td>
</tr>
<tr>
<td>5.153</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n160_s/COUT</td>
</tr>
<tr>
<td>5.153</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n159_s/CIN</td>
</tr>
<tr>
<td>5.189</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n159_s/COUT</td>
</tr>
<tr>
<td>5.189</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n158_s/CIN</td>
</tr>
<tr>
<td>5.224</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n158_s/COUT</td>
</tr>
<tr>
<td>5.224</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n157_s/CIN</td>
</tr>
<tr>
<td>5.259</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n157_s/COUT</td>
</tr>
<tr>
<td>5.259</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n156_s/CIN</td>
</tr>
<tr>
<td>5.294</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n156_s/COUT</td>
</tr>
<tr>
<td>5.294</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n155_s/CIN</td>
</tr>
<tr>
<td>5.329</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n155_s/COUT</td>
</tr>
<tr>
<td>5.329</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n154_s/CIN</td>
</tr>
<tr>
<td>5.365</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n154_s/COUT</td>
</tr>
<tr>
<td>5.365</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n153_s/CIN</td>
</tr>
<tr>
<td>5.400</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n153_s/COUT</td>
</tr>
<tr>
<td>5.400</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n152_s/CIN</td>
</tr>
<tr>
<td>5.435</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n152_s/COUT</td>
</tr>
<tr>
<td>5.435</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n151_s/CIN</td>
</tr>
<tr>
<td>5.470</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n151_s/COUT</td>
</tr>
<tr>
<td>5.470</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n150_s/CIN</td>
</tr>
<tr>
<td>5.505</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n150_s/COUT</td>
</tr>
<tr>
<td>5.505</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n149_s/CIN</td>
</tr>
<tr>
<td>5.541</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n149_s/COUT</td>
</tr>
<tr>
<td>5.541</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n148_s/CIN</td>
</tr>
<tr>
<td>5.576</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n148_s/COUT</td>
</tr>
<tr>
<td>5.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n147_s/CIN</td>
</tr>
<tr>
<td>5.611</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n147_s/COUT</td>
</tr>
<tr>
<td>5.611</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n146_s/CIN</td>
</tr>
<tr>
<td>5.646</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n146_s/COUT</td>
</tr>
<tr>
<td>5.646</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n145_s/CIN</td>
</tr>
<tr>
<td>5.681</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n145_s/COUT</td>
</tr>
<tr>
<td>5.681</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n144_s/CIN</td>
</tr>
<tr>
<td>5.717</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n144_s/COUT</td>
</tr>
<tr>
<td>5.954</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/n213_s5/I2</td>
</tr>
<tr>
<td>6.407</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n213_s5/F</td>
</tr>
<tr>
<td>6.644</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/n213_s4/I0</td>
</tr>
<tr>
<td>7.161</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n213_s4/F</td>
</tr>
<tr>
<td>7.398</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/reg_wb_data_31_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_wb_data_31_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core0/reg_wb_data_31_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>12</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.407, 67.437%; route: 1.896, 29.013%; tC2Q: 0.232, 3.550%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.685</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.142</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>core0/reg_wb_data_30_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/I2</td>
</tr>
<tr>
<td>2.577</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/F</td>
</tr>
<tr>
<td>2.814</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/I3</td>
</tr>
<tr>
<td>3.185</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/F</td>
</tr>
<tr>
<td>3.422</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/I2</td>
</tr>
<tr>
<td>3.875</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/F</td>
</tr>
<tr>
<td>4.112</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n174_s/I0</td>
</tr>
<tr>
<td>4.661</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>core0/n174_s/COUT</td>
</tr>
<tr>
<td>4.661</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>core0/n173_s/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>core0/n173_s/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n172_s/CIN</td>
</tr>
<tr>
<td>4.731</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n172_s/COUT</td>
</tr>
<tr>
<td>4.731</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n171_s/CIN</td>
</tr>
<tr>
<td>4.766</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n171_s/COUT</td>
</tr>
<tr>
<td>4.766</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n170_s/CIN</td>
</tr>
<tr>
<td>4.801</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n170_s/COUT</td>
</tr>
<tr>
<td>4.801</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n169_s/CIN</td>
</tr>
<tr>
<td>4.837</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n169_s/COUT</td>
</tr>
<tr>
<td>4.837</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n168_s/CIN</td>
</tr>
<tr>
<td>4.872</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n168_s/COUT</td>
</tr>
<tr>
<td>4.872</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n167_s/CIN</td>
</tr>
<tr>
<td>4.907</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n167_s/COUT</td>
</tr>
<tr>
<td>4.907</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n166_s/CIN</td>
</tr>
<tr>
<td>4.942</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n166_s/COUT</td>
</tr>
<tr>
<td>4.942</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n165_s/CIN</td>
</tr>
<tr>
<td>4.977</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n165_s/COUT</td>
</tr>
<tr>
<td>4.977</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n164_s/CIN</td>
</tr>
<tr>
<td>5.013</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n164_s/COUT</td>
</tr>
<tr>
<td>5.013</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n163_s/CIN</td>
</tr>
<tr>
<td>5.048</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n163_s/COUT</td>
</tr>
<tr>
<td>5.048</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n162_s/CIN</td>
</tr>
<tr>
<td>5.083</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n162_s/COUT</td>
</tr>
<tr>
<td>5.083</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n161_s/CIN</td>
</tr>
<tr>
<td>5.118</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n161_s/COUT</td>
</tr>
<tr>
<td>5.118</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n160_s/CIN</td>
</tr>
<tr>
<td>5.153</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n160_s/COUT</td>
</tr>
<tr>
<td>5.153</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n159_s/CIN</td>
</tr>
<tr>
<td>5.189</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n159_s/COUT</td>
</tr>
<tr>
<td>5.189</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n158_s/CIN</td>
</tr>
<tr>
<td>5.224</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n158_s/COUT</td>
</tr>
<tr>
<td>5.224</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n157_s/CIN</td>
</tr>
<tr>
<td>5.259</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n157_s/COUT</td>
</tr>
<tr>
<td>5.259</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n156_s/CIN</td>
</tr>
<tr>
<td>5.294</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n156_s/COUT</td>
</tr>
<tr>
<td>5.294</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n155_s/CIN</td>
</tr>
<tr>
<td>5.329</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n155_s/COUT</td>
</tr>
<tr>
<td>5.329</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n154_s/CIN</td>
</tr>
<tr>
<td>5.365</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n154_s/COUT</td>
</tr>
<tr>
<td>5.365</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n153_s/CIN</td>
</tr>
<tr>
<td>5.400</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n153_s/COUT</td>
</tr>
<tr>
<td>5.400</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n152_s/CIN</td>
</tr>
<tr>
<td>5.435</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n152_s/COUT</td>
</tr>
<tr>
<td>5.435</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n151_s/CIN</td>
</tr>
<tr>
<td>5.470</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n151_s/COUT</td>
</tr>
<tr>
<td>5.470</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n150_s/CIN</td>
</tr>
<tr>
<td>5.505</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n150_s/COUT</td>
</tr>
<tr>
<td>5.505</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n149_s/CIN</td>
</tr>
<tr>
<td>5.541</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n149_s/COUT</td>
</tr>
<tr>
<td>5.541</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n148_s/CIN</td>
</tr>
<tr>
<td>5.576</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n148_s/COUT</td>
</tr>
<tr>
<td>5.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n147_s/CIN</td>
</tr>
<tr>
<td>5.611</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n147_s/COUT</td>
</tr>
<tr>
<td>5.611</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n146_s/CIN</td>
</tr>
<tr>
<td>5.646</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n146_s/COUT</td>
</tr>
<tr>
<td>5.646</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n145_s/CIN</td>
</tr>
<tr>
<td>5.681</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n145_s/COUT</td>
</tr>
<tr>
<td>5.681</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n144_s/CIN</td>
</tr>
<tr>
<td>6.151</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n144_s/SUM</td>
</tr>
<tr>
<td>6.388</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/n214_s0/I0</td>
</tr>
<tr>
<td>6.905</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n214_s0/F</td>
</tr>
<tr>
<td>7.142</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/reg_wb_data_30_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_wb_data_30_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core0/reg_wb_data_30_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>11</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.389, 69.888%; route: 1.659, 26.418%; tC2Q: 0.232, 3.694%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.720</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.107</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>core0/reg_wb_data_29_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/I2</td>
</tr>
<tr>
<td>2.577</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/F</td>
</tr>
<tr>
<td>2.814</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/I3</td>
</tr>
<tr>
<td>3.185</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/F</td>
</tr>
<tr>
<td>3.422</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/I2</td>
</tr>
<tr>
<td>3.875</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/F</td>
</tr>
<tr>
<td>4.112</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n174_s/I0</td>
</tr>
<tr>
<td>4.661</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>core0/n174_s/COUT</td>
</tr>
<tr>
<td>4.661</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>core0/n173_s/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>core0/n173_s/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n172_s/CIN</td>
</tr>
<tr>
<td>4.731</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n172_s/COUT</td>
</tr>
<tr>
<td>4.731</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n171_s/CIN</td>
</tr>
<tr>
<td>4.766</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n171_s/COUT</td>
</tr>
<tr>
<td>4.766</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n170_s/CIN</td>
</tr>
<tr>
<td>4.801</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n170_s/COUT</td>
</tr>
<tr>
<td>4.801</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n169_s/CIN</td>
</tr>
<tr>
<td>4.837</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n169_s/COUT</td>
</tr>
<tr>
<td>4.837</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n168_s/CIN</td>
</tr>
<tr>
<td>4.872</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n168_s/COUT</td>
</tr>
<tr>
<td>4.872</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n167_s/CIN</td>
</tr>
<tr>
<td>4.907</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n167_s/COUT</td>
</tr>
<tr>
<td>4.907</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n166_s/CIN</td>
</tr>
<tr>
<td>4.942</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n166_s/COUT</td>
</tr>
<tr>
<td>4.942</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n165_s/CIN</td>
</tr>
<tr>
<td>4.977</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n165_s/COUT</td>
</tr>
<tr>
<td>4.977</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n164_s/CIN</td>
</tr>
<tr>
<td>5.013</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n164_s/COUT</td>
</tr>
<tr>
<td>5.013</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n163_s/CIN</td>
</tr>
<tr>
<td>5.048</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n163_s/COUT</td>
</tr>
<tr>
<td>5.048</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n162_s/CIN</td>
</tr>
<tr>
<td>5.083</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n162_s/COUT</td>
</tr>
<tr>
<td>5.083</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n161_s/CIN</td>
</tr>
<tr>
<td>5.118</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n161_s/COUT</td>
</tr>
<tr>
<td>5.118</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n160_s/CIN</td>
</tr>
<tr>
<td>5.153</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n160_s/COUT</td>
</tr>
<tr>
<td>5.153</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n159_s/CIN</td>
</tr>
<tr>
<td>5.189</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n159_s/COUT</td>
</tr>
<tr>
<td>5.189</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n158_s/CIN</td>
</tr>
<tr>
<td>5.224</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n158_s/COUT</td>
</tr>
<tr>
<td>5.224</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n157_s/CIN</td>
</tr>
<tr>
<td>5.259</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n157_s/COUT</td>
</tr>
<tr>
<td>5.259</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n156_s/CIN</td>
</tr>
<tr>
<td>5.294</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n156_s/COUT</td>
</tr>
<tr>
<td>5.294</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n155_s/CIN</td>
</tr>
<tr>
<td>5.329</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n155_s/COUT</td>
</tr>
<tr>
<td>5.329</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n154_s/CIN</td>
</tr>
<tr>
<td>5.365</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n154_s/COUT</td>
</tr>
<tr>
<td>5.365</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n153_s/CIN</td>
</tr>
<tr>
<td>5.400</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n153_s/COUT</td>
</tr>
<tr>
<td>5.400</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n152_s/CIN</td>
</tr>
<tr>
<td>5.435</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n152_s/COUT</td>
</tr>
<tr>
<td>5.435</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n151_s/CIN</td>
</tr>
<tr>
<td>5.470</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n151_s/COUT</td>
</tr>
<tr>
<td>5.470</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n150_s/CIN</td>
</tr>
<tr>
<td>5.505</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n150_s/COUT</td>
</tr>
<tr>
<td>5.505</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n149_s/CIN</td>
</tr>
<tr>
<td>5.541</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n149_s/COUT</td>
</tr>
<tr>
<td>5.541</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n148_s/CIN</td>
</tr>
<tr>
<td>5.576</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n148_s/COUT</td>
</tr>
<tr>
<td>5.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n147_s/CIN</td>
</tr>
<tr>
<td>5.611</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n147_s/COUT</td>
</tr>
<tr>
<td>5.611</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n146_s/CIN</td>
</tr>
<tr>
<td>5.646</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n146_s/COUT</td>
</tr>
<tr>
<td>5.646</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n145_s/CIN</td>
</tr>
<tr>
<td>6.116</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n145_s/SUM</td>
</tr>
<tr>
<td>6.353</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/n215_s0/I0</td>
</tr>
<tr>
<td>6.870</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n215_s0/F</td>
</tr>
<tr>
<td>7.107</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/reg_wb_data_29_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_wb_data_29_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core0/reg_wb_data_29_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>11</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.354, 69.718%; route: 1.659, 26.567%; tC2Q: 0.232, 3.715%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.756</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.072</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>core0/reg_wb_data_28_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/I2</td>
</tr>
<tr>
<td>2.577</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/F</td>
</tr>
<tr>
<td>2.814</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/I3</td>
</tr>
<tr>
<td>3.185</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/F</td>
</tr>
<tr>
<td>3.422</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/I2</td>
</tr>
<tr>
<td>3.875</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/F</td>
</tr>
<tr>
<td>4.112</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n174_s/I0</td>
</tr>
<tr>
<td>4.661</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>core0/n174_s/COUT</td>
</tr>
<tr>
<td>4.661</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>core0/n173_s/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>core0/n173_s/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n172_s/CIN</td>
</tr>
<tr>
<td>4.731</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n172_s/COUT</td>
</tr>
<tr>
<td>4.731</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n171_s/CIN</td>
</tr>
<tr>
<td>4.766</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n171_s/COUT</td>
</tr>
<tr>
<td>4.766</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n170_s/CIN</td>
</tr>
<tr>
<td>4.801</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n170_s/COUT</td>
</tr>
<tr>
<td>4.801</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n169_s/CIN</td>
</tr>
<tr>
<td>4.837</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n169_s/COUT</td>
</tr>
<tr>
<td>4.837</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n168_s/CIN</td>
</tr>
<tr>
<td>4.872</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n168_s/COUT</td>
</tr>
<tr>
<td>4.872</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n167_s/CIN</td>
</tr>
<tr>
<td>4.907</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n167_s/COUT</td>
</tr>
<tr>
<td>4.907</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n166_s/CIN</td>
</tr>
<tr>
<td>4.942</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n166_s/COUT</td>
</tr>
<tr>
<td>4.942</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n165_s/CIN</td>
</tr>
<tr>
<td>4.977</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n165_s/COUT</td>
</tr>
<tr>
<td>4.977</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n164_s/CIN</td>
</tr>
<tr>
<td>5.013</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n164_s/COUT</td>
</tr>
<tr>
<td>5.013</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n163_s/CIN</td>
</tr>
<tr>
<td>5.048</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n163_s/COUT</td>
</tr>
<tr>
<td>5.048</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n162_s/CIN</td>
</tr>
<tr>
<td>5.083</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n162_s/COUT</td>
</tr>
<tr>
<td>5.083</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n161_s/CIN</td>
</tr>
<tr>
<td>5.118</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n161_s/COUT</td>
</tr>
<tr>
<td>5.118</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n160_s/CIN</td>
</tr>
<tr>
<td>5.153</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n160_s/COUT</td>
</tr>
<tr>
<td>5.153</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n159_s/CIN</td>
</tr>
<tr>
<td>5.189</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n159_s/COUT</td>
</tr>
<tr>
<td>5.189</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n158_s/CIN</td>
</tr>
<tr>
<td>5.224</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n158_s/COUT</td>
</tr>
<tr>
<td>5.224</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n157_s/CIN</td>
</tr>
<tr>
<td>5.259</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n157_s/COUT</td>
</tr>
<tr>
<td>5.259</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n156_s/CIN</td>
</tr>
<tr>
<td>5.294</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n156_s/COUT</td>
</tr>
<tr>
<td>5.294</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n155_s/CIN</td>
</tr>
<tr>
<td>5.329</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n155_s/COUT</td>
</tr>
<tr>
<td>5.329</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n154_s/CIN</td>
</tr>
<tr>
<td>5.365</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n154_s/COUT</td>
</tr>
<tr>
<td>5.365</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n153_s/CIN</td>
</tr>
<tr>
<td>5.400</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n153_s/COUT</td>
</tr>
<tr>
<td>5.400</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n152_s/CIN</td>
</tr>
<tr>
<td>5.435</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n152_s/COUT</td>
</tr>
<tr>
<td>5.435</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n151_s/CIN</td>
</tr>
<tr>
<td>5.470</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n151_s/COUT</td>
</tr>
<tr>
<td>5.470</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n150_s/CIN</td>
</tr>
<tr>
<td>5.505</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n150_s/COUT</td>
</tr>
<tr>
<td>5.505</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n149_s/CIN</td>
</tr>
<tr>
<td>5.541</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n149_s/COUT</td>
</tr>
<tr>
<td>5.541</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n148_s/CIN</td>
</tr>
<tr>
<td>5.576</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n148_s/COUT</td>
</tr>
<tr>
<td>5.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n147_s/CIN</td>
</tr>
<tr>
<td>5.611</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n147_s/COUT</td>
</tr>
<tr>
<td>5.611</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n146_s/CIN</td>
</tr>
<tr>
<td>6.081</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n146_s/SUM</td>
</tr>
<tr>
<td>6.318</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/n216_s0/I0</td>
</tr>
<tr>
<td>6.835</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n216_s0/F</td>
</tr>
<tr>
<td>7.072</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/reg_wb_data_28_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_wb_data_28_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core0/reg_wb_data_28_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>11</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.318, 69.546%; route: 1.659, 26.718%; tC2Q: 0.232, 3.736%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.791</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>7.037</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>core0/reg_wb_data_27_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_ADAREG_G_3_s/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/I2</td>
</tr>
<tr>
<td>2.577</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/F</td>
</tr>
<tr>
<td>2.814</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/I3</td>
</tr>
<tr>
<td>3.185</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>32</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/F</td>
</tr>
<tr>
<td>3.422</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/I2</td>
</tr>
<tr>
<td>3.875</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/F</td>
</tr>
<tr>
<td>4.112</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n174_s/I0</td>
</tr>
<tr>
<td>4.661</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>1</td>
<td>core0/n174_s/COUT</td>
</tr>
<tr>
<td>4.661</td>
<td>0.000</td>
<td>tNET</td>
<td>RR</td>
<td>2</td>
<td>core0/n173_s/CIN</td>
</tr>
<tr>
<td>4.696</td>
<td>0.035</td>
<td>tINS</td>
<td>RF</td>
<td>1</td>
<td>core0/n173_s/COUT</td>
</tr>
<tr>
<td>4.696</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n172_s/CIN</td>
</tr>
<tr>
<td>4.731</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n172_s/COUT</td>
</tr>
<tr>
<td>4.731</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n171_s/CIN</td>
</tr>
<tr>
<td>4.766</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n171_s/COUT</td>
</tr>
<tr>
<td>4.766</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n170_s/CIN</td>
</tr>
<tr>
<td>4.801</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n170_s/COUT</td>
</tr>
<tr>
<td>4.801</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n169_s/CIN</td>
</tr>
<tr>
<td>4.837</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n169_s/COUT</td>
</tr>
<tr>
<td>4.837</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n168_s/CIN</td>
</tr>
<tr>
<td>4.872</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n168_s/COUT</td>
</tr>
<tr>
<td>4.872</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n167_s/CIN</td>
</tr>
<tr>
<td>4.907</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n167_s/COUT</td>
</tr>
<tr>
<td>4.907</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n166_s/CIN</td>
</tr>
<tr>
<td>4.942</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n166_s/COUT</td>
</tr>
<tr>
<td>4.942</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n165_s/CIN</td>
</tr>
<tr>
<td>4.977</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n165_s/COUT</td>
</tr>
<tr>
<td>4.977</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n164_s/CIN</td>
</tr>
<tr>
<td>5.013</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n164_s/COUT</td>
</tr>
<tr>
<td>5.013</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n163_s/CIN</td>
</tr>
<tr>
<td>5.048</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n163_s/COUT</td>
</tr>
<tr>
<td>5.048</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n162_s/CIN</td>
</tr>
<tr>
<td>5.083</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n162_s/COUT</td>
</tr>
<tr>
<td>5.083</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n161_s/CIN</td>
</tr>
<tr>
<td>5.118</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n161_s/COUT</td>
</tr>
<tr>
<td>5.118</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n160_s/CIN</td>
</tr>
<tr>
<td>5.153</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n160_s/COUT</td>
</tr>
<tr>
<td>5.153</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n159_s/CIN</td>
</tr>
<tr>
<td>5.189</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n159_s/COUT</td>
</tr>
<tr>
<td>5.189</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n158_s/CIN</td>
</tr>
<tr>
<td>5.224</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n158_s/COUT</td>
</tr>
<tr>
<td>5.224</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n157_s/CIN</td>
</tr>
<tr>
<td>5.259</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n157_s/COUT</td>
</tr>
<tr>
<td>5.259</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n156_s/CIN</td>
</tr>
<tr>
<td>5.294</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n156_s/COUT</td>
</tr>
<tr>
<td>5.294</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n155_s/CIN</td>
</tr>
<tr>
<td>5.329</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n155_s/COUT</td>
</tr>
<tr>
<td>5.329</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n154_s/CIN</td>
</tr>
<tr>
<td>5.365</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n154_s/COUT</td>
</tr>
<tr>
<td>5.365</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n153_s/CIN</td>
</tr>
<tr>
<td>5.400</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n153_s/COUT</td>
</tr>
<tr>
<td>5.400</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n152_s/CIN</td>
</tr>
<tr>
<td>5.435</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n152_s/COUT</td>
</tr>
<tr>
<td>5.435</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n151_s/CIN</td>
</tr>
<tr>
<td>5.470</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n151_s/COUT</td>
</tr>
<tr>
<td>5.470</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n150_s/CIN</td>
</tr>
<tr>
<td>5.505</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n150_s/COUT</td>
</tr>
<tr>
<td>5.505</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n149_s/CIN</td>
</tr>
<tr>
<td>5.541</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n149_s/COUT</td>
</tr>
<tr>
<td>5.541</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n148_s/CIN</td>
</tr>
<tr>
<td>5.576</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n148_s/COUT</td>
</tr>
<tr>
<td>5.576</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>core0/n147_s/CIN</td>
</tr>
<tr>
<td>6.046</td>
<td>0.470</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n147_s/SUM</td>
</tr>
<tr>
<td>6.283</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/n217_s0/I0</td>
</tr>
<tr>
<td>6.800</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>core0/n217_s0/F</td>
</tr>
<tr>
<td>7.037</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>core0/reg_wb_data_27_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>206</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>core0/reg_wb_data_27_s0/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>core0/reg_wb_data_27_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>11</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 4.283, 69.372%; route: 1.659, 26.870%; tC2Q: 0.232, 3.758%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
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