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21166 lines
339 KiB
HTML
21166 lines
339 KiB
HTML
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html>
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<head>
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<title>Timing Analysis Report</title>
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<style type="text/css">
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body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
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div#content { width: 100%; margin: }
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hr { margin-top: 30px; margin-bottom: 30px; }
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h1, h3 { text-align: center; }
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h1 {margin-top: 50px; }
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table, th, td {white-space:pre; border: 1px solid #aaa; }
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table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
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th, td { padding: 5px 5px 5px 5px; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
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table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
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table.detail_table th.label { min-width: 8%; width: 8%; }
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</style>
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</head>
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<body>
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<div id="content">
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<h1><a name="Message">Timing Messages</a></h1>
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<table class="summary_table">
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<tr>
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<td class="label">Report Title</td>
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<td>Timing Analysis Report</td>
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</tr>
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<tr>
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<td class="label">Design File</td>
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<td>C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg</td>
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</tr>
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<tr>
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<td class="label">Physical Constraints File</td>
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<td>C:\Users\kuroc\Downloads\cpu\src\cpu.cst</td>
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</tr>
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<tr>
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<td class="label">Timing Constraint File</td>
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<td>---</td>
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</tr>
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<tr>
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<td class="label">Version</td>
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<td>V1.9.8.09 Education</td>
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</tr>
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<tr>
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<td class="label">Part Number</td>
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<td>GW2A-LV18PG256C8/I7</td>
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</tr>
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<tr>
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<td class="label">Device</td>
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<td>GW2A-18C</td>
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Mon May 22 14:29:38 2023
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</td>
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</tr>
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<tr>
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<td class="label">Legal Announcement</td>
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<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
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</tr>
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</table>
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<h1><a name="Summary">Timing Summaries</a></h1>
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<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
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<table class="summary_table">
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<tr>
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<td class="label">Setup Delay Model</td>
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<td>Slow 0.95V 85C C8/I7</td>
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</tr>
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<tr>
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<td class="label">Hold Delay Model</td>
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<td>Fast 1.05V 0C C8/I7</td>
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</tr>
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<tr>
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<td class="label">Numbers of Paths Analyzed</td>
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<td>397</td>
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</tr>
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<tr>
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<td class="label">Numbers of Endpoints Analyzed</td>
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<td>418</td>
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</tr>
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<tr>
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<td class="label">Numbers of Falling Endpoints</td>
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<td>0</td>
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</tr>
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<tr>
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<td class="label">Numbers of Setup Violated Endpoints</td>
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<td>0</td>
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</tr>
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<tr>
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<td class="label">Numbers of Hold Violated Endpoints</td>
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<td>0</td>
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</tr>
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</table>
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<h2><a name="Clock_Report">Clock Summary:</a></h2>
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<table class="detail_table">
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<tr>
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<th class="label">Clock Name</th>
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<th class="label">Type</th>
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<th class="label">Period</th>
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<th class="label">Frequency(MHz)</th>
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<th class="label">Rise</th>
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<th class="label">Fall</th>
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<th class="label">Source</th>
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<th class="label">Master</th>
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<th class="label">Objects</th>
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</tr>
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<tr>
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<td>clock</td>
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<td>Base</td>
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<td>10.000</td>
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<td>100.000
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<td>0.000</td>
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<td>5.000</td>
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<td></td>
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<td></td>
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<td>clock_ibuf/I </td>
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</tr>
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</table>
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<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
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<table>
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<tr>
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<th>NO.</th>
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<th>Clock Name</th>
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<th>Constraint</th>
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<th>Actual Fmax</th>
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<th>Logic Level</th>
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<th>Entity</th>
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</tr>
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<tr>
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<td>1</td>
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<td>clock</td>
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<td>100.000(MHz)</td>
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<td>128.136(MHz)</td>
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<td>9</td>
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<td>TOP</td>
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</tr>
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</table>
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<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
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<table class="detail_table">
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<tr>
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<th class="label">Clock Name</th>
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<th class="label">Analysis Type</th>
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<th class="label">Endpoints TNS</th>
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<th class="label">Number of Endpoints</th>
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</tr>
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<tr>
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<td>clock</td>
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<td>Setup</td>
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<td>0.000</td>
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<td>0</td>
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</tr>
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<tr>
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<td>clock</td>
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<td>Hold</td>
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<td>0.000</td>
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<td>0</td>
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</tr>
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</table>
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<h1><a name="Detail">Timing Details</a></h1>
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<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
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<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
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<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
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<table class="detail_table">
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<tr>
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<th class="label">Path Number</th>
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<th class="label">Path Slack</th>
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<th class="label">From Node</th>
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<th class="label">To Node</th>
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<th class="label">From Clock</th>
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<th class="label">To Clock</th>
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<th class="label">Relation</th>
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<th class="label">Clock Skew</th>
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<th class="label">Data Delay</th>
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</tr>
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<tr>
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<td>1</td>
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<td>2.196</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_31_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.769</td>
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</tr>
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<tr>
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<td>2</td>
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<td>2.518</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_26_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.447</td>
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</tr>
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<tr>
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<td>3</td>
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<td>2.618</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_29_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.347</td>
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</tr>
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<tr>
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<td>4</td>
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<td>2.751</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_12_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.214</td>
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</tr>
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<tr>
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<td>5</td>
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<td>2.779</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_25_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.186</td>
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</tr>
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<tr>
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<td>6</td>
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<td>2.789</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_16_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.176</td>
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</tr>
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<tr>
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<td>7</td>
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<td>2.852</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_28_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.113</td>
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</tr>
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<tr>
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<td>8</td>
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<td>2.893</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_19_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.072</td>
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</tr>
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<tr>
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<td>9</td>
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<td>2.902</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_24_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.063</td>
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</tr>
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<tr>
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<td>10</td>
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<td>2.934</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_20_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.031</td>
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</tr>
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<tr>
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<td>11</td>
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<td>2.959</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_13_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>7.006</td>
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</tr>
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<tr>
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<td>12</td>
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<td>3.005</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_18_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.960</td>
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</tr>
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<tr>
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<td>13</td>
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<td>3.039</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_27_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.926</td>
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</tr>
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<tr>
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<td>14</td>
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<td>3.044</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_23_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.921</td>
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</tr>
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<tr>
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<td>15</td>
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<td>3.061</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_17_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.904</td>
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</tr>
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<tr>
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<td>16</td>
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<td>3.098</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_21_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.867</td>
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</tr>
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<tr>
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<td>17</td>
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<td>3.190</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_30_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.775</td>
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</tr>
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<tr>
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<td>18</td>
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<td>3.218</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_15_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.747</td>
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</tr>
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<tr>
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<td>19</td>
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<td>3.306</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_22_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.659</td>
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</tr>
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<tr>
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<td>20</td>
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<td>3.345</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_14_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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|
<td>10.000</td>
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<td>0.000</td>
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<td>6.620</td>
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</tr>
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<tr>
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<td>21</td>
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<td>3.370</td>
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<td>core0/rs1_3_s2/Q</td>
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<td>core0/alu_out_3_s1/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.595</td>
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</tr>
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<tr>
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<td>22</td>
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<td>3.374</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/alu_out_5_s1/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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|
<td>10.000</td>
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<td>0.000</td>
|
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<td>6.591</td>
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</tr>
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<tr>
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<td>23</td>
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<td>3.390</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/alu_out_2_s1/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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|
<td>10.000</td>
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<td>0.000</td>
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<td>6.575</td>
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</tr>
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<tr>
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<td>24</td>
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<td>3.491</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/reg_wb_data_2_s0/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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|
<td>10.000</td>
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<td>0.000</td>
|
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<td>6.474</td>
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</tr>
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<tr>
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<td>25</td>
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<td>3.496</td>
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<td>core0/register_register_0_0_s/DO[1]</td>
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<td>core0/alu_out_4_s1/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>6.469</td>
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</tr>
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</table>
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<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">Path Number</th>
|
|
<th class="label">Path Slack</th>
|
|
<th class="label">From Node</th>
|
|
<th class="label">To Node</th>
|
|
<th class="label">From Clock</th>
|
|
<th class="label">To Clock</th>
|
|
<th class="label">Relation</th>
|
|
<th class="label">Clock Skew</th>
|
|
<th class="label">Data Delay</th>
|
|
</tr>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>0.199</td>
|
|
<td>core0/reg_wb_data_30_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[30]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.448</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2</td>
|
|
<td>0.203</td>
|
|
<td>core0/reg_wb_data_7_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[7]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.452</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3</td>
|
|
<td>0.203</td>
|
|
<td>core0/reg_wb_data_6_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[6]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.452</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>0.213</td>
|
|
<td>core0/reg_wb_data_9_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[9]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.462</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>0.215</td>
|
|
<td>core0/reg_wb_data_31_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[31]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.464</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6</td>
|
|
<td>0.215</td>
|
|
<td>core0/reg_wb_data_21_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[21]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.464</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7</td>
|
|
<td>0.215</td>
|
|
<td>core0/reg_wb_data_20_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[20]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.464</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>0.215</td>
|
|
<td>core0/reg_wb_data_11_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[11]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.464</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>0.215</td>
|
|
<td>core0/reg_wb_data_10_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[10]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.464</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10</td>
|
|
<td>0.215</td>
|
|
<td>core0/reg_wb_data_8_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[8]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.464</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11</td>
|
|
<td>0.215</td>
|
|
<td>core0/reg_wb_data_5_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[5]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.464</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12</td>
|
|
<td>0.215</td>
|
|
<td>core0/reg_wb_data_4_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[4]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.464</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13</td>
|
|
<td>0.227</td>
|
|
<td>core0/reg_wb_data_29_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[29]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.476</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14</td>
|
|
<td>0.321</td>
|
|
<td>core0/reg_wb_data_25_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[25]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.570</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15</td>
|
|
<td>0.321</td>
|
|
<td>core0/reg_wb_data_24_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[24]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.570</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16</td>
|
|
<td>0.325</td>
|
|
<td>core0/reg_wb_data_27_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[27]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.574</td>
|
|
</tr>
|
|
<tr>
|
|
<td>17</td>
|
|
<td>0.337</td>
|
|
<td>core0/reg_wb_data_17_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[17]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.586</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18</td>
|
|
<td>0.337</td>
|
|
<td>core0/reg_wb_data_15_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[15]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.586</td>
|
|
</tr>
|
|
<tr>
|
|
<td>19</td>
|
|
<td>0.337</td>
|
|
<td>core0/reg_wb_data_14_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[14]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.586</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20</td>
|
|
<td>0.337</td>
|
|
<td>core0/reg_wb_data_0_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[0]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.586</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21</td>
|
|
<td>0.353</td>
|
|
<td>core0/reg_wb_data_23_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[23]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.602</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22</td>
|
|
<td>0.353</td>
|
|
<td>core0/reg_wb_data_1_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[1]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.602</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23</td>
|
|
<td>0.364</td>
|
|
<td>core0/reg_wb_data_19_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[19]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.613</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24</td>
|
|
<td>0.364</td>
|
|
<td>core0/reg_wb_data_13_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[13]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.613</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25</td>
|
|
<td>0.364</td>
|
|
<td>core0/reg_wb_data_3_s0/Q</td>
|
|
<td>core0/register_register_0_0_s/DI[3]</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.613</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>Nothing to report!</h4>
|
|
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>Nothing to report!</h4>
|
|
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">Number</th>
|
|
<th class="label">Slack</th>
|
|
<th class="label">Actual Width</th>
|
|
<th class="label">Required Width</th>
|
|
<th class="label">Type</th>
|
|
<th class="label">Clock</th>
|
|
<th class="label">Objects</th>
|
|
</tr>
|
|
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_30_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_28_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_16_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_0_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>core0/reg_inst_28_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>core0/reg_wb_data_11_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>core0/reg_wb_data_12_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>core0/reg_inst_29_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>core0/reg_wb_data_13_s0</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
|
|
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
|
<h3>Path1</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.196</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>8.695</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td>core0/n151_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n151_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td>core0/n150_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n150_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td>core0/n149_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n149_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td>core0/n148_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n148_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td>core0/n147_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.785</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n147_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.785</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[2][A]</td>
|
|
<td>core0/n146_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.820</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n146_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.820</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[2][B]</td>
|
|
<td>core0/n145_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.855</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n145_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.855</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C42[0][A]</td>
|
|
<td>core0/n144_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.891</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n144_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.774</td>
|
|
<td>0.883</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R11C42[1][A]</td>
|
|
<td>core0/n213_s5/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.323</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R11C42[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n213_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.324</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R11C42[0][A]</td>
|
|
<td>core0/n213_s4/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.695</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R11C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n213_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.695</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R11C42[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_31_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R11C42[0][A]</td>
|
|
<td>core0/reg_wb_data_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R11C42[0][A]</td>
|
|
<td>core0/reg_wb_data_31_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>9</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 3.066, 39.461%; route: 2.443, 31.450%; tC2Q: 2.260, 29.089%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path2</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.518</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>8.373</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_26_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td>core0/n151_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n151_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td>core0/n150_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n150_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td>core0/n149_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n149_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td>core0/n148_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.185</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n148_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.824</td>
|
|
<td>0.640</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>core0/n218_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.373</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n218_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.373</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_26_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>core0/reg_wb_data_26_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>core0/reg_wb_data_26_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.989, 40.132%; route: 2.199, 29.522%; tC2Q: 2.260, 30.346%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path3</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.618</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>8.273</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_29_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td>core0/n151_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n151_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td>core0/n150_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n150_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td>core0/n149_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n149_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td>core0/n148_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n148_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td>core0/n147_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.785</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n147_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.785</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[2][A]</td>
|
|
<td>core0/n146_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.820</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n146_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.820</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[2][B]</td>
|
|
<td>core0/n145_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.290</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n145_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.703</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][B]</td>
|
|
<td>core0/n215_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.273</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n215_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.273</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_29_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][B]</td>
|
|
<td>core0/reg_wb_data_29_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C42[0][B]</td>
|
|
<td>core0/reg_wb_data_29_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>8</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 3.115, 42.401%; route: 1.972, 26.840%; tC2Q: 2.260, 30.759%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path4</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.751</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>8.139</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_12_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.692</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.590</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C42[2][B]</td>
|
|
<td>core0/n232_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.139</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R15C42[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n232_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.139</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C42[2][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_12_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C42[2][B]</td>
|
|
<td>core0/reg_wb_data_12_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C42[2][B]</td>
|
|
<td>core0/reg_wb_data_12_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>6</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.496, 34.602%; route: 2.458, 34.068%; tC2Q: 2.260, 31.330%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path5</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.779</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>8.112</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_25_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td>core0/n151_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n151_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td>core0/n150_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n150_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td>core0/n149_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.149</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n149_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.563</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>core0/n219_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.112</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n219_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.112</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_25_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>core0/reg_wb_data_25_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>core0/reg_wb_data_25_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.954, 41.104%; route: 1.972, 27.444%; tC2Q: 2.260, 31.452%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path6</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.789</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>8.102</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_16_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.833</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.731</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C42[0][A]</td>
|
|
<td>core0/n228_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.102</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n228_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.102</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C42[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_16_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C42[0][A]</td>
|
|
<td>core0/reg_wb_data_16_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C42[0][A]</td>
|
|
<td>core0/reg_wb_data_16_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>6</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.459, 34.263%; route: 2.458, 34.245%; tC2Q: 2.260, 31.492%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path7</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.852</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>8.039</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_28_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td>core0/n151_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n151_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td>core0/n150_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n150_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td>core0/n149_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n149_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td>core0/n148_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n148_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td>core0/n147_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.785</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n147_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.785</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[2][A]</td>
|
|
<td>core0/n146_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.255</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n146_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.668</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td>core0/n216_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.039</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n216_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8.039</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_28_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td>core0/reg_wb_data_28_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td>core0/reg_wb_data_28_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>8</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.881, 40.505%; route: 1.972, 27.724%; tC2Q: 2.260, 31.772%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path8</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.893</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.998</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_19_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.938</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.428</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][A]</td>
|
|
<td>core0/n225_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n225_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.998</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_19_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][A]</td>
|
|
<td>core0/reg_wb_data_19_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C42[1][A]</td>
|
|
<td>core0/reg_wb_data_19_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.763, 39.074%; route: 2.049, 28.969%; tC2Q: 2.260, 31.956%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path9</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.902</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.989</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td>core0/n151_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n151_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td>core0/n150_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.114</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n150_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.527</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td>core0/n220_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.989</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n220_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.989</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_24_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td>core0/reg_wb_data_24_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td>core0/reg_wb_data_24_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.831, 40.085%; route: 1.972, 27.919%; tC2Q: 2.260, 31.996%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path10</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.934</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.957</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_20_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.973</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.387</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td>core0/n224_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.957</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n224_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.957</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_20_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td>core0/reg_wb_data_20_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td>core0/reg_wb_data_20_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.799, 39.806%; route: 1.972, 28.049%; tC2Q: 2.260, 32.145%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path11</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>2.959</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.932</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_13_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.727</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.383</td>
|
|
<td>0.656</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C40[0][A]</td>
|
|
<td>core0/n231_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.932</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R15C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n231_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.932</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C40[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_13_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C40[0][A]</td>
|
|
<td>core0/reg_wb_data_13_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C40[0][A]</td>
|
|
<td>core0/reg_wb_data_13_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>6</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.531, 36.129%; route: 2.215, 31.613%; tC2Q: 2.260, 32.258%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path12</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.005</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.886</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_18_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.903</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.316</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][B]</td>
|
|
<td>core0/n226_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.886</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n226_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.886</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_18_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][B]</td>
|
|
<td>core0/reg_wb_data_18_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[0][B]</td>
|
|
<td>core0/reg_wb_data_18_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.728, 39.197%; route: 1.972, 28.333%; tC2Q: 2.260, 32.470%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path13</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.039</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.852</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_27_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td>core0/n151_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n151_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td>core0/n150_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n150_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td>core0/n149_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n149_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td>core0/n148_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n148_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td>core0/n147_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.220</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n147_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.390</td>
|
|
<td>0.170</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][A]</td>
|
|
<td>core0/n217_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.852</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n217_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.852</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_27_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][A]</td>
|
|
<td>core0/reg_wb_data_27_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R12C42[1][A]</td>
|
|
<td>core0/reg_wb_data_27_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.937, 42.403%; route: 1.729, 24.968%; tC2Q: 2.260, 32.629%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path14</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.044</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.847</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_23_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td>core0/n151_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.079</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n151_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.476</td>
|
|
<td>0.397</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][A]</td>
|
|
<td>core0/n221_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.847</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n221_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.847</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_23_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][A]</td>
|
|
<td>core0/reg_wb_data_23_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C40[2][A]</td>
|
|
<td>core0/reg_wb_data_23_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.705, 39.086%; route: 1.956, 28.260%; tC2Q: 2.260, 32.654%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path15</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.061</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.830</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_17_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.868</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.281</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][B]</td>
|
|
<td>core0/n227_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.830</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n227_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.830</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_17_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][B]</td>
|
|
<td>core0/reg_wb_data_17_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C40[2][B]</td>
|
|
<td>core0/reg_wb_data_17_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>6</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.672, 38.702%; route: 1.972, 28.564%; tC2Q: 2.260, 32.734%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path16</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.098</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.793</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_21_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.009</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.422</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>core0/n223_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.793</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n223_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.793</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_21_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>core0/reg_wb_data_21_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>core0/reg_wb_data_21_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.635, 38.370%; route: 1.972, 28.719%; tC2Q: 2.260, 32.912%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path17</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.190</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.701</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_30_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.609</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td>core0/n151_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n151_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.644</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td>core0/n150_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n150_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.679</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td>core0/n149_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n149_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.715</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td>core0/n148_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n148_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.750</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td>core0/n147_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.785</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n147_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.785</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[2][A]</td>
|
|
<td>core0/n146_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.820</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n146_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.820</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C41[2][B]</td>
|
|
<td>core0/n145_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.855</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C41[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n145_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.855</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C42[0][A]</td>
|
|
<td>core0/n144_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.325</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n144_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.330</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][B]</td>
|
|
<td>core0/n214_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.701</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n214_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.701</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_30_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][B]</td>
|
|
<td>core0/reg_wb_data_30_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R12C42[1][B]</td>
|
|
<td>core0/reg_wb_data_30_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>8</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.952, 43.567%; route: 1.563, 23.075%; tC2Q: 2.260, 33.358%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path18</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.218</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.673</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_15_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.797</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.211</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td>core0/n229_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.673</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n229_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.673</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_15_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td>core0/reg_wb_data_15_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td>core0/reg_wb_data_15_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>6</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.515, 37.272%; route: 1.972, 29.230%; tC2Q: 2.260, 33.498%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path19</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.306</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.585</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_22_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.327</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td>core0/n159_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n159_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.363</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td>core0/n158_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n158_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.398</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td>core0/n157_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n157_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.433</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td>core0/n156_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n156_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.468</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td>core0/n155_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n155_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.503</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td>core0/n154_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n154_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.539</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td>core0/n153_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n153_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.574</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td>core0/n152_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.044</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C40[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n152_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.214</td>
|
|
<td>0.170</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][B]</td>
|
|
<td>core0/n222_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.585</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n222_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.585</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_22_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][B]</td>
|
|
<td>core0/reg_wb_data_22_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C40[0][B]</td>
|
|
<td>core0/reg_wb_data_22_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>7</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.670, 40.094%; route: 1.729, 25.969%; tC2Q: 2.260, 33.937%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path20</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.345</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.546</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_14_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.011</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/n168_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n168_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.046</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/n167_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n167_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.081</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/n166_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n166_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.116</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/n165_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n165_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.151</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/n164_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n164_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.187</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/n163_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n163_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.222</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td>core0/n162_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n162_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.257</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td>core0/n161_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n161_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.292</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td>core0/n160_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.762</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n160_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.175</td>
|
|
<td>0.413</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C39[0][B]</td>
|
|
<td>core0/n230_s0/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.546</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C39[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n230_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.546</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C39[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_14_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C39[0][B]</td>
|
|
<td>core0/reg_wb_data_14_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C39[0][B]</td>
|
|
<td>core0/reg_wb_data_14_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>6</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.388, 36.076%; route: 1.972, 29.787%; tC2Q: 2.260, 34.137%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path21</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.370</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.521</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/rs1_3_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_3_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R11C43[1][A]</td>
|
|
<td>core0/rs1_3_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>3</td>
|
|
<td>R11C43[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/rs1_3_s2/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.819</td>
|
|
<td>0.661</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C41[3][A]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_0_s4/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.368</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R14C41[3][A]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_0_s4/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.370</td>
|
|
<td>0.001</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[0][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_0_s3/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.832</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_0_s3/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.004</td>
|
|
<td>0.172</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_0_s1/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.375</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>32</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_0_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.093</td>
|
|
<td>0.717</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C39[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_0_s0/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.546</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C39[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_0_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.963</td>
|
|
<td>0.418</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[0][A]</td>
|
|
<td>core0/n105_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.533</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R13C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n105_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.533</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C41[0][B]</td>
|
|
<td>core0/n104_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.568</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C41[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n104_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.568</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[1][A]</td>
|
|
<td>core0/n103_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.603</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n103_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.603</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[1][B]</td>
|
|
<td>core0/n102_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.073</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n102_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.972</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C43[1][A]</td>
|
|
<td>core0/n203_s2/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.521</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C43[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n203_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.521</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C43[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_3_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C43[1][A]</td>
|
|
<td>core0/alu_out_3_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R12C43[1][A]</td>
|
|
<td>core0/alu_out_3_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>8</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 3.494, 52.984%; route: 2.869, 43.499%; tC2Q: 0.232, 3.518%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path22</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.374</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.517</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_5_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.975</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td>core0/n169_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.445</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n169_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.968</td>
|
|
<td>0.522</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C43[2][A]</td>
|
|
<td>core0/n201_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.517</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C43[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n201_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.517</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C43[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_5_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C43[2][A]</td>
|
|
<td>core0/alu_out_5_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R12C43[2][A]</td>
|
|
<td>core0/alu_out_5_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.250, 34.132%; route: 2.081, 31.578%; tC2Q: 2.260, 34.290%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path23</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.390</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.501</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_2_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.340</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.952</td>
|
|
<td>0.612</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C43[0][B]</td>
|
|
<td>core0/n204_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.501</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C43[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n204_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.501</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C43[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_2_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C43[0][B]</td>
|
|
<td>core0/alu_out_2_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R12C43[0][B]</td>
|
|
<td>core0/alu_out_2_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.144, 32.608%; route: 2.171, 33.021%; tC2Q: 2.260, 34.372%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path24</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.491</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.400</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/reg_wb_data_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.340</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.400</td>
|
|
<td>1.060</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C42[2][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_2_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C42[2][B]</td>
|
|
<td>core0/reg_wb_data_2_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R12C42[2][B]</td>
|
|
<td>core0/reg_wb_data_2_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.595, 24.638%; route: 2.619, 40.453%; tC2Q: 2.260, 34.910%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path25</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>3.496</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>7.395</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/alu_out_4_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>32</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKB</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.186</td>
|
|
<td>2.260</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DO[1]</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.084</td>
|
|
<td>0.899</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td>core0/register_rs1_data[0]_DOAL_G_1_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.639</td>
|
|
<td>0.555</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[3][B]</td>
|
|
<td style=" background: #97FFFF;">core0/register_rs1_data[0]_DOAL_G_1_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.300</td>
|
|
<td>0.660</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td>core0/n173_s/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C37[0][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n173_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.870</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td>core0/n172_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n172_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.905</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td>core0/n171_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.035</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C37[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n171_s/COUT</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.940</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td>core0/n170_s/CIN</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.410</td>
|
|
<td>0.470</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R12C37[2][A]</td>
|
|
<td style=" background: #97FFFF;">core0/n170_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6.933</td>
|
|
<td>0.522</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R12C43[1][B]</td>
|
|
<td>core0/n202_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.395</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R12C43[1][B]</td>
|
|
<td style=" background: #97FFFF;">core0/n202_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7.395</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C43[1][B]</td>
|
|
<td style=" font-weight:bold;">core0/alu_out_4_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C43[1][B]</td>
|
|
<td>core0/alu_out_4_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R12C43[1][B]</td>
|
|
<td>core0/alu_out_4_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 2.127, 32.888%; route: 2.081, 32.175%; tC2Q: 2.260, 34.937%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
|
<h3>Path1</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.199</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.308</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_30_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][B]</td>
|
|
<td>core0/reg_wb_data_30_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C42[1][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_30_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.308</td>
|
|
<td>0.246</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[30]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.246, 54.955%; tC2Q: 0.202, 45.045%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path2</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.203</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.312</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_7_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td>core0/reg_wb_data_7_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_7_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.312</td>
|
|
<td>0.250</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[7]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.250, 55.351%; tC2Q: 0.202, 44.649%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path3</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.203</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.312</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td>core0/reg_wb_data_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C38[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_6_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.312</td>
|
|
<td>0.250</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[6]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.250, 55.351%; tC2Q: 0.202, 44.649%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path4</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.213</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.322</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_9_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td>core0/reg_wb_data_9_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_9_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.322</td>
|
|
<td>0.260</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[9]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path5</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.215</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R11C42[0][A]</td>
|
|
<td>core0/reg_wb_data_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R11C42[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.323</td>
|
|
<td>0.262</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[31]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path6</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.215</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_21_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>core0/reg_wb_data_21_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_21_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.323</td>
|
|
<td>0.262</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[21]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path7</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.215</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_20_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td>core0/reg_wb_data_20_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_20_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.323</td>
|
|
<td>0.262</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[20]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path8</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.215</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_11_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td>core0/reg_wb_data_11_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_11_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.323</td>
|
|
<td>0.262</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[11]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path9</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.215</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_10_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td>core0/reg_wb_data_10_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C38[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_10_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.323</td>
|
|
<td>0.262</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[10]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path10</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.215</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td>core0/reg_wb_data_8_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C38[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_8_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.323</td>
|
|
<td>0.262</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[8]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path11</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.215</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_5_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td>core0/reg_wb_data_5_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_5_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.323</td>
|
|
<td>0.262</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[5]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path12</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.215</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.323</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td>core0/reg_wb_data_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.323</td>
|
|
<td>0.262</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[4]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path13</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.227</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.335</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_29_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][B]</td>
|
|
<td>core0/reg_wb_data_29_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R14C42[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_29_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.335</td>
|
|
<td>0.274</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[29]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.274, 57.536%; tC2Q: 0.202, 42.464%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path14</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.321</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.430</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_25_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>core0/reg_wb_data_25_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_25_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.430</td>
|
|
<td>0.368</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[25]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.368, 64.589%; tC2Q: 0.202, 35.411%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path15</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.321</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.430</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td>core0/reg_wb_data_24_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_24_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.430</td>
|
|
<td>0.368</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[24]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.368, 64.589%; tC2Q: 0.202, 35.411%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path16</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.325</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.434</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_27_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C42[1][A]</td>
|
|
<td>core0/reg_wb_data_27_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C42[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_27_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.434</td>
|
|
<td>0.372</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[27]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.372, 64.834%; tC2Q: 0.202, 35.166%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path17</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.337</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.445</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_17_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][B]</td>
|
|
<td>core0/reg_wb_data_17_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R14C40[2][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_17_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.445</td>
|
|
<td>0.384</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[17]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path18</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.337</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.445</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_15_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td>core0/reg_wb_data_15_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_15_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.445</td>
|
|
<td>0.384</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[15]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path19</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.337</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.445</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_14_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C39[0][B]</td>
|
|
<td>core0/reg_wb_data_14_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R15C39[0][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_14_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.445</td>
|
|
<td>0.384</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[14]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path20</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.337</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.445</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_0_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[2][A]</td>
|
|
<td>core0/reg_wb_data_0_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C39[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_0_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.445</td>
|
|
<td>0.384</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[0]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path21</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.353</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.461</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_23_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C40[2][A]</td>
|
|
<td>core0/reg_wb_data_23_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R14C40[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_23_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.461</td>
|
|
<td>0.400</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[23]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.400, 66.427%; tC2Q: 0.202, 33.573%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path22</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.353</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.461</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_1_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R12C42[2][A]</td>
|
|
<td>core0/reg_wb_data_1_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R12C42[2][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_1_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.461</td>
|
|
<td>0.400</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[1]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.400, 66.427%; tC2Q: 0.202, 33.573%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path23</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.364</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.473</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_19_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][A]</td>
|
|
<td>core0/reg_wb_data_19_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R14C42[1][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_19_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.473</td>
|
|
<td>0.411</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[19]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.411, 67.040%; tC2Q: 0.202, 32.960%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path24</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.364</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.473</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_13_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C40[0][A]</td>
|
|
<td>core0/reg_wb_data_13_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R15C40[0][A]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_13_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.473</td>
|
|
<td>0.411</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[13]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.411, 67.040%; tC2Q: 0.202, 32.960%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path25</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.364</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.473</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>1.109</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>core0/reg_wb_data_3_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][B]</td>
|
|
<td>core0/reg_wb_data_3_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C38[2][B]</td>
|
|
<td style=" font-weight:bold;">core0/reg_wb_data_3_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.473</td>
|
|
<td>0.411</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td style=" font-weight:bold;">core0/register_register_0_0_s/DI[3]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>206</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s/CLKA</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.109</td>
|
|
<td>0.249</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>BSRAM_R10[11]</td>
|
|
<td>core0/register_register_0_0_s</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.000, 0.000%; route: 0.411, 67.040%; tC2Q: 0.202, 32.960%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>No recovery paths to report!</h4>
|
|
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>No removal paths to report!</h4>
|
|
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
|
|
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
<h3>MPW1</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_30_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_30_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_30_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW2</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_28_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_28_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_28_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW3</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW4</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_16_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_16_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_16_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW5</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_0_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_0_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_0_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW6</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>core0/reg_inst_28_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>core0/reg_inst_28_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>core0/reg_inst_28_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW7</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>core0/reg_wb_data_11_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>core0/reg_wb_data_11_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>core0/reg_wb_data_11_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW8</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>core0/reg_wb_data_12_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>core0/reg_wb_data_12_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>core0/reg_wb_data_12_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW9</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>core0/reg_inst_29_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>core0/reg_inst_29_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>core0/reg_inst_29_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW10</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>core0/reg_wb_data_13_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>core0/reg_wb_data_13_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>core0/reg_wb_data_13_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
|
|
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">NET NAME</th>
|
|
<th class="label">WORST SLACK</th>
|
|
<th class="label">MAX DELAY</th>
|
|
</tr>
|
|
<tr>
|
|
<td>206</td>
|
|
<td>clock_d</td>
|
|
<td>2.196</td>
|
|
<td>0.261</td>
|
|
</tr>
|
|
<tr>
|
|
<td>36</td>
|
|
<td>n312_5</td>
|
|
<td>8.189</td>
|
|
<td>0.966</td>
|
|
</tr>
|
|
<tr>
|
|
<td>32</td>
|
|
<td>n12_17</td>
|
|
<td>6.024</td>
|
|
<td>0.698</td>
|
|
</tr>
|
|
<tr>
|
|
<td>32</td>
|
|
<td>register_rs1_data[0]_DOAL_G_0_3</td>
|
|
<td>2.347</td>
|
|
<td>0.934</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25</td>
|
|
<td>i_imm[7]</td>
|
|
<td>5.967</td>
|
|
<td>0.956</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23</td>
|
|
<td>pc[2]</td>
|
|
<td>7.004</td>
|
|
<td>0.919</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22</td>
|
|
<td>n213_4</td>
|
|
<td>6.135</td>
|
|
<td>0.725</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21</td>
|
|
<td>n314_3</td>
|
|
<td>6.491</td>
|
|
<td>0.967</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21</td>
|
|
<td>reg_wb_data_31_6</td>
|
|
<td>6.385</td>
|
|
<td>0.755</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21</td>
|
|
<td>pc[0]</td>
|
|
<td>7.332</td>
|
|
<td>0.559</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
|
|
<h4>Report Command:report_route_congestion -max_grids 10</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">GRID LOC</th>
|
|
<th class="label">ROUTE CONGESTIONS</th>
|
|
</tr>
|
|
<tr>
|
|
<td>R11C38</td>
|
|
<td>84.72%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R11C39</td>
|
|
<td>83.33%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R12C38</td>
|
|
<td>83.33%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R11C37</td>
|
|
<td>81.94%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C45</td>
|
|
<td>81.94%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C42</td>
|
|
<td>80.56%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C44</td>
|
|
<td>80.56%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R12C44</td>
|
|
<td>80.56%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C37</td>
|
|
<td>80.56%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R12C43</td>
|
|
<td>79.17%</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
|
|
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">SDC Command Type</th>
|
|
<th class="label">State</th>
|
|
<th class="label">Detail Command</th>
|
|
</tr>
|
|
</table>
|
|
</div><!-- content -->
|
|
</body>
|
|
</html>
|