mirror of
https://github.com/mii443/tangprimer-riscv.git
synced 2025-08-22 16:25:39 +00:00
817 lines
32 KiB
Plaintext
817 lines
32 KiB
Plaintext
#! /c/Source/iverilog-install/bin/vvp
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:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "C:\iverilog\lib\ivl\system.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
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:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
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:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
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:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
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S_0000021801ba52c0 .scope module, "memory_tb" "memory_tb" 2 1;
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.timescale 0 0;
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P_0000021801be7060 .param/l "RATE" 0 2 3, +C4<00000000000000000000000000000001>;
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v0000021801c530f0_0 .net "LED", 0 0, L_0000021801be1260; 1 drivers
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v0000021801c521f0_0 .net "TX", 0 0, L_0000021801be13b0; 1 drivers
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v0000021801c51d90_0 .var "clk", 0 0;
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S_0000021801bc85c0 .scope module, "top" "TOP" 2 17, 3 1 0, S_0000021801ba52c0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "clock";
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.port_info 1 /OUTPUT 1 "LED";
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.port_info 2 /OUTPUT 1 "tx";
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v0000021801c520b0_0 .net "LED", 0 0, L_0000021801be1260; alias, 1 drivers
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v0000021801c51b10_0 .net "clock", 0 0, v0000021801c51d90_0; 1 drivers
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v0000021801c51ed0_0 .net "iaddr", 31 0, v0000021801c4e5a0_0; 1 drivers
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v0000021801c53550_0 .net "inst", 31 0, L_0000021801c52ab0; 1 drivers
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v0000021801c52970_0 .net "raddr", 31 0, v0000021801c4d380_0; 1 drivers
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v0000021801c523d0_0 .net "rdata", 31 0, L_0000021801c52a10; 1 drivers
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v0000021801c525b0_0 .net "tx", 0 0, L_0000021801be13b0; alias, 1 drivers
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v0000021801c52f10_0 .net "tx_busy", 0 0, L_0000021801c52dd0; 1 drivers
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v0000021801c51bb0_0 .net "tx_data", 7 0, L_0000021801be1420; 1 drivers
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v0000021801c51f70_0 .net "tx_start", 0 0, L_0000021801be1a40; 1 drivers
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v0000021801c52c90_0 .net "wdata", 31 0, L_0000021801be1b20; 1 drivers
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v0000021801c52d30_0 .net "wen", 0 0, L_0000021801be1880; 1 drivers
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S_0000021801bc8750 .scope module, "core0" "CORE" 3 36, 4 3 0, S_0000021801bc85c0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "clock";
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.port_info 1 /OUTPUT 1 "tx_start";
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.port_info 2 /OUTPUT 8 "tx_data";
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.port_info 3 /OUTPUT 32 "raddr";
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.port_info 4 /OUTPUT 32 "iaddr";
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.port_info 5 /OUTPUT 1 "wen";
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.port_info 6 /OUTPUT 32 "wdata";
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.port_info 7 /INPUT 32 "inst";
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.port_info 8 /INPUT 32 "rdata";
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P_0000021801bec390 .param/l "ST_ACCESS" 1 4 59, +C4<00000000000000000000000000000011>;
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P_0000021801bec3c8 .param/l "ST_EX" 1 4 58, +C4<00000000000000000000000000000010>;
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P_0000021801bec400 .param/l "ST_ID" 1 4 57, +C4<00000000000000000000000000000001>;
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P_0000021801bec438 .param/l "ST_IF" 1 4 56, +C4<00000000000000000000000000000000>;
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P_0000021801bec470 .param/l "ST_WB" 1 4 60, +C4<00000000000000000000000000000100>;
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L_0000021801be1490 .functor BUFZ 32, L_0000021801c52b50, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
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L_0000021801be1110 .functor BUFZ 32, L_0000021801c53190, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
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L_0000021801be1a40 .functor BUFZ 1, v0000021801c4df60_0, C4<0>, C4<0>, C4<0>;
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L_0000021801be1420 .functor BUFZ 8, v0000021801c4ed20_0, C4<00000000>, C4<00000000>, C4<00000000>;
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L_0000021801be1b20 .functor BUFZ 32, v0000021801c4de20_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
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L_0000021801be1880 .functor BUFZ 1, v0000021801c4d920_0, C4<0>, C4<0>, C4<0>;
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v0000021801be51d0_0 .var "REGISTER_TEST", 31 0;
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v0000021801be5770_0 .net *"_ivl_0", 31 0, L_0000021801c52b50; 1 drivers
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v0000021801be5810_0 .net *"_ivl_10", 6 0, L_0000021801c51c50; 1 drivers
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L_0000021801c603e8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
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v0000021801be5a90_0 .net *"_ivl_13", 1 0, L_0000021801c603e8; 1 drivers
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v0000021801be5db0_0 .net *"_ivl_17", 0 0, L_0000021801c53230; 1 drivers
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v0000021801be5e50_0 .net *"_ivl_18", 19 0, L_0000021801c51890; 1 drivers
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v0000021801c4d4c0_0 .net *"_ivl_2", 6 0, L_0000021801c53690; 1 drivers
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v0000021801c4e960_0 .net *"_ivl_21", 10 0, L_0000021801c51930; 1 drivers
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v0000021801c4da60_0 .net *"_ivl_22", 30 0, L_0000021801c519d0; 1 drivers
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L_0000021801c60430 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
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v0000021801c4d560_0 .net *"_ivl_27", 0 0, L_0000021801c60430; 1 drivers
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v0000021801c4d600_0 .net *"_ivl_29", 0 0, L_0000021801c52010; 1 drivers
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v0000021801c4eb40_0 .net *"_ivl_30", 19 0, L_0000021801cb8550; 1 drivers
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v0000021801c4d420_0 .net *"_ivl_33", 10 0, L_0000021801cb9ef0; 1 drivers
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v0000021801c4e140_0 .net *"_ivl_34", 30 0, L_0000021801cb8d70; 1 drivers
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L_0000021801c60478 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
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v0000021801c4e640_0 .net *"_ivl_39", 0 0, L_0000021801c60478; 1 drivers
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L_0000021801c603a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
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v0000021801c4e6e0_0 .net *"_ivl_5", 1 0, L_0000021801c603a0; 1 drivers
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v0000021801c4e1e0_0 .net *"_ivl_8", 31 0, L_0000021801c53190; 1 drivers
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v0000021801c4e820_0 .var "alu_out", 31 0;
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v0000021801c4e780_0 .var "b_imm", 12 0;
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v0000021801c4e500_0 .net "clock", 0 0, v0000021801c51d90_0; alias, 1 drivers
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v0000021801c4e280_0 .var "funct3", 2 0;
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v0000021801c4e320_0 .var "funct7", 6 0;
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v0000021801c4e8c0_0 .var/i "i", 31 0;
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v0000021801c4d740_0 .var "i_imm", 11 0;
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v0000021801c4ea00_0 .net "i_imm_sext", 31 0, L_0000021801c51a70; 1 drivers
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v0000021801c4d7e0_0 .net "iaddr", 31 0, v0000021801c4e5a0_0; alias, 1 drivers
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v0000021801c4ef00_0 .net "inst", 31 0, L_0000021801c52ab0; alias, 1 drivers
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v0000021801c4ec80_0 .var "j_imm", 20 0;
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v0000021801c4e460_0 .var "opcode", 6 0;
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v0000021801c4d9c0_0 .var "pc", 31 0;
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v0000021801c4d880_0 .var "pc_p4", 31 0;
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v0000021801c4dc40_0 .net "raddr", 31 0, v0000021801c4d380_0; alias, 1 drivers
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v0000021801c4d6a0_0 .var "rd", 4 0;
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v0000021801c4e3c0_0 .net "rdata", 31 0, L_0000021801c52a10; alias, 1 drivers
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v0000021801c4e5a0_0 .var "reg_iaddr", 31 0;
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v0000021801c4db00_0 .var "reg_inst", 31 0;
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v0000021801c4d380_0 .var "reg_raddr", 31 0;
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v0000021801c4ed20_0 .var "reg_tx_data", 7 0;
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v0000021801c4df60_0 .var "reg_tx_start", 0 0;
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v0000021801c4eaa0_0 .var "reg_wb_data", 31 0;
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v0000021801c4ebe0_0 .var "reg_wb_wen", 0 0;
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v0000021801c4de20_0 .var "reg_wdata", 31 0;
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v0000021801c4d920_0 .var "reg_wen", 0 0;
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v0000021801c4ee60 .array "register", 0 31, 31 0;
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v0000021801c4e000_0 .var "rs1", 4 0;
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v0000021801c4edc0_0 .net "rs1_data", 31 0, L_0000021801be1490; 1 drivers
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v0000021801c4d060_0 .var "rs2", 4 0;
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v0000021801c4d100_0 .net "rs2_data", 31 0, L_0000021801be1110; 1 drivers
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v0000021801c4d2e0_0 .var "s_imm", 11 0;
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v0000021801c4dba0_0 .net "s_imm_sext", 31 0, L_0000021801cb9e50; 1 drivers
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v0000021801c4e0a0_0 .var "stage", 3 0;
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v0000021801c4d240_0 .net "tx_data", 7 0, L_0000021801be1420; alias, 1 drivers
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v0000021801c4d1a0_0 .net "tx_start", 0 0, L_0000021801be1a40; alias, 1 drivers
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v0000021801c4dce0_0 .var "u_imm", 31 0;
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v0000021801c4dd80_0 .net "wdata", 31 0, L_0000021801be1b20; alias, 1 drivers
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v0000021801c4dec0_0 .net "wen", 0 0, L_0000021801be1880; alias, 1 drivers
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E_0000021801be73e0 .event posedge, v0000021801c4e500_0;
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L_0000021801c52b50 .array/port v0000021801c4ee60, L_0000021801c53690;
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L_0000021801c53690 .concat [ 5 2 0 0], v0000021801c4e000_0, L_0000021801c603a0;
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L_0000021801c53190 .array/port v0000021801c4ee60, L_0000021801c51c50;
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L_0000021801c51c50 .concat [ 5 2 0 0], v0000021801c4d060_0, L_0000021801c603e8;
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L_0000021801c53230 .part v0000021801c4d740_0, 11, 1;
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LS_0000021801c51890_0_0 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
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LS_0000021801c51890_0_4 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
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LS_0000021801c51890_0_8 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
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LS_0000021801c51890_0_12 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
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LS_0000021801c51890_0_16 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
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LS_0000021801c51890_1_0 .concat [ 4 4 4 4], LS_0000021801c51890_0_0, LS_0000021801c51890_0_4, LS_0000021801c51890_0_8, LS_0000021801c51890_0_12;
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LS_0000021801c51890_1_4 .concat [ 4 0 0 0], LS_0000021801c51890_0_16;
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L_0000021801c51890 .concat [ 16 4 0 0], LS_0000021801c51890_1_0, LS_0000021801c51890_1_4;
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L_0000021801c51930 .part v0000021801c4d740_0, 0, 11;
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L_0000021801c519d0 .concat [ 11 20 0 0], L_0000021801c51930, L_0000021801c51890;
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L_0000021801c51a70 .concat [ 31 1 0 0], L_0000021801c519d0, L_0000021801c60430;
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L_0000021801c52010 .part v0000021801c4d2e0_0, 11, 1;
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LS_0000021801cb8550_0_0 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
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LS_0000021801cb8550_0_4 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
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LS_0000021801cb8550_0_8 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
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LS_0000021801cb8550_0_12 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
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LS_0000021801cb8550_0_16 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
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LS_0000021801cb8550_1_0 .concat [ 4 4 4 4], LS_0000021801cb8550_0_0, LS_0000021801cb8550_0_4, LS_0000021801cb8550_0_8, LS_0000021801cb8550_0_12;
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LS_0000021801cb8550_1_4 .concat [ 4 0 0 0], LS_0000021801cb8550_0_16;
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L_0000021801cb8550 .concat [ 16 4 0 0], LS_0000021801cb8550_1_0, LS_0000021801cb8550_1_4;
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L_0000021801cb9ef0 .part v0000021801c4d2e0_0, 0, 11;
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L_0000021801cb8d70 .concat [ 11 20 0 0], L_0000021801cb9ef0, L_0000021801cb8550;
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L_0000021801cb9e50 .concat [ 31 1 0 0], L_0000021801cb8d70, L_0000021801c60478;
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S_0000021801ba6d00 .scope module, "mem0" "MEMORY" 3 26, 5 1 0, S_0000021801bc85c0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "clock";
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.port_info 1 /INPUT 32 "raddr";
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.port_info 2 /INPUT 32 "iaddr";
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.port_info 3 /INPUT 1 "wen";
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.port_info 4 /INPUT 32 "wdata";
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.port_info 5 /OUTPUT 32 "inst";
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.port_info 6 /OUTPUT 32 "rdata";
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v0000021801c4fed0_0 .net *"_ivl_0", 7 0, L_0000021801c528d0; 1 drivers
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v0000021801c4f250_0 .net *"_ivl_10", 31 0, L_0000021801c52e70; 1 drivers
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v0000021801c50330_0 .net *"_ivl_12", 7 0, L_0000021801c534b0; 1 drivers
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L_0000021801c601f0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
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v0000021801c4f570_0 .net/2u *"_ivl_14", 31 0, L_0000021801c601f0; 1 drivers
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v0000021801c4fc50_0 .net *"_ivl_16", 31 0, L_0000021801c535f0; 1 drivers
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v0000021801c50bf0_0 .net *"_ivl_18", 7 0, L_0000021801c53410; 1 drivers
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L_0000021801c60160 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
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v0000021801c50e70_0 .net/2u *"_ivl_2", 31 0, L_0000021801c60160; 1 drivers
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L_0000021801c60238 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>;
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v0000021801c50b50_0 .net/2u *"_ivl_20", 31 0, L_0000021801c60238; 1 drivers
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v0000021801c4fe30_0 .net *"_ivl_22", 31 0, L_0000021801c51e30; 1 drivers
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v0000021801c50d30_0 .net *"_ivl_26", 7 0, L_0000021801c53370; 1 drivers
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L_0000021801c60280 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
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v0000021801c50150_0 .net/2u *"_ivl_28", 31 0, L_0000021801c60280; 1 drivers
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v0000021801c50470_0 .net *"_ivl_30", 31 0, L_0000021801c52290; 1 drivers
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v0000021801c505b0_0 .net *"_ivl_32", 7 0, L_0000021801c53050; 1 drivers
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L_0000021801c602c8 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
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v0000021801c506f0_0 .net/2u *"_ivl_34", 31 0, L_0000021801c602c8; 1 drivers
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v0000021801c4f110_0 .net *"_ivl_36", 31 0, L_0000021801c52330; 1 drivers
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v0000021801c4f6b0_0 .net *"_ivl_38", 7 0, L_0000021801c526f0; 1 drivers
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v0000021801c50510_0 .net *"_ivl_4", 31 0, L_0000021801c52650; 1 drivers
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L_0000021801c60310 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
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v0000021801c50650_0 .net/2u *"_ivl_40", 31 0, L_0000021801c60310; 1 drivers
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v0000021801c508d0_0 .net *"_ivl_42", 31 0, L_0000021801c52bf0; 1 drivers
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v0000021801c4f070_0 .net *"_ivl_44", 7 0, L_0000021801c53730; 1 drivers
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L_0000021801c60358 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>;
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v0000021801c50ab0_0 .net/2u *"_ivl_46", 31 0, L_0000021801c60358; 1 drivers
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v0000021801c4f930_0 .net *"_ivl_48", 31 0, L_0000021801c52470; 1 drivers
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v0000021801c4f610_0 .net *"_ivl_6", 7 0, L_0000021801c52fb0; 1 drivers
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L_0000021801c601a8 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
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v0000021801c4f750_0 .net/2u *"_ivl_8", 31 0, L_0000021801c601a8; 1 drivers
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v0000021801c50c90_0 .net "clock", 0 0, v0000021801c51d90_0; alias, 1 drivers
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v0000021801c50790_0 .var/i "i", 31 0;
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v0000021801c4ff70_0 .net "iaddr", 31 0, v0000021801c4e5a0_0; alias, 1 drivers
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v0000021801c500b0_0 .net "inst", 31 0, L_0000021801c52ab0; alias, 1 drivers
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v0000021801c4f7f0 .array "mem", 0 32, 7 0;
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v0000021801c4fcf0_0 .net "raddr", 31 0, v0000021801c4d380_0; alias, 1 drivers
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v0000021801c50a10_0 .net "rdata", 31 0, L_0000021801c52a10; alias, 1 drivers
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v0000021801c50970_0 .var "reg_raddr", 31 0;
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v0000021801c50dd0_0 .net "wdata", 31 0, L_0000021801be1b20; alias, 1 drivers
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v0000021801c50830_0 .net "wen", 0 0, L_0000021801be1880; alias, 1 drivers
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L_0000021801c528d0 .array/port v0000021801c4f7f0, L_0000021801c52650;
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L_0000021801c52650 .arith/sum 32, v0000021801c4e5a0_0, L_0000021801c60160;
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L_0000021801c52fb0 .array/port v0000021801c4f7f0, L_0000021801c52e70;
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L_0000021801c52e70 .arith/sum 32, v0000021801c4e5a0_0, L_0000021801c601a8;
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L_0000021801c534b0 .array/port v0000021801c4f7f0, L_0000021801c535f0;
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L_0000021801c535f0 .arith/sum 32, v0000021801c4e5a0_0, L_0000021801c601f0;
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L_0000021801c53410 .array/port v0000021801c4f7f0, L_0000021801c51e30;
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L_0000021801c51e30 .arith/sum 32, v0000021801c4e5a0_0, L_0000021801c60238;
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L_0000021801c52ab0 .concat [ 8 8 8 8], L_0000021801c53410, L_0000021801c534b0, L_0000021801c52fb0, L_0000021801c528d0;
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L_0000021801c53370 .array/port v0000021801c4f7f0, L_0000021801c52290;
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L_0000021801c52290 .arith/sum 32, v0000021801c4d380_0, L_0000021801c60280;
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L_0000021801c53050 .array/port v0000021801c4f7f0, L_0000021801c52330;
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L_0000021801c52330 .arith/sum 32, v0000021801c4d380_0, L_0000021801c602c8;
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L_0000021801c526f0 .array/port v0000021801c4f7f0, L_0000021801c52bf0;
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L_0000021801c52bf0 .arith/sum 32, v0000021801c4d380_0, L_0000021801c60310;
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L_0000021801c53730 .array/port v0000021801c4f7f0, L_0000021801c52470;
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L_0000021801c52470 .arith/sum 32, v0000021801c4d380_0, L_0000021801c60358;
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L_0000021801c52a10 .concat [ 8 8 8 8], L_0000021801c53730, L_0000021801c526f0, L_0000021801c53050, L_0000021801c53370;
|
|
S_0000021801bc2830 .scope module, "uart0" "UART" 3 11, 6 1 0, S_0000021801bc85c0;
|
|
.timescale 0 0;
|
|
.port_info 0 /INPUT 1 "clock";
|
|
.port_info 1 /INPUT 8 "data_in";
|
|
.port_info 2 /INPUT 1 "start";
|
|
.port_info 3 /OUTPUT 1 "tx_busy";
|
|
.port_info 4 /OUTPUT 1 "tx";
|
|
.port_info 5 /OUTPUT 1 "LED";
|
|
P_0000021801ba6fd0 .param/l "FPGA_FREQ" 1 6 13, +C4<00000000000000000000000000011011>;
|
|
P_0000021801ba7008 .param/l "S_END" 1 6 43, +C4<00000000000000000000000000000100>;
|
|
P_0000021801ba7040 .param/l "S_IDLE" 1 6 39, +C4<00000000000000000000000000000000>;
|
|
P_0000021801ba7078 .param/l "S_P" 1 6 42, +C4<00000000000000000000000000000011>;
|
|
P_0000021801ba70b0 .param/l "S_SEND" 1 6 41, +C4<00000000000000000000000000000010>;
|
|
P_0000021801ba70e8 .param/l "S_START" 1 6 40, +C4<00000000000000000000000000000001>;
|
|
P_0000021801ba7120 .param/l "TX_CLOCK_COUNT_MAX" 1 6 15, +C4<00000000000000000000000000000000000000000000000000000000011101001>;
|
|
P_0000021801ba7158 .param/l "UART_FREQ" 1 6 14, +C4<00000000000000011100001000000000>;
|
|
L_0000021801be1260 .functor BUFZ 1, v0000021801c4f890_0, C4<0>, C4<0>, C4<0>;
|
|
L_0000021801be13b0 .functor BUFZ 1, v0000021801c52790_0, C4<0>, C4<0>, C4<0>;
|
|
v0000021801c4f1b0_0 .net "LED", 0 0, L_0000021801be1260; alias, 1 drivers
|
|
L_0000021801c600d0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
|
v0000021801c4fd90_0 .net *"_ivl_11", 26 0, L_0000021801c600d0; 1 drivers
|
|
L_0000021801c60118 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
|
v0000021801c501f0_0 .net/2u *"_ivl_12", 31 0, L_0000021801c60118; 1 drivers
|
|
L_0000021801c60088 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
|
v0000021801c50f10_0 .net/2u *"_ivl_2", 31 0, L_0000021801c60088; 1 drivers
|
|
v0000021801c4f2f0_0 .net *"_ivl_8", 31 0, L_0000021801c52830; 1 drivers
|
|
v0000021801c4f9d0_0 .net "clock", 0 0, v0000021801c51d90_0; alias, 1 drivers
|
|
v0000021801c4f390_0 .var "clock_count", 31 0;
|
|
v0000021801c4f430_0 .var "data", 7 0;
|
|
v0000021801c4f4d0_0 .net "data_in", 7 0, L_0000021801be1420; alias, 1 drivers
|
|
v0000021801c4f890_0 .var "led_flag", 0 0;
|
|
v0000021801c4fa70_0 .var "local_in", 7 0;
|
|
v0000021801c4fb10_0 .var "local_start", 0 0;
|
|
v0000021801c4fbb0_0 .var "send_count", 3 0;
|
|
v0000021801c50010_0 .net "start", 0 0, L_0000021801be1a40; alias, 1 drivers
|
|
v0000021801c50290_0 .var "state", 4 0;
|
|
v0000021801c503d0_0 .net "tx", 0 0, L_0000021801be13b0; alias, 1 drivers
|
|
v0000021801c52510_0 .net "tx_busy", 0 0, L_0000021801c52dd0; alias, 1 drivers
|
|
v0000021801c532d0_0 .net "tx_clock", 0 0, L_0000021801c52150; 1 drivers
|
|
v0000021801c52790_0 .var "tx_reg", 0 0;
|
|
L_0000021801c52150 .cmp/eq 32, v0000021801c4f390_0, L_0000021801c60088;
|
|
L_0000021801c52830 .concat [ 5 27 0 0], v0000021801c50290_0, L_0000021801c600d0;
|
|
L_0000021801c52dd0 .cmp/ne 32, L_0000021801c52830, L_0000021801c60118;
|
|
.scope S_0000021801bc2830;
|
|
T_0 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4f390_0, 0, 32;
|
|
%end;
|
|
.thread T_0;
|
|
.scope S_0000021801bc2830;
|
|
T_1 ;
|
|
%wait E_0000021801be73e0;
|
|
%load/vec4 v0000021801c4f390_0;
|
|
%pad/u 65;
|
|
%cmpi/e 233, 0, 65;
|
|
%jmp/0xz T_1.0, 4;
|
|
%pushi/vec4 0, 0, 32;
|
|
%assign/vec4 v0000021801c4f390_0, 0;
|
|
%load/vec4 v0000021801c4f890_0;
|
|
%inv;
|
|
%assign/vec4 v0000021801c4f890_0, 0;
|
|
%jmp T_1.1;
|
|
T_1.0 ;
|
|
%load/vec4 v0000021801c4f390_0;
|
|
%addi 1, 0, 32;
|
|
%assign/vec4 v0000021801c4f390_0, 0;
|
|
T_1.1 ;
|
|
%jmp T_1;
|
|
.thread T_1;
|
|
.scope S_0000021801bc2830;
|
|
T_2 ;
|
|
%wait E_0000021801be73e0;
|
|
%load/vec4 v0000021801c4f4d0_0;
|
|
%assign/vec4 v0000021801c4fa70_0, 0;
|
|
%load/vec4 v0000021801c50010_0;
|
|
%assign/vec4 v0000021801c4fb10_0, 0;
|
|
%jmp T_2;
|
|
.thread T_2;
|
|
.scope S_0000021801bc2830;
|
|
T_3 ;
|
|
%pushi/vec4 0, 0, 5;
|
|
%store/vec4 v0000021801c50290_0, 0, 5;
|
|
%pushi/vec4 0, 0, 4;
|
|
%store/vec4 v0000021801c4fbb0_0, 0, 4;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0000021801c52790_0, 0, 1;
|
|
%end;
|
|
.thread T_3;
|
|
.scope S_0000021801bc2830;
|
|
T_4 ;
|
|
%wait E_0000021801be73e0;
|
|
%load/vec4 v0000021801c50290_0;
|
|
%dup/vec4;
|
|
%pushi/vec4 0, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_4.0, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 1, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_4.1, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 2, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_4.2, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 3, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_4.3, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 4, 0, 5;
|
|
%cmp/u;
|
|
%jmp/1 T_4.4, 6;
|
|
%jmp T_4.5;
|
|
T_4.0 ;
|
|
%load/vec4 v0000021801c532d0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_4.6, 8;
|
|
%load/vec4 v0000021801c4fb10_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_4.8, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%pushi/vec4 1, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
%jmp T_4.9;
|
|
T_4.8 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%pushi/vec4 0, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
T_4.9 ;
|
|
T_4.6 ;
|
|
%jmp T_4.5;
|
|
T_4.1 ;
|
|
%load/vec4 v0000021801c532d0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_4.10, 8;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%load/vec4 v0000021801c4fa70_0;
|
|
%assign/vec4 v0000021801c4f430_0, 0;
|
|
%pushi/vec4 0, 0, 4;
|
|
%assign/vec4 v0000021801c4fbb0_0, 0;
|
|
%pushi/vec4 2, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
%jmp T_4.11;
|
|
T_4.10 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%pushi/vec4 1, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
T_4.11 ;
|
|
%jmp T_4.5;
|
|
T_4.2 ;
|
|
%load/vec4 v0000021801c532d0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_4.12, 8;
|
|
%load/vec4 v0000021801c4f430_0;
|
|
%load/vec4 v0000021801c4fbb0_0;
|
|
%part/u 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%load/vec4 v0000021801c4fbb0_0;
|
|
%cmpi/e 7, 0, 4;
|
|
%jmp/0xz T_4.14, 4;
|
|
%pushi/vec4 3, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
%jmp T_4.15;
|
|
T_4.14 ;
|
|
%load/vec4 v0000021801c4fbb0_0;
|
|
%addi 1, 0, 4;
|
|
%assign/vec4 v0000021801c4fbb0_0, 0;
|
|
%pushi/vec4 2, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
T_4.15 ;
|
|
%jmp T_4.13;
|
|
T_4.12 ;
|
|
%load/vec4 v0000021801c4f430_0;
|
|
%load/vec4 v0000021801c4fbb0_0;
|
|
%part/u 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%pushi/vec4 2, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
T_4.13 ;
|
|
%jmp T_4.5;
|
|
T_4.3 ;
|
|
%load/vec4 v0000021801c532d0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_4.16, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%pushi/vec4 4, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
%jmp T_4.17;
|
|
T_4.16 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%pushi/vec4 3, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
T_4.17 ;
|
|
%jmp T_4.5;
|
|
T_4.4 ;
|
|
%load/vec4 v0000021801c532d0_0;
|
|
%flag_set/vec4 8;
|
|
%jmp/0xz T_4.18, 8;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%pushi/vec4 0, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
%jmp T_4.19;
|
|
T_4.18 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0000021801c52790_0, 0;
|
|
%pushi/vec4 4, 0, 5;
|
|
%assign/vec4 v0000021801c50290_0, 0;
|
|
T_4.19 ;
|
|
%jmp T_4.5;
|
|
T_4.5 ;
|
|
%pop/vec4 1;
|
|
%jmp T_4;
|
|
.thread T_4;
|
|
.scope S_0000021801ba6d00;
|
|
T_5 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c50790_0, 0, 32;
|
|
T_5.0 ;
|
|
%load/vec4 v0000021801c50790_0;
|
|
%cmpi/s 64, 0, 32;
|
|
%jmp/0xz T_5.1, 5;
|
|
%pushi/vec4 0, 0, 8;
|
|
%ix/getv/s 3, v0000021801c50790_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4f7f0, 0, 4;
|
|
%load/vec4 v0000021801c50790_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0000021801c50790_0, 0, 32;
|
|
%jmp T_5.0;
|
|
T_5.1 ;
|
|
%pushi/vec4 221, 0, 8;
|
|
%ix/load 3, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4f7f0, 0, 4;
|
|
%pushi/vec4 0, 0, 8;
|
|
%ix/load 3, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4f7f0, 0, 4;
|
|
%pushi/vec4 2, 0, 8;
|
|
%ix/load 3, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4f7f0, 0, 4;
|
|
%pushi/vec4 55, 0, 8;
|
|
%ix/load 3, 3, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4f7f0, 0, 4;
|
|
%pushi/vec4 3, 0, 8;
|
|
%ix/load 3, 4, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4f7f0, 0, 4;
|
|
%pushi/vec4 50, 0, 8;
|
|
%ix/load 3, 5, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4f7f0, 0, 4;
|
|
%pushi/vec4 2, 0, 8;
|
|
%ix/load 3, 6, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4f7f0, 0, 4;
|
|
%pushi/vec4 19, 0, 8;
|
|
%ix/load 3, 7, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4f7f0, 0, 4;
|
|
%pushi/vec4 0, 0, 32;
|
|
%assign/vec4 v0000021801c50970_0, 0;
|
|
%end;
|
|
.thread T_5;
|
|
.scope S_0000021801ba6d00;
|
|
T_6 ;
|
|
%wait E_0000021801be73e0;
|
|
%load/vec4 v0000021801c50830_0;
|
|
%cmpi/e 1, 0, 1;
|
|
%jmp/0xz T_6.0, 4;
|
|
%load/vec4 v0000021801c50dd0_0;
|
|
%parti/s 8, 0, 2;
|
|
%ix/getv 4, v0000021801c4fcf0_0;
|
|
%store/vec4a v0000021801c4f7f0, 4, 0;
|
|
%load/vec4 v0000021801c50dd0_0;
|
|
%parti/s 8, 8, 5;
|
|
%load/vec4 v0000021801c4fcf0_0;
|
|
%addi 1, 0, 32;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0000021801c4f7f0, 4, 0;
|
|
%load/vec4 v0000021801c50dd0_0;
|
|
%parti/s 8, 16, 6;
|
|
%load/vec4 v0000021801c4fcf0_0;
|
|
%addi 2, 0, 32;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0000021801c4f7f0, 4, 0;
|
|
%load/vec4 v0000021801c50dd0_0;
|
|
%parti/s 8, 24, 6;
|
|
%load/vec4 v0000021801c4fcf0_0;
|
|
%addi 3, 0, 32;
|
|
%ix/vec4 4;
|
|
%store/vec4a v0000021801c4f7f0, 4, 0;
|
|
T_6.0 ;
|
|
%jmp T_6;
|
|
.thread T_6;
|
|
.scope S_0000021801bc8750;
|
|
T_7 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4e8c0_0, 0, 32;
|
|
T_7.0 ;
|
|
%load/vec4 v0000021801c4e8c0_0;
|
|
%cmpi/s 32, 0, 32;
|
|
%jmp/0xz T_7.1, 5;
|
|
%pushi/vec4 0, 0, 32;
|
|
%ix/getv/s 3, v0000021801c4e8c0_0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4ee60, 0, 4;
|
|
%load/vec4 v0000021801c4e8c0_0;
|
|
%addi 1, 0, 32;
|
|
%store/vec4 v0000021801c4e8c0_0, 0, 32;
|
|
%jmp T_7.0;
|
|
T_7.1 ;
|
|
%pushi/vec4 0, 0, 32;
|
|
%ix/load 3, 0, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4ee60, 0, 4;
|
|
%pushi/vec4 0, 0, 32;
|
|
%ix/load 3, 1, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4ee60, 0, 4;
|
|
%pushi/vec4 0, 0, 32;
|
|
%ix/load 3, 2, 0;
|
|
%flag_set/imm 4, 0;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4ee60, 0, 4;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4eaa0_0, 0, 32;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0000021801c4ebe0_0, 0, 1;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4d9c0_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4db00_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4e5a0_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4d380_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4de20_0, 0, 32;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0000021801c4d920_0, 0, 1;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4e820_0, 0, 32;
|
|
%pushi/vec4 0, 0, 4;
|
|
%store/vec4 v0000021801c4e0a0_0, 0, 4;
|
|
%end;
|
|
.thread T_7;
|
|
.scope S_0000021801bc8750;
|
|
T_8 ;
|
|
%wait E_0000021801be73e0;
|
|
%load/vec4 v0000021801c4e0a0_0;
|
|
%dup/vec4;
|
|
%pushi/vec4 0, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_8.0, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 1, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_8.1, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 2, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_8.2, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 3, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_8.3, 6;
|
|
%dup/vec4;
|
|
%pushi/vec4 4, 0, 4;
|
|
%cmp/u;
|
|
%jmp/1 T_8.4, 6;
|
|
%jmp T_8.5;
|
|
T_8.0 ;
|
|
%pushi/vec4 1, 0, 1;
|
|
%assign/vec4 v0000021801c4df60_0, 0;
|
|
%load/vec4 v0000021801c4e3c0_0;
|
|
%parti/s 8, 24, 6;
|
|
%assign/vec4 v0000021801c4ed20_0, 0;
|
|
%ix/load 4, 4, 0;
|
|
%flag_set/imm 4, 0;
|
|
%load/vec4a v0000021801c4ee60, 4;
|
|
%assign/vec4 v0000021801be51d0_0, 0;
|
|
%load/vec4 v0000021801c4ef00_0;
|
|
%assign/vec4 v0000021801c4db00_0, 0;
|
|
%load/vec4 v0000021801c4d9c0_0;
|
|
%addi 4, 0, 32;
|
|
%assign/vec4 v0000021801c4d880_0, 0;
|
|
%pushi/vec4 1, 0, 4;
|
|
%assign/vec4 v0000021801c4e0a0_0, 0;
|
|
%jmp T_8.5;
|
|
T_8.1 ;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 7, 0, 2;
|
|
%store/vec4 v0000021801c4e460_0, 0, 7;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 5, 7, 4;
|
|
%store/vec4 v0000021801c4d6a0_0, 0, 5;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 3, 12, 5;
|
|
%store/vec4 v0000021801c4e280_0, 0, 3;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 5, 15, 5;
|
|
%assign/vec4 v0000021801c4e000_0, 0;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 5, 20, 6;
|
|
%assign/vec4 v0000021801c4d060_0, 0;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 7, 25, 6;
|
|
%store/vec4 v0000021801c4e320_0, 0, 7;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 12, 20, 6;
|
|
%assign/vec4 v0000021801c4d740_0, 0;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 7, 25, 6;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 5, 7, 4;
|
|
%concat/vec4; draw_concat_vec4
|
|
%assign/vec4 v0000021801c4d2e0_0, 0;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 7, 25, 6;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 5, 7, 4;
|
|
%concat/vec4; draw_concat_vec4
|
|
%pad/u 13;
|
|
%store/vec4 v0000021801c4e780_0, 0, 13;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 20, 12, 5;
|
|
%ix/load 4, 12, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4 v0000021801c4dce0_0, 4, 20;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 1, 31, 6;
|
|
%replicate 12;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 8, 12, 5;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 1, 20, 6;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 6, 25, 6;
|
|
%concat/vec4; draw_concat_vec4
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%parti/s 4, 21, 6;
|
|
%concat/vec4; draw_concat_vec4
|
|
%concati/vec4 0, 0, 1;
|
|
%pad/u 21;
|
|
%store/vec4 v0000021801c4ec80_0, 0, 21;
|
|
%pushi/vec4 2, 0, 4;
|
|
%assign/vec4 v0000021801c4e0a0_0, 0;
|
|
%jmp T_8.5;
|
|
T_8.2 ;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%pushi/vec4 28799, 0, 32;
|
|
%and;
|
|
%cmpi/e 8227, 0, 32;
|
|
%jmp/0xz T_8.6, 4;
|
|
%load/vec4 v0000021801c4edc0_0;
|
|
%load/vec4 v0000021801c4dba0_0;
|
|
%add;
|
|
%store/vec4 v0000021801c4e820_0, 0, 32;
|
|
T_8.6 ;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%pushi/vec4 28799, 0, 32;
|
|
%and;
|
|
%cmpi/e 8195, 0, 32;
|
|
%jmp/0xz T_8.8, 4;
|
|
%load/vec4 v0000021801c4edc0_0;
|
|
%load/vec4 v0000021801c4ea00_0;
|
|
%add;
|
|
%store/vec4 v0000021801c4e820_0, 0, 32;
|
|
T_8.8 ;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%pushi/vec4 127, 0, 32;
|
|
%and;
|
|
%cmpi/e 55, 0, 32;
|
|
%jmp/0xz T_8.10, 4;
|
|
%load/vec4 v0000021801c4dce0_0;
|
|
%parti/s 20, 12, 5;
|
|
%ix/load 4, 12, 0;
|
|
%flag_set/imm 4, 0;
|
|
%store/vec4 v0000021801c4eaa0_0, 4, 20;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0000021801c4ebe0_0, 0, 1;
|
|
T_8.10 ;
|
|
%load/vec4 v0000021801c4db00_0;
|
|
%pushi/vec4 28799, 0, 32;
|
|
%and;
|
|
%cmpi/e 19, 0, 32;
|
|
%jmp/0xz T_8.12, 4;
|
|
%load/vec4 v0000021801c4edc0_0;
|
|
%load/vec4 v0000021801c4ea00_0;
|
|
%add;
|
|
%store/vec4 v0000021801c4eaa0_0, 0, 32;
|
|
%pushi/vec4 1, 0, 1;
|
|
%store/vec4 v0000021801c4ebe0_0, 0, 1;
|
|
T_8.12 ;
|
|
%pushi/vec4 3, 0, 4;
|
|
%assign/vec4 v0000021801c4e0a0_0, 0;
|
|
%jmp T_8.5;
|
|
T_8.3 ;
|
|
%load/vec4 v0000021801c4e820_0;
|
|
%store/vec4 v0000021801c4d380_0, 0, 32;
|
|
%load/vec4 v0000021801c4e460_0;
|
|
%pad/u 32;
|
|
%pushi/vec4 8227, 0, 32;
|
|
%cmp/e;
|
|
%flag_get/vec4 4;
|
|
%store/vec4 v0000021801c4d920_0, 0, 1;
|
|
%load/vec4 v0000021801c4d100_0;
|
|
%store/vec4 v0000021801c4de20_0, 0, 32;
|
|
%pushi/vec4 4, 0, 4;
|
|
%assign/vec4 v0000021801c4e0a0_0, 0;
|
|
%jmp T_8.5;
|
|
T_8.4 ;
|
|
%load/vec4 v0000021801c4e460_0;
|
|
%pad/u 32;
|
|
%cmpi/e 8195, 0, 32;
|
|
%jmp/0xz T_8.14, 4;
|
|
%load/vec4 v0000021801c4e3c0_0;
|
|
%load/vec4 v0000021801c4d6a0_0;
|
|
%pad/u 7;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4ee60, 0, 4;
|
|
T_8.14 ;
|
|
%load/vec4 v0000021801c4ebe0_0;
|
|
%pad/u 32;
|
|
%cmpi/e 1, 0, 32;
|
|
%jmp/0xz T_8.16, 4;
|
|
%load/vec4 v0000021801c4eaa0_0;
|
|
%load/vec4 v0000021801c4d6a0_0;
|
|
%pad/u 7;
|
|
%ix/vec4 3;
|
|
%ix/load 4, 0, 0; Constant delay
|
|
%assign/vec4/a/d v0000021801c4ee60, 0, 4;
|
|
T_8.16 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0000021801c4ebe0_0, 0, 1;
|
|
%load/vec4 v0000021801c4d880_0;
|
|
%store/vec4 v0000021801c4d9c0_0, 0, 32;
|
|
%pushi/vec4 0, 0, 32;
|
|
%store/vec4 v0000021801c4e820_0, 0, 32;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0000021801c4d920_0, 0, 1;
|
|
%load/vec4 v0000021801c4d880_0;
|
|
%store/vec4 v0000021801c4e5a0_0, 0, 32;
|
|
%pushi/vec4 0, 0, 4;
|
|
%assign/vec4 v0000021801c4e0a0_0, 0;
|
|
%jmp T_8.5;
|
|
T_8.5 ;
|
|
%pop/vec4 1;
|
|
%jmp T_8;
|
|
.thread T_8;
|
|
.scope S_0000021801ba52c0;
|
|
T_9 ;
|
|
%pushi/vec4 0, 0, 1;
|
|
%store/vec4 v0000021801c51d90_0, 0, 1;
|
|
%end;
|
|
.thread T_9;
|
|
.scope S_0000021801ba52c0;
|
|
T_10 ;
|
|
%vpi_call 2 6 "$dumpfile", "tb_memory.vcd" {0 0 0};
|
|
%vpi_call 2 7 "$dumpvars", 32'sb00000000000000000000000000000011, S_0000021801ba52c0 {0 0 0};
|
|
%delay 10000, 0;
|
|
%vpi_call 2 9 "$finish" {0 0 0};
|
|
%end;
|
|
.thread T_10;
|
|
.scope S_0000021801ba52c0;
|
|
T_11 ;
|
|
%delay 1, 0;
|
|
%load/vec4 v0000021801c51d90_0;
|
|
%nor/r;
|
|
%store/vec4 v0000021801c51d90_0, 0, 1;
|
|
%jmp T_11;
|
|
.thread T_11;
|
|
# The file index is used to find the file name in the following table.
|
|
:file_names 7;
|
|
"N/A";
|
|
"<interactive>";
|
|
"uart_tb.v";
|
|
"top.v";
|
|
"core.v";
|
|
"memory.v";
|
|
"uart.v";
|