-- Setup Paths Table
+
- Setup Paths Table
diff --git a/impl/pnr/cpu_tr_content.html b/impl/pnr/cpu_tr_content.html
index 52e5ae2..0e79f76 100644
--- a/impl/pnr/cpu_tr_content.html
+++ b/impl/pnr/cpu_tr_content.html
@@ -50,7 +50,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Created Time |
-Thu May 18 14:32:04 2023
+ | Mon May 22 14:29:38 2023
|
@@ -71,11 +71,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Numbers of Paths Analyzed |
-1619 |
+397 |
Numbers of Endpoints Analyzed |
-1590 |
+418 |
Numbers of Falling Endpoints |
@@ -83,7 +83,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Numbers of Setup Violated Endpoints |
-1027 |
+0 |
Numbers of Hold Violated Endpoints |
@@ -129,8 +129,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
1 |
clock |
100.000(MHz) |
-68.477(MHz) |
-13 |
+128.136(MHz) |
+9 |
TOP |
@@ -145,8 +145,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
clock |
Setup |
--3052.220 |
-1027 |
+0.000 |
+0 |
clock |
@@ -171,280 +171,280 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Clock Skew |
Data Delay |
-
+
1 |
--4.604 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_15_G[7]_s0/CE |
+2.196 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_31_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.569 |
+7.769 |
-
+
2 |
--4.604 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_15_G[6]_s0/CE |
+2.518 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_26_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.569 |
+7.447 |
-
+
3 |
--4.604 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_15_G[5]_s0/CE |
+2.618 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_29_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.569 |
+7.347 |
-
+
4 |
--4.604 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_15_G[2]_s0/CE |
+2.751 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_12_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.569 |
+7.214 |
-
+
5 |
--4.604 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_15_G[1]_s0/CE |
+2.779 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_25_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.569 |
+7.186 |
-
+
6 |
--4.604 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_15_G[0]_s0/CE |
+2.789 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_16_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.569 |
+7.176 |
-
+
7 |
--4.537 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_24_G[2]_s0/CE |
+2.852 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_28_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.502 |
+7.113 |
-
+
8 |
--4.482 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_18_G[5]_s0/D |
+2.893 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_19_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.447 |
+7.072 |
-
+
9 |
--4.448 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_18_G[5]_s0/CE |
+2.902 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_24_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.413 |
+7.063 |
-
+
10 |
--4.448 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_18_G[1]_s0/CE |
+2.934 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_20_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.413 |
+7.031 |
-
+
11 |
--4.434 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_19_G[6]_s0/D |
+2.959 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_13_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.399 |
+7.006 |
-
+
12 |
--4.395 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_24_G[1]_s0/CE |
+3.005 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_18_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.360 |
+6.960 |
-
+
13 |
--4.315 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_30_G[1]_s0/CE |
+3.039 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_27_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.280 |
+6.926 |
-
+
14 |
--4.291 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_44_G[3]_s0/D |
+3.044 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_23_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.256 |
+6.921 |
-
+
15 |
--4.262 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_51_G[7]_s0/CE |
+3.061 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_17_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.227 |
+6.904 |
-
+
16 |
--4.262 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_51_G[3]_s0/CE |
+3.098 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_21_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.227 |
+6.867 |
-
+
17 |
--4.258 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_51_G[5]_s0/CE |
+3.190 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_30_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.223 |
+6.775 |
-
+
18 |
--4.254 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_22_G[0]_s0/D |
+3.218 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_15_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.219 |
+6.747 |
-
+
19 |
--4.249 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_40_G[7]_s0/D |
+3.306 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_22_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.214 |
+6.659 |
-
+
20 |
--4.226 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_13_G[5]_s0/CE |
+3.345 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_14_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.191 |
+6.620 |
-
+
21 |
--4.226 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_13_G[3]_s0/CE |
+3.370 |
+core0/rs1_3_s2/Q |
+core0/alu_out_3_s1/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.191 |
+6.595 |
-
+
22 |
--4.226 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_13_G[0]_s0/CE |
+3.374 |
+core0/register_register_0_0_s/DO[1] |
+core0/alu_out_5_s1/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.191 |
+6.591 |
-
+
23 |
--4.204 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_15_G[4]_s0/CE |
+3.390 |
+core0/register_register_0_0_s/DO[1] |
+core0/alu_out_2_s1/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.169 |
+6.575 |
-
+
24 |
--4.198 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_51_G[6]_s0/CE |
+3.491 |
+core0/register_register_0_0_s/DO[1] |
+core0/reg_wb_data_2_s0/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.163 |
+6.474 |
-
+
25 |
--4.185 |
-core0/reg_raddr_4_s0/Q |
-mem0/mem_mem_RAMREG_24_G[5]_s0/CE |
+3.496 |
+core0/register_register_0_0_s/DO[1] |
+core0/alu_out_4_s1/D |
clock:[R] |
clock:[R] |
10.000 |
0.000 |
-14.150 |
+6.469 |
@@ -463,9 +463,53 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
1 |
-0.346 |
-core0/rs2_4_s0/Q |
-core0/register_register_0_0_s/ADB[9] |
+0.199 |
+core0/reg_wb_data_30_s0/Q |
+core0/register_register_0_0_s/DI[30] |
+clock:[R] |
+clock:[R] |
+0.000 |
+0.000 |
+0.448 |
+
+
+2 |
+0.203 |
+core0/reg_wb_data_7_s0/Q |
+core0/register_register_0_0_s/DI[7] |
+clock:[R] |
+clock:[R] |
+0.000 |
+0.000 |
+0.452 |
+
+
+3 |
+0.203 |
+core0/reg_wb_data_6_s0/Q |
+core0/register_register_0_0_s/DI[6] |
+clock:[R] |
+clock:[R] |
+0.000 |
+0.000 |
+0.452 |
+
+
+4 |
+0.213 |
+core0/reg_wb_data_9_s0/Q |
+core0/register_register_0_0_s/DI[9] |
+clock:[R] |
+clock:[R] |
+0.000 |
+0.000 |
+0.462 |
+
+
+5 |
+0.215 |
+core0/reg_wb_data_31_s0/Q |
+core0/register_register_0_0_s/DI[31] |
clock:[R] |
clock:[R] |
0.000 |
@@ -473,268 +517,224 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.464 |
-2 |
-0.359 |
-core0/rd_0_s0/Q |
-core0/register_register_0_0_s/ADA[5] |
-clock:[R] |
-clock:[R] |
-0.000 |
-0.000 |
-0.477 |
-
-
-3 |
-0.425 |
-core0/alu_out_0_s1/Q |
-core0/alu_out_0_s1/D |
-clock:[R] |
-clock:[R] |
-0.000 |
-0.000 |
-0.436 |
-
-
-4 |
-0.425 |
-core0/alu_out_3_s1/Q |
-core0/alu_out_3_s1/D |
-clock:[R] |
-clock:[R] |
-0.000 |
-0.000 |
-0.436 |
-
-
-5 |
-0.425 |
-core0/alu_out_5_s1/Q |
-core0/alu_out_5_s1/D |
-clock:[R] |
-clock:[R] |
-0.000 |
-0.000 |
-0.436 |
-
-
6 |
-0.425 |
-core0/alu_out_6_s1/Q |
-core0/alu_out_6_s1/D |
+0.215 |
+core0/reg_wb_data_21_s0/Q |
+core0/register_register_0_0_s/DI[21] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.464 |
7 |
-0.425 |
-core0/alu_out_7_s1/Q |
-core0/alu_out_7_s1/D |
+0.215 |
+core0/reg_wb_data_20_s0/Q |
+core0/register_register_0_0_s/DI[20] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.464 |
8 |
-0.425 |
-core0/alu_out_9_s1/Q |
-core0/alu_out_9_s1/D |
+0.215 |
+core0/reg_wb_data_11_s0/Q |
+core0/register_register_0_0_s/DI[11] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.464 |
9 |
-0.425 |
-core0/alu_out_11_s1/Q |
-core0/alu_out_11_s1/D |
+0.215 |
+core0/reg_wb_data_10_s0/Q |
+core0/register_register_0_0_s/DI[10] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.464 |
10 |
-0.425 |
-core0/alu_out_12_s1/Q |
-core0/alu_out_12_s1/D |
+0.215 |
+core0/reg_wb_data_8_s0/Q |
+core0/register_register_0_0_s/DI[8] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.464 |
11 |
-0.425 |
-core0/alu_out_13_s1/Q |
-core0/alu_out_13_s1/D |
+0.215 |
+core0/reg_wb_data_5_s0/Q |
+core0/register_register_0_0_s/DI[5] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.464 |
12 |
-0.425 |
-core0/alu_out_14_s1/Q |
-core0/alu_out_14_s1/D |
+0.215 |
+core0/reg_wb_data_4_s0/Q |
+core0/register_register_0_0_s/DI[4] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.464 |
13 |
-0.425 |
-core0/alu_out_23_s1/Q |
-core0/alu_out_23_s1/D |
+0.227 |
+core0/reg_wb_data_29_s0/Q |
+core0/register_register_0_0_s/DI[29] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.476 |
14 |
-0.425 |
-core0/alu_out_25_s1/Q |
-core0/alu_out_25_s1/D |
+0.321 |
+core0/reg_wb_data_25_s0/Q |
+core0/register_register_0_0_s/DI[25] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.570 |
15 |
-0.425 |
-core0/alu_out_27_s1/Q |
-core0/alu_out_27_s1/D |
+0.321 |
+core0/reg_wb_data_24_s0/Q |
+core0/register_register_0_0_s/DI[24] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.570 |
16 |
-0.425 |
-uart0/led_flag_s1/Q |
-uart0/led_flag_s1/D |
+0.325 |
+core0/reg_wb_data_27_s0/Q |
+core0/register_register_0_0_s/DI[27] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.574 |
17 |
-0.425 |
-uart0/clock_count_2_s0/Q |
-uart0/clock_count_2_s0/D |
+0.337 |
+core0/reg_wb_data_17_s0/Q |
+core0/register_register_0_0_s/DI[17] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.586 |
18 |
-0.425 |
-uart0/clock_count_6_s0/Q |
-uart0/clock_count_6_s0/D |
+0.337 |
+core0/reg_wb_data_15_s0/Q |
+core0/register_register_0_0_s/DI[15] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.586 |
19 |
-0.425 |
-uart0/clock_count_8_s0/Q |
-uart0/clock_count_8_s0/D |
+0.337 |
+core0/reg_wb_data_14_s0/Q |
+core0/register_register_0_0_s/DI[14] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.586 |
20 |
-0.425 |
-uart0/clock_count_12_s0/Q |
-uart0/clock_count_12_s0/D |
+0.337 |
+core0/reg_wb_data_0_s0/Q |
+core0/register_register_0_0_s/DI[0] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.586 |
21 |
-0.425 |
-uart0/clock_count_14_s0/Q |
-uart0/clock_count_14_s0/D |
+0.353 |
+core0/reg_wb_data_23_s0/Q |
+core0/register_register_0_0_s/DI[23] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.602 |
22 |
-0.425 |
-uart0/clock_count_18_s0/Q |
-uart0/clock_count_18_s0/D |
+0.353 |
+core0/reg_wb_data_1_s0/Q |
+core0/register_register_0_0_s/DI[1] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.602 |
23 |
-0.425 |
-uart0/clock_count_20_s0/Q |
-uart0/clock_count_20_s0/D |
+0.364 |
+core0/reg_wb_data_19_s0/Q |
+core0/register_register_0_0_s/DI[19] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.613 |
24 |
-0.425 |
-uart0/clock_count_24_s0/Q |
-uart0/clock_count_24_s0/D |
+0.364 |
+core0/reg_wb_data_13_s0/Q |
+core0/register_register_0_0_s/DI[13] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.613 |
25 |
-0.425 |
-uart0/clock_count_26_s0/Q |
-uart0/clock_count_26_s0/D |
+0.364 |
+core0/reg_wb_data_3_s0/Q |
+core0/register_register_0_0_s/DI[3] |
clock:[R] |
clock:[R] |
0.000 |
0.000 |
-0.436 |
+0.613 |
@@ -807,7 +807,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
1.000 |
Low Pulse Width |
clock |
-mem0/mem_mem_RAMREG_0_G[4]_s0 |
+core0/reg_inst_28_s0 |
7 |
@@ -816,7 +816,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
1.000 |
Low Pulse Width |
clock |
-mem0/mem_mem_RAMREG_8_G[4]_s0 |
+core0/reg_wb_data_11_s0 |
8 |
@@ -825,7 +825,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
1.000 |
Low Pulse Width |
clock |
-mem0/mem_mem_RAMREG_24_G[4]_s0 |
+core0/reg_wb_data_12_s0 |
9 |
@@ -834,7 +834,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
1.000 |
Low Pulse Width |
clock |
-mem0/mem_mem_RAMREG_56_G[4]_s0 |
+core0/reg_inst_29_s0 |
10 |
@@ -843,7 +843,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
1.000 |
Low Pulse Width |
clock |
-mem0/mem_mem_RAMREG_56_G[3]_s0 |
+core0/reg_wb_data_13_s0 |
@@ -854,11 +854,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.604 |
+2.196 |
Data Arrival Time |
-15.494 |
+8.695 |
Data Required Time |
@@ -866,11 +866,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_15_G[7]_s0 |
+core0/reg_wb_data_31_s0 |
Launch Clk |
@@ -924,7 +924,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -933,549 +933,621 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
+5.870 |
+0.570 |
+tINS |
+FR |
+1 |
+R12C37[0][B] |
+core0/n173_s/COUT |
+
+
+5.870 |
+0.000 |
+tNET |
+RR |
+2 |
+R12C37[1][A] |
+core0/n172_s/CIN |
+
+
+5.905 |
+0.035 |
+tINS |
+RF |
+1 |
+R12C37[1][A] |
+core0/n172_s/COUT |
+
+
+5.905 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[1][B] |
+core0/n171_s/CIN |
+
+
+5.940 |
+0.035 |
tINS |
FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
+1 |
+R12C37[1][B] |
+core0/n171_s/COUT |
-5.606 |
-0.573 |
+5.940 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[2][A] |
+core0/n170_s/CIN |
+
+
+5.975 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C37[2][A] |
+core0/n170_s/COUT |
+
+
+5.975 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[2][B] |
+core0/n169_s/CIN |
+
+
+6.011 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C37[2][B] |
+core0/n169_s/COUT |
+
+
+6.011 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[0][A] |
+core0/n168_s/CIN |
+
+
+6.046 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[0][A] |
+core0/n168_s/COUT |
+
+
+6.046 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[0][B] |
+core0/n167_s/CIN |
+
+
+6.081 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[0][B] |
+core0/n167_s/COUT |
+
+
+6.081 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
+
+
+6.116 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][A] |
+core0/n166_s/COUT |
+
+
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.292 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/COUT |
+
+
+6.292 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][A] |
+core0/n160_s/CIN |
+
+
+6.327 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][A] |
+core0/n160_s/COUT |
+
+
+6.327 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][B] |
+core0/n159_s/CIN |
+
+
+6.363 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][B] |
+core0/n159_s/COUT |
+
+
+6.363 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][A] |
+core0/n158_s/CIN |
+
+
+6.398 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][A] |
+core0/n158_s/COUT |
+
+
+6.398 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][B] |
+core0/n157_s/CIN |
+
+
+6.433 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][B] |
+core0/n157_s/COUT |
+
+
+6.433 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][A] |
+core0/n156_s/CIN |
+
+
+6.468 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][A] |
+core0/n156_s/COUT |
+
+
+6.468 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][B] |
+core0/n155_s/CIN |
+
+
+6.503 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][B] |
+core0/n155_s/COUT |
+
+
+6.503 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][A] |
+core0/n154_s/CIN |
+
+
+6.539 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][A] |
+core0/n154_s/COUT |
+
+
+6.539 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][B] |
+core0/n153_s/CIN |
+
+
+6.574 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
+
+
+6.574 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
+
+
+6.609 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][A] |
+core0/n152_s/COUT |
+
+
+6.609 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][B] |
+core0/n151_s/CIN |
+
+
+6.644 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][B] |
+core0/n151_s/COUT |
+
+
+6.644 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][A] |
+core0/n150_s/CIN |
+
+
+6.679 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][A] |
+core0/n150_s/COUT |
+
+
+6.679 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][B] |
+core0/n149_s/CIN |
+
+
+6.715 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][B] |
+core0/n149_s/COUT |
+
+
+6.715 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][A] |
+core0/n148_s/CIN |
+
+
+6.750 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[1][A] |
+core0/n148_s/COUT |
+
+
+6.750 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][B] |
+core0/n147_s/CIN |
+
+
+6.785 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[1][B] |
+core0/n147_s/COUT |
+
+
+6.785 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[2][A] |
+core0/n146_s/CIN |
+
+
+6.820 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[2][A] |
+core0/n146_s/COUT |
+
+
+6.820 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[2][B] |
+core0/n145_s/CIN |
+
+
+6.855 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[2][B] |
+core0/n145_s/COUT |
+
+
+6.855 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C42[0][A] |
+core0/n144_s/CIN |
+
+
+6.891 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C42[0][A] |
+core0/n144_s/COUT |
+
+
+7.774 |
+0.883 |
tNET |
FF |
1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
+R11C42[1][A] |
+core0/n213_s5/I2 |
-6.155 |
+8.323 |
0.549 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R11C42[1][A] |
+core0/n213_s5/F |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
-0.000 |
-tNET |
-RR |
-2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
-
-
-7.681 |
-0.035 |
-tINS |
-RF |
-1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
-
-
-7.681 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
-
-
-7.716 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
-
-
-7.716 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
-
-
-7.751 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
-
-
-7.751 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
-
-
-7.786 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
-
-
-7.786 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
-
-
-7.822 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
-
-
-7.822 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
-
-
-7.857 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
-
-
-7.857 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
-
-
-7.892 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
-
-
-7.892 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
-
-
-7.927 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
-
-
-7.927 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
-
-
-7.962 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
-
-
-7.962 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
-
-
-7.998 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
-
-
-7.998 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
-
-
-8.033 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
-
-
-8.033 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
-
-
-8.068 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
-
-
-8.068 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
-
-
-8.103 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
-
-
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
-tNET |
-FF |
-1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
-
-
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-12.531 |
-2.002 |
-tNET |
-FF |
-1 |
-R38C35[0][B] |
-mem0/mem_s5264/I0 |
-
-
-13.086 |
-0.555 |
-tINS |
-FF |
-9 |
-R38C35[0][B] |
-mem0/mem_s5264/F |
-
-
-13.623 |
-0.537 |
-tNET |
-FF |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/I3 |
-
-
-14.193 |
-0.570 |
-tINS |
-FR |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/F |
-
-
-14.195 |
+8.324 |
0.001 |
tNET |
RR |
1 |
-R36C39[3][A] |
-mem0/mem_s4983/I3 |
+R11C42[0][A] |
+core0/n213_s4/I0 |
-14.765 |
-0.570 |
+8.695 |
+0.371 |
tINS |
-RR |
-8 |
-R36C39[3][A] |
-mem0/mem_s4983/F |
+RF |
+1 |
+R11C42[0][A] |
+core0/n213_s4/F |
-15.494 |
-0.730 |
+8.695 |
+0.000 |
tNET |
-RR |
+FF |
1 |
-R34C36[1][B] |
-mem0/mem_mem_RAMREG_15_G[7]_s0/CE |
+R11C42[0][A] |
+core0/reg_wb_data_31_s0/D |
Data Required Path:
@@ -1521,7 +1593,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -1531,8 +1603,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R34C36[1][B] |
-mem0/mem_mem_RAMREG_15_G[7]_s0/CLK |
+R11C42[0][A] |
+core0/reg_wb_data_31_s0/CLK |
10.891 |
@@ -1540,8 +1612,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R34C36[1][B] |
-mem0/mem_mem_RAMREG_15_G[7]_s0 |
+R11C42[0][A] |
+core0/reg_wb_data_31_s0 |
Path Statistics:
@@ -1556,7 +1628,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+9 |
Arrival Clock Path Delay |
@@ -1564,7 +1636,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592% |
+cell: 3.066, 39.461%; route: 2.443, 31.450%; tC2Q: 2.260, 29.089% |
Required Clock Path Delay |
@@ -1576,11 +1648,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.604 |
+2.518 |
Data Arrival Time |
-15.494 |
+8.373 |
Data Required Time |
@@ -1588,11 +1660,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_15_G[6]_s0 |
+core0/reg_wb_data_26_s0 |
Launch Clk |
@@ -1646,7 +1718,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -1655,549 +1727,531 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
+5.870 |
+0.570 |
+tINS |
+FR |
+1 |
+R12C37[0][B] |
+core0/n173_s/COUT |
+
+
+5.870 |
+0.000 |
+tNET |
+RR |
+2 |
+R12C37[1][A] |
+core0/n172_s/CIN |
+
+
+5.905 |
+0.035 |
+tINS |
+RF |
+1 |
+R12C37[1][A] |
+core0/n172_s/COUT |
+
+
+5.905 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[1][B] |
+core0/n171_s/CIN |
+
+
+5.940 |
+0.035 |
tINS |
FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
+1 |
+R12C37[1][B] |
+core0/n171_s/COUT |
-5.606 |
-0.573 |
+5.940 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[2][A] |
+core0/n170_s/CIN |
+
+
+5.975 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C37[2][A] |
+core0/n170_s/COUT |
+
+
+5.975 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[2][B] |
+core0/n169_s/CIN |
+
+
+6.011 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C37[2][B] |
+core0/n169_s/COUT |
+
+
+6.011 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[0][A] |
+core0/n168_s/CIN |
+
+
+6.046 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[0][A] |
+core0/n168_s/COUT |
+
+
+6.046 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[0][B] |
+core0/n167_s/CIN |
+
+
+6.081 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[0][B] |
+core0/n167_s/COUT |
+
+
+6.081 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
+
+
+6.116 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][A] |
+core0/n166_s/COUT |
+
+
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.292 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/COUT |
+
+
+6.292 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][A] |
+core0/n160_s/CIN |
+
+
+6.327 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][A] |
+core0/n160_s/COUT |
+
+
+6.327 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][B] |
+core0/n159_s/CIN |
+
+
+6.363 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][B] |
+core0/n159_s/COUT |
+
+
+6.363 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][A] |
+core0/n158_s/CIN |
+
+
+6.398 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][A] |
+core0/n158_s/COUT |
+
+
+6.398 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][B] |
+core0/n157_s/CIN |
+
+
+6.433 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][B] |
+core0/n157_s/COUT |
+
+
+6.433 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][A] |
+core0/n156_s/CIN |
+
+
+6.468 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][A] |
+core0/n156_s/COUT |
+
+
+6.468 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][B] |
+core0/n155_s/CIN |
+
+
+6.503 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][B] |
+core0/n155_s/COUT |
+
+
+6.503 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][A] |
+core0/n154_s/CIN |
+
+
+6.539 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][A] |
+core0/n154_s/COUT |
+
+
+6.539 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][B] |
+core0/n153_s/CIN |
+
+
+6.574 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
+
+
+6.574 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
+
+
+6.609 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][A] |
+core0/n152_s/COUT |
+
+
+6.609 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][B] |
+core0/n151_s/CIN |
+
+
+6.644 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][B] |
+core0/n151_s/COUT |
+
+
+6.644 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][A] |
+core0/n150_s/CIN |
+
+
+6.679 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][A] |
+core0/n150_s/COUT |
+
+
+6.679 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][B] |
+core0/n149_s/CIN |
+
+
+6.715 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][B] |
+core0/n149_s/COUT |
+
+
+6.715 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][A] |
+core0/n148_s/CIN |
+
+
+7.185 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C41[1][A] |
+core0/n148_s/SUM |
+
+
+7.824 |
+0.640 |
tNET |
FF |
1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
+R14C42[0][A] |
+core0/n218_s0/I0 |
-6.155 |
+8.373 |
0.549 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R14C42[0][A] |
+core0/n218_s0/F |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+8.373 |
0.000 |
tNET |
RR |
-2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
-
-
-7.681 |
-0.035 |
-tINS |
-RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
-
-
-7.681 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
-
-
-7.716 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
-
-
-7.716 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
-
-
-7.751 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
-
-
-7.751 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
-
-
-7.786 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
-
-
-7.786 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
-
-
-7.822 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
-
-
-7.822 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
-
-
-7.857 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
-
-
-7.857 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
-
-
-7.892 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
-
-
-7.892 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
-
-
-7.927 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
-
-
-7.927 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
-
-
-7.962 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
-
-
-7.962 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
-
-
-7.998 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
-
-
-7.998 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
-
-
-8.033 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
-
-
-8.033 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
-
-
-8.068 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
-
-
-8.068 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
-
-
-8.103 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
-
-
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
-tNET |
-FF |
-1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
-
-
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-12.531 |
-2.002 |
-tNET |
-FF |
-1 |
-R38C35[0][B] |
-mem0/mem_s5264/I0 |
-
-
-13.086 |
-0.555 |
-tINS |
-FF |
-9 |
-R38C35[0][B] |
-mem0/mem_s5264/F |
-
-
-13.623 |
-0.537 |
-tNET |
-FF |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/I3 |
-
-
-14.193 |
-0.570 |
-tINS |
-FR |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/F |
-
-
-14.195 |
-0.001 |
-tNET |
-RR |
-1 |
-R36C39[3][A] |
-mem0/mem_s4983/I3 |
-
-
-14.765 |
-0.570 |
-tINS |
-RR |
-8 |
-R36C39[3][A] |
-mem0/mem_s4983/F |
-
-
-15.494 |
-0.730 |
-tNET |
-RR |
-1 |
-R34C35[0][B] |
-mem0/mem_mem_RAMREG_15_G[6]_s0/CE |
+R14C42[0][A] |
+core0/reg_wb_data_26_s0/D |
Data Required Path:
@@ -2243,7 +2297,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -2253,8 +2307,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R34C35[0][B] |
-mem0/mem_mem_RAMREG_15_G[6]_s0/CLK |
+R14C42[0][A] |
+core0/reg_wb_data_26_s0/CLK |
10.891 |
@@ -2262,8 +2316,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R34C35[0][B] |
-mem0/mem_mem_RAMREG_15_G[6]_s0 |
+R14C42[0][A] |
+core0/reg_wb_data_26_s0 |
Path Statistics:
@@ -2278,7 +2332,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+7 |
Arrival Clock Path Delay |
@@ -2286,7 +2340,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592% |
+cell: 2.989, 40.132%; route: 2.199, 29.522%; tC2Q: 2.260, 30.346% |
Required Clock Path Delay |
@@ -2298,11 +2352,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.604 |
+2.618 |
Data Arrival Time |
-15.494 |
+8.273 |
Data Required Time |
@@ -2310,11 +2364,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_15_G[5]_s0 |
+core0/reg_wb_data_29_s0 |
Launch Clk |
@@ -2368,7 +2422,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -2377,549 +2431,585 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-7.786 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-7.822 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-7.822 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-7.857 |
+6.081 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
+R12C38[0][B] |
+core0/n167_s/COUT |
-7.857 |
+6.081 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
+R12C38[1][A] |
+core0/n166_s/CIN |
-7.892 |
+6.116 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
+R12C38[1][A] |
+core0/n166_s/COUT |
-7.892 |
+6.116 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
+R12C38[1][B] |
+core0/n165_s/CIN |
-7.927 |
+6.151 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
+R12C38[1][B] |
+core0/n165_s/COUT |
-7.927 |
+6.151 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
+R12C38[2][A] |
+core0/n164_s/CIN |
-7.962 |
+6.187 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
+R12C38[2][A] |
+core0/n164_s/COUT |
-7.962 |
+6.187 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
+R12C38[2][B] |
+core0/n163_s/CIN |
-7.998 |
+6.222 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
+R12C38[2][B] |
+core0/n163_s/COUT |
-7.998 |
+6.222 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
+R12C39[0][A] |
+core0/n162_s/CIN |
-8.033 |
+6.257 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
+R12C39[0][A] |
+core0/n162_s/COUT |
-8.033 |
+6.257 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
+R12C39[0][B] |
+core0/n161_s/CIN |
-8.068 |
+6.292 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
+R12C39[0][B] |
+core0/n161_s/COUT |
-8.068 |
+6.292 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
+R12C39[1][A] |
+core0/n160_s/CIN |
-8.103 |
+6.327 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
+R12C39[1][A] |
+core0/n160_s/COUT |
-8.103 |
+6.327 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
+R12C39[1][B] |
+core0/n159_s/CIN |
-8.138 |
+6.363 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
+R12C39[1][B] |
+core0/n159_s/COUT |
-8.138 |
+6.363 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
+R12C39[2][A] |
+core0/n158_s/CIN |
-8.174 |
+6.398 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
+R12C39[2][A] |
+core0/n158_s/COUT |
-8.174 |
+6.398 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
+R12C39[2][B] |
+core0/n157_s/CIN |
-8.209 |
+6.433 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
+R12C39[2][B] |
+core0/n157_s/COUT |
-8.209 |
+6.433 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
+R12C40[0][A] |
+core0/n156_s/CIN |
-8.244 |
+6.468 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
+R12C40[0][A] |
+core0/n156_s/COUT |
-8.244 |
+6.468 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
+R12C40[0][B] |
+core0/n155_s/CIN |
-8.279 |
+6.503 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
+R12C40[0][B] |
+core0/n155_s/COUT |
-8.279 |
+6.503 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
+R12C40[1][A] |
+core0/n154_s/CIN |
-8.314 |
+6.539 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
+R12C40[1][A] |
+core0/n154_s/COUT |
-8.314 |
+6.539 |
0.000 |
tNET |
FF |
2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
+R12C40[1][B] |
+core0/n153_s/CIN |
-8.350 |
+6.574 |
0.035 |
tINS |
FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
-10.077 |
-1.727 |
+6.574 |
+0.000 |
tNET |
FF |
-1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
-10.530 |
-0.453 |
+6.609 |
+0.035 |
tINS |
FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
+1 |
+R12C40[2][A] |
+core0/n152_s/COUT |
-12.531 |
-2.002 |
+6.609 |
+0.000 |
tNET |
FF |
-1 |
-R38C35[0][B] |
-mem0/mem_s5264/I0 |
+2 |
+R12C40[2][B] |
+core0/n151_s/CIN |
-13.086 |
-0.555 |
+6.644 |
+0.035 |
tINS |
FF |
-9 |
-R38C35[0][B] |
-mem0/mem_s5264/F |
+1 |
+R12C40[2][B] |
+core0/n151_s/COUT |
-13.623 |
-0.537 |
+6.644 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][A] |
+core0/n150_s/CIN |
+
+
+6.679 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][A] |
+core0/n150_s/COUT |
+
+
+6.679 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][B] |
+core0/n149_s/CIN |
+
+
+6.715 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][B] |
+core0/n149_s/COUT |
+
+
+6.715 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][A] |
+core0/n148_s/CIN |
+
+
+6.750 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[1][A] |
+core0/n148_s/COUT |
+
+
+6.750 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][B] |
+core0/n147_s/CIN |
+
+
+6.785 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[1][B] |
+core0/n147_s/COUT |
+
+
+6.785 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[2][A] |
+core0/n146_s/CIN |
+
+
+6.820 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[2][A] |
+core0/n146_s/COUT |
+
+
+6.820 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[2][B] |
+core0/n145_s/CIN |
+
+
+7.290 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C41[2][B] |
+core0/n145_s/SUM |
+
+
+7.703 |
+0.413 |
tNET |
FF |
1 |
-R36C39[0][B] |
-mem0/mem_s5923/I3 |
+R14C42[0][B] |
+core0/n215_s0/I0 |
-14.193 |
+8.273 |
0.570 |
tINS |
FR |
1 |
-R36C39[0][B] |
-mem0/mem_s5923/F |
+R14C42[0][B] |
+core0/n215_s0/F |
-14.195 |
-0.001 |
+8.273 |
+0.000 |
tNET |
RR |
1 |
-R36C39[3][A] |
-mem0/mem_s4983/I3 |
-
-
-14.765 |
-0.570 |
-tINS |
-RR |
-8 |
-R36C39[3][A] |
-mem0/mem_s4983/F |
-
-
-15.494 |
-0.730 |
-tNET |
-RR |
-1 |
-R34C35[0][A] |
-mem0/mem_mem_RAMREG_15_G[5]_s0/CE |
+R14C42[0][B] |
+core0/reg_wb_data_29_s0/D |
Data Required Path:
@@ -2965,7 +3055,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -2975,8 +3065,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R34C35[0][A] |
-mem0/mem_mem_RAMREG_15_G[5]_s0/CLK |
+R14C42[0][B] |
+core0/reg_wb_data_29_s0/CLK |
10.891 |
@@ -2984,8 +3074,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R34C35[0][A] |
-mem0/mem_mem_RAMREG_15_G[5]_s0 |
+R14C42[0][B] |
+core0/reg_wb_data_29_s0 |
Path Statistics:
@@ -3000,7 +3090,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+8 |
Arrival Clock Path Delay |
@@ -3008,7 +3098,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592% |
+cell: 3.115, 42.401%; route: 1.972, 26.840%; tC2Q: 2.260, 30.759% |
Required Clock Path Delay |
@@ -3020,11 +3110,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.604 |
+2.751 |
Data Arrival Time |
-15.494 |
+8.139 |
Data Required Time |
@@ -3032,11 +3122,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_15_G[2]_s0 |
+core0/reg_wb_data_12_s0 |
Launch Clk |
@@ -3090,7 +3180,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -3099,549 +3189,279 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
+5.870 |
+0.570 |
+tINS |
+FR |
+1 |
+R12C37[0][B] |
+core0/n173_s/COUT |
+
+
+5.870 |
+0.000 |
+tNET |
+RR |
+2 |
+R12C37[1][A] |
+core0/n172_s/CIN |
+
+
+5.905 |
+0.035 |
+tINS |
+RF |
+1 |
+R12C37[1][A] |
+core0/n172_s/COUT |
+
+
+5.905 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[1][B] |
+core0/n171_s/CIN |
+
+
+5.940 |
+0.035 |
tINS |
FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
+1 |
+R12C37[1][B] |
+core0/n171_s/COUT |
-5.606 |
-0.573 |
+5.940 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[2][A] |
+core0/n170_s/CIN |
+
+
+5.975 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C37[2][A] |
+core0/n170_s/COUT |
+
+
+5.975 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[2][B] |
+core0/n169_s/CIN |
+
+
+6.011 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C37[2][B] |
+core0/n169_s/COUT |
+
+
+6.011 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[0][A] |
+core0/n168_s/CIN |
+
+
+6.046 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[0][A] |
+core0/n168_s/COUT |
+
+
+6.046 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[0][B] |
+core0/n167_s/CIN |
+
+
+6.081 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[0][B] |
+core0/n167_s/COUT |
+
+
+6.081 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
+
+
+6.116 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][A] |
+core0/n166_s/COUT |
+
+
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.692 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/SUM |
+
+
+7.590 |
+0.899 |
tNET |
FF |
1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
+R15C42[2][B] |
+core0/n232_s0/I0 |
-6.155 |
+8.139 |
0.549 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R15C42[2][B] |
+core0/n232_s0/F |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+8.139 |
0.000 |
tNET |
RR |
-2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
-
-
-7.681 |
-0.035 |
-tINS |
-RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
-
-
-7.681 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
-
-
-7.716 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
-
-
-7.716 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
-
-
-7.751 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
-
-
-7.751 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
-
-
-7.786 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
-
-
-7.786 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
-
-
-7.822 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
-
-
-7.822 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
-
-
-7.857 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
-
-
-7.857 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
-
-
-7.892 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
-
-
-7.892 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
-
-
-7.927 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
-
-
-7.927 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
-
-
-7.962 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
-
-
-7.962 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
-
-
-7.998 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
-
-
-7.998 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
-
-
-8.033 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
-
-
-8.033 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
-
-
-8.068 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
-
-
-8.068 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
-
-
-8.103 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
-
-
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
-tNET |
-FF |
-1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
-
-
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-12.531 |
-2.002 |
-tNET |
-FF |
-1 |
-R38C35[0][B] |
-mem0/mem_s5264/I0 |
-
-
-13.086 |
-0.555 |
-tINS |
-FF |
-9 |
-R38C35[0][B] |
-mem0/mem_s5264/F |
-
-
-13.623 |
-0.537 |
-tNET |
-FF |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/I3 |
-
-
-14.193 |
-0.570 |
-tINS |
-FR |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/F |
-
-
-14.195 |
-0.001 |
-tNET |
-RR |
-1 |
-R36C39[3][A] |
-mem0/mem_s4983/I3 |
-
-
-14.765 |
-0.570 |
-tINS |
-RR |
-8 |
-R36C39[3][A] |
-mem0/mem_s4983/F |
-
-
-15.494 |
-0.730 |
-tNET |
-RR |
-1 |
-R34C36[0][B] |
-mem0/mem_mem_RAMREG_15_G[2]_s0/CE |
+R15C42[2][B] |
+core0/reg_wb_data_12_s0/D |
Data Required Path:
@@ -3687,7 +3507,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -3697,8 +3517,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R34C36[0][B] |
-mem0/mem_mem_RAMREG_15_G[2]_s0/CLK |
+R15C42[2][B] |
+core0/reg_wb_data_12_s0/CLK |
10.891 |
@@ -3706,8 +3526,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R34C36[0][B] |
-mem0/mem_mem_RAMREG_15_G[2]_s0 |
+R15C42[2][B] |
+core0/reg_wb_data_12_s0 |
Path Statistics:
@@ -3722,7 +3542,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+6 |
Arrival Clock Path Delay |
@@ -3730,7 +3550,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592% |
+cell: 2.496, 34.602%; route: 2.458, 34.068%; tC2Q: 2.260, 31.330% |
Required Clock Path Delay |
@@ -3742,11 +3562,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.604 |
+2.779 |
Data Arrival Time |
-15.494 |
+8.112 |
Data Required Time |
@@ -3754,11 +3574,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_15_G[1]_s0 |
+core0/reg_wb_data_25_s0 |
Launch Clk |
@@ -3812,7 +3632,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -3821,549 +3641,513 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
+5.870 |
+0.570 |
+tINS |
+FR |
+1 |
+R12C37[0][B] |
+core0/n173_s/COUT |
+
+
+5.870 |
+0.000 |
+tNET |
+RR |
+2 |
+R12C37[1][A] |
+core0/n172_s/CIN |
+
+
+5.905 |
+0.035 |
+tINS |
+RF |
+1 |
+R12C37[1][A] |
+core0/n172_s/COUT |
+
+
+5.905 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[1][B] |
+core0/n171_s/CIN |
+
+
+5.940 |
+0.035 |
tINS |
FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
+1 |
+R12C37[1][B] |
+core0/n171_s/COUT |
-5.606 |
-0.573 |
+5.940 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[2][A] |
+core0/n170_s/CIN |
+
+
+5.975 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C37[2][A] |
+core0/n170_s/COUT |
+
+
+5.975 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C37[2][B] |
+core0/n169_s/CIN |
+
+
+6.011 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C37[2][B] |
+core0/n169_s/COUT |
+
+
+6.011 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[0][A] |
+core0/n168_s/CIN |
+
+
+6.046 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[0][A] |
+core0/n168_s/COUT |
+
+
+6.046 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[0][B] |
+core0/n167_s/CIN |
+
+
+6.081 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[0][B] |
+core0/n167_s/COUT |
+
+
+6.081 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
+
+
+6.116 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][A] |
+core0/n166_s/COUT |
+
+
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.292 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/COUT |
+
+
+6.292 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][A] |
+core0/n160_s/CIN |
+
+
+6.327 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][A] |
+core0/n160_s/COUT |
+
+
+6.327 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][B] |
+core0/n159_s/CIN |
+
+
+6.363 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][B] |
+core0/n159_s/COUT |
+
+
+6.363 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][A] |
+core0/n158_s/CIN |
+
+
+6.398 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][A] |
+core0/n158_s/COUT |
+
+
+6.398 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][B] |
+core0/n157_s/CIN |
+
+
+6.433 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][B] |
+core0/n157_s/COUT |
+
+
+6.433 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][A] |
+core0/n156_s/CIN |
+
+
+6.468 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][A] |
+core0/n156_s/COUT |
+
+
+6.468 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][B] |
+core0/n155_s/CIN |
+
+
+6.503 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][B] |
+core0/n155_s/COUT |
+
+
+6.503 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][A] |
+core0/n154_s/CIN |
+
+
+6.539 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][A] |
+core0/n154_s/COUT |
+
+
+6.539 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][B] |
+core0/n153_s/CIN |
+
+
+6.574 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
+
+
+6.574 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
+
+
+6.609 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][A] |
+core0/n152_s/COUT |
+
+
+6.609 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][B] |
+core0/n151_s/CIN |
+
+
+6.644 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][B] |
+core0/n151_s/COUT |
+
+
+6.644 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][A] |
+core0/n150_s/CIN |
+
+
+6.679 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][A] |
+core0/n150_s/COUT |
+
+
+6.679 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][B] |
+core0/n149_s/CIN |
+
+
+7.149 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C41[0][B] |
+core0/n149_s/SUM |
+
+
+7.563 |
+0.413 |
tNET |
FF |
1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
+R13C42[0][A] |
+core0/n219_s0/I0 |
-6.155 |
+8.112 |
0.549 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R13C42[0][A] |
+core0/n219_s0/F |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+8.112 |
0.000 |
tNET |
RR |
-2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
-
-
-7.681 |
-0.035 |
-tINS |
-RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
-
-
-7.681 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
-
-
-7.716 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
-
-
-7.716 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
-
-
-7.751 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
-
-
-7.751 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
-
-
-7.786 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
-
-
-7.786 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
-
-
-7.822 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
-
-
-7.822 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
-
-
-7.857 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
-
-
-7.857 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
-
-
-7.892 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
-
-
-7.892 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
-
-
-7.927 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
-
-
-7.927 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
-
-
-7.962 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
-
-
-7.962 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
-
-
-7.998 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
-
-
-7.998 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
-
-
-8.033 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
-
-
-8.033 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
-
-
-8.068 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
-
-
-8.068 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
-
-
-8.103 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
-
-
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
-tNET |
-FF |
-1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
-
-
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-12.531 |
-2.002 |
-tNET |
-FF |
-1 |
-R38C35[0][B] |
-mem0/mem_s5264/I0 |
-
-
-13.086 |
-0.555 |
-tINS |
-FF |
-9 |
-R38C35[0][B] |
-mem0/mem_s5264/F |
-
-
-13.623 |
-0.537 |
-tNET |
-FF |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/I3 |
-
-
-14.193 |
-0.570 |
-tINS |
-FR |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/F |
-
-
-14.195 |
-0.001 |
-tNET |
-RR |
-1 |
-R36C39[3][A] |
-mem0/mem_s4983/I3 |
-
-
-14.765 |
-0.570 |
-tINS |
-RR |
-8 |
-R36C39[3][A] |
-mem0/mem_s4983/F |
-
-
-15.494 |
-0.730 |
-tNET |
-RR |
-1 |
-R34C36[0][A] |
-mem0/mem_mem_RAMREG_15_G[1]_s0/CE |
+R13C42[0][A] |
+core0/reg_wb_data_25_s0/D |
Data Required Path:
@@ -4409,7 +4193,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -4419,8 +4203,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R34C36[0][A] |
-mem0/mem_mem_RAMREG_15_G[1]_s0/CLK |
+R13C42[0][A] |
+core0/reg_wb_data_25_s0/CLK |
10.891 |
@@ -4428,8 +4212,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R34C36[0][A] |
-mem0/mem_mem_RAMREG_15_G[1]_s0 |
+R13C42[0][A] |
+core0/reg_wb_data_25_s0 |
Path Statistics:
@@ -4444,7 +4228,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+7 |
Arrival Clock Path Delay |
@@ -4452,7 +4236,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592% |
+cell: 2.954, 41.104%; route: 1.972, 27.444%; tC2Q: 2.260, 31.452% |
Required Clock Path Delay |
@@ -4464,11 +4248,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.604 |
+2.789 |
Data Arrival Time |
-15.494 |
+8.102 |
Data Required Time |
@@ -4476,11 +4260,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_15_G[0]_s0 |
+core0/reg_wb_data_16_s0 |
Launch Clk |
@@ -4534,7 +4318,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -4543,549 +4327,351 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-7.786 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-7.822 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-7.822 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-7.857 |
+6.081 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
+R12C38[0][B] |
+core0/n167_s/COUT |
-7.857 |
+6.081 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
+R12C38[1][A] |
+core0/n166_s/CIN |
-7.892 |
+6.116 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
+R12C38[1][A] |
+core0/n166_s/COUT |
-7.892 |
+6.116 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
+R12C38[1][B] |
+core0/n165_s/CIN |
-7.927 |
+6.151 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
+R12C38[1][B] |
+core0/n165_s/COUT |
-7.927 |
+6.151 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
+R12C38[2][A] |
+core0/n164_s/CIN |
-7.962 |
+6.187 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
+R12C38[2][A] |
+core0/n164_s/COUT |
-7.962 |
+6.187 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
+R12C38[2][B] |
+core0/n163_s/CIN |
-7.998 |
+6.222 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
+R12C38[2][B] |
+core0/n163_s/COUT |
-7.998 |
+6.222 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
+R12C39[0][A] |
+core0/n162_s/CIN |
-8.033 |
+6.257 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
+R12C39[0][A] |
+core0/n162_s/COUT |
-8.033 |
+6.257 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
+R12C39[0][B] |
+core0/n161_s/CIN |
-8.068 |
+6.292 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
+R12C39[0][B] |
+core0/n161_s/COUT |
-8.068 |
+6.292 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
+R12C39[1][A] |
+core0/n160_s/CIN |
-8.103 |
+6.327 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
+R12C39[1][A] |
+core0/n160_s/COUT |
-8.103 |
+6.327 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
+R12C39[1][B] |
+core0/n159_s/CIN |
-8.138 |
+6.363 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
+R12C39[1][B] |
+core0/n159_s/COUT |
-8.138 |
+6.363 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
+R12C39[2][A] |
+core0/n158_s/CIN |
-8.174 |
-0.035 |
+6.833 |
+0.470 |
tINS |
FF |
1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
+R12C39[2][A] |
+core0/n158_s/SUM |
-8.174 |
+7.731 |
+0.899 |
+tNET |
+FF |
+1 |
+R15C42[0][A] |
+core0/n228_s0/I0 |
+
+
+8.102 |
+0.371 |
+tINS |
+FF |
+1 |
+R15C42[0][A] |
+core0/n228_s0/F |
+
+
+8.102 |
0.000 |
tNET |
FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
-tNET |
-FF |
-1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
-
-
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-12.531 |
-2.002 |
-tNET |
-FF |
-1 |
-R38C35[0][B] |
-mem0/mem_s5264/I0 |
-
-
-13.086 |
-0.555 |
-tINS |
-FF |
-9 |
-R38C35[0][B] |
-mem0/mem_s5264/F |
-
-
-13.623 |
-0.537 |
-tNET |
-FF |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/I3 |
-
-
-14.193 |
-0.570 |
-tINS |
-FR |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/F |
-
-
-14.195 |
-0.001 |
-tNET |
-RR |
-1 |
-R36C39[3][A] |
-mem0/mem_s4983/I3 |
-
-
-14.765 |
-0.570 |
-tINS |
-RR |
-8 |
-R36C39[3][A] |
-mem0/mem_s4983/F |
-
-
-15.494 |
-0.730 |
-tNET |
-RR |
-1 |
-R34C35[1][A] |
-mem0/mem_mem_RAMREG_15_G[0]_s0/CE |
+R15C42[0][A] |
+core0/reg_wb_data_16_s0/D |
Data Required Path:
@@ -5131,7 +4717,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -5141,8 +4727,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R34C35[1][A] |
-mem0/mem_mem_RAMREG_15_G[0]_s0/CLK |
+R15C42[0][A] |
+core0/reg_wb_data_16_s0/CLK |
10.891 |
@@ -5150,8 +4736,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R34C35[1][A] |
-mem0/mem_mem_RAMREG_15_G[0]_s0 |
+R15C42[0][A] |
+core0/reg_wb_data_16_s0 |
Path Statistics:
@@ -5166,7 +4752,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+6 |
Arrival Clock Path Delay |
@@ -5174,7 +4760,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.549, 38.089%; route: 8.788, 60.319%; tC2Q: 0.232, 1.592% |
+cell: 2.459, 34.263%; route: 2.458, 34.245%; tC2Q: 2.260, 31.492% |
Required Clock Path Delay |
@@ -5186,11 +4772,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.537 |
+2.852 |
Data Arrival Time |
-15.428 |
+8.039 |
Data Required Time |
@@ -5198,11 +4784,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_24_G[2]_s0 |
+core0/reg_wb_data_28_s0 |
Launch Clk |
@@ -5256,7 +4842,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -5265,549 +4851,567 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-7.786 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-7.822 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-7.822 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-7.857 |
+6.081 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
+R12C38[0][B] |
+core0/n167_s/COUT |
-7.857 |
+6.081 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
+R12C38[1][A] |
+core0/n166_s/CIN |
-7.892 |
+6.116 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
+R12C38[1][A] |
+core0/n166_s/COUT |
-7.892 |
+6.116 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
+R12C38[1][B] |
+core0/n165_s/CIN |
-7.927 |
+6.151 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
+R12C38[1][B] |
+core0/n165_s/COUT |
-7.927 |
+6.151 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
+R12C38[2][A] |
+core0/n164_s/CIN |
-7.962 |
+6.187 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
+R12C38[2][A] |
+core0/n164_s/COUT |
-7.962 |
+6.187 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
+R12C38[2][B] |
+core0/n163_s/CIN |
-7.998 |
+6.222 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
+R12C38[2][B] |
+core0/n163_s/COUT |
-7.998 |
+6.222 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
+R12C39[0][A] |
+core0/n162_s/CIN |
-8.033 |
+6.257 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
+R12C39[0][A] |
+core0/n162_s/COUT |
-8.033 |
+6.257 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
+R12C39[0][B] |
+core0/n161_s/CIN |
-8.068 |
+6.292 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
+R12C39[0][B] |
+core0/n161_s/COUT |
-8.068 |
+6.292 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
+R12C39[1][A] |
+core0/n160_s/CIN |
-8.103 |
+6.327 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
+R12C39[1][A] |
+core0/n160_s/COUT |
-8.103 |
+6.327 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
+R12C39[1][B] |
+core0/n159_s/CIN |
-8.138 |
+6.363 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
+R12C39[1][B] |
+core0/n159_s/COUT |
-8.138 |
+6.363 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
+R12C39[2][A] |
+core0/n158_s/CIN |
-8.174 |
+6.398 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
+R12C39[2][A] |
+core0/n158_s/COUT |
-8.174 |
+6.398 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
+R12C39[2][B] |
+core0/n157_s/CIN |
-8.209 |
+6.433 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
+R12C39[2][B] |
+core0/n157_s/COUT |
-8.209 |
+6.433 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
+R12C40[0][A] |
+core0/n156_s/CIN |
-8.244 |
+6.468 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
+R12C40[0][A] |
+core0/n156_s/COUT |
-8.244 |
+6.468 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
+R12C40[0][B] |
+core0/n155_s/CIN |
-8.279 |
+6.503 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
+R12C40[0][B] |
+core0/n155_s/COUT |
-8.279 |
+6.503 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
+R12C40[1][A] |
+core0/n154_s/CIN |
-8.314 |
+6.539 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
+R12C40[1][A] |
+core0/n154_s/COUT |
-8.314 |
+6.539 |
0.000 |
tNET |
FF |
2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
+R12C40[1][B] |
+core0/n153_s/CIN |
-8.350 |
+6.574 |
0.035 |
tINS |
FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
-10.077 |
-1.727 |
+6.574 |
+0.000 |
tNET |
FF |
-1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
-10.530 |
-0.453 |
+6.609 |
+0.035 |
tINS |
FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
+1 |
+R12C40[2][A] |
+core0/n152_s/COUT |
-11.252 |
-0.722 |
+6.609 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][B] |
+core0/n151_s/CIN |
+
+
+6.644 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][B] |
+core0/n151_s/COUT |
+
+
+6.644 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][A] |
+core0/n150_s/CIN |
+
+
+6.679 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][A] |
+core0/n150_s/COUT |
+
+
+6.679 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][B] |
+core0/n149_s/CIN |
+
+
+6.715 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][B] |
+core0/n149_s/COUT |
+
+
+6.715 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][A] |
+core0/n148_s/CIN |
+
+
+6.750 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[1][A] |
+core0/n148_s/COUT |
+
+
+6.750 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][B] |
+core0/n147_s/CIN |
+
+
+6.785 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[1][B] |
+core0/n147_s/COUT |
+
+
+6.785 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[2][A] |
+core0/n146_s/CIN |
+
+
+7.255 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C41[2][A] |
+core0/n146_s/SUM |
+
+
+7.668 |
+0.413 |
tNET |
FF |
1 |
-R15C24[1][B] |
-mem0/mem_s5401/I0 |
+R13C42[1][A] |
+core0/n216_s0/I0 |
-11.769 |
-0.517 |
+8.039 |
+0.371 |
tINS |
FF |
-9 |
-R15C24[1][B] |
-mem0/mem_s5401/F |
+1 |
+R13C42[1][A] |
+core0/n216_s0/F |
-13.705 |
-1.936 |
+8.039 |
+0.000 |
tNET |
FF |
1 |
-R32C27[3][A] |
-mem0/mem_s5937/I3 |
-
-
-14.275 |
-0.570 |
-tINS |
-FR |
-1 |
-R32C27[3][A] |
-mem0/mem_s5937/F |
-
-
-14.276 |
-0.001 |
-tNET |
-RR |
-1 |
-R32C27[3][B] |
-mem0/mem_s4992/I2 |
-
-
-14.738 |
-0.462 |
-tINS |
-RR |
-8 |
-R32C27[3][B] |
-mem0/mem_s4992/F |
-
-
-15.428 |
-0.690 |
-tNET |
-RR |
-1 |
-R29C25[2][B] |
-mem0/mem_mem_RAMREG_24_G[2]_s0/CE |
+R13C42[1][A] |
+core0/reg_wb_data_28_s0/D |
Data Required Path:
@@ -5853,7 +5457,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -5863,8 +5467,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R29C25[2][B] |
-mem0/mem_mem_RAMREG_24_G[2]_s0/CLK |
+R13C42[1][A] |
+core0/reg_wb_data_28_s0/CLK |
10.891 |
@@ -5872,8 +5476,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R29C25[2][B] |
-mem0/mem_mem_RAMREG_24_G[2]_s0 |
+R13C42[1][A] |
+core0/reg_wb_data_28_s0 |
Path Statistics:
@@ -5888,7 +5492,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+8 |
Arrival Clock Path Delay |
@@ -5896,7 +5500,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.403, 37.256%; route: 8.867, 61.144%; tC2Q: 0.232, 1.600% |
+cell: 2.881, 40.505%; route: 1.972, 27.724%; tC2Q: 2.260, 31.772% |
Required Clock Path Delay |
@@ -5908,11 +5512,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.482 |
+2.893 |
Data Arrival Time |
-15.372 |
+7.998 |
Data Required Time |
@@ -5920,11 +5524,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_18_G[5]_s0 |
+core0/reg_wb_data_19_s0 |
Launch Clk |
@@ -5978,7 +5582,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -5987,297 +5591,405 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.391 |
-1.510 |
-tNET |
-FF |
-1 |
-R40C15[0][B] |
-mem0/n65_s4/I0 |
-
-
-4.946 |
-0.555 |
-tINS |
-FF |
-26 |
-R40C15[0][B] |
-mem0/n65_s4/F |
-
-
-5.412 |
-0.466 |
-tNET |
-FF |
-1 |
-R38C14[3][B] |
-mem0/n54_s4/I1 |
-
-
-5.929 |
-0.517 |
-tINS |
-FF |
-8 |
-R38C14[3][B] |
-mem0/n54_s4/F |
-
-
-6.383 |
-0.454 |
-tNET |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/I1 |
-
-
-6.938 |
-0.555 |
-tINS |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/F |
-
-
-7.335 |
-0.397 |
+5.300 |
+0.660 |
tNET |
FF |
2 |
-R36C14[1][A] |
-mem0/n52_s3/I1 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-7.905 |
+5.870 |
0.570 |
tINS |
FR |
1 |
-R36C14[1][A] |
-mem0/n52_s3/COUT |
+R12C37[0][B] |
+core0/n173_s/COUT |
-7.905 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R36C14[1][B] |
-mem0/n51_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.940 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R36C14[1][B] |
-mem0/n51_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.940 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][A] |
-mem0/n50_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.976 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][A] |
-mem0/n50_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.976 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][B] |
-mem0/n49_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-8.011 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][B] |
-mem0/n49_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-8.011 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][A] |
-mem0/n48_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-8.046 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][A] |
-mem0/n48_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-8.046 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][B] |
-mem0/n47_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-8.081 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][B] |
-mem0/n47_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-8.081 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R36C15[1][A] |
-mem0/n46_s2/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-8.116 |
+6.081 |
0.035 |
tINS |
FF |
-44 |
-R36C15[1][A] |
-mem0/n46_s2/COUT |
+1 |
+R12C38[0][B] |
+core0/n167_s/COUT |
-10.584 |
-2.467 |
+6.081 |
+0.000 |
tNET |
FF |
-1 |
-R13C36[3][A] |
-mem0/mem_s6339/I1 |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
-11.139 |
-0.555 |
-tINS |
-FF |
-64 |
-R13C36[3][A] |
-mem0/mem_s6339/F |
-
-
-12.224 |
-1.085 |
-tNET |
-FF |
-1 |
-R15C28[2][A] |
-mem0/mem_s6061/I2 |
-
-
-12.595 |
-0.371 |
-tINS |
-FF |
-9 |
-R15C28[2][A] |
-mem0/mem_s6061/F |
-
-
-13.015 |
-0.420 |
-tNET |
-FF |
-1 |
-R15C30[1][A] |
-mem0/mem_s5309/I2 |
-
-
-13.532 |
-0.517 |
+6.116 |
+0.035 |
tINS |
FF |
1 |
-R15C30[1][A] |
-mem0/mem_s5309/F |
+R12C38[1][A] |
+core0/n166_s/COUT |
-14.823 |
-1.291 |
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.292 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/COUT |
+
+
+6.292 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][A] |
+core0/n160_s/CIN |
+
+
+6.327 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][A] |
+core0/n160_s/COUT |
+
+
+6.327 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][B] |
+core0/n159_s/CIN |
+
+
+6.363 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][B] |
+core0/n159_s/COUT |
+
+
+6.363 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][A] |
+core0/n158_s/CIN |
+
+
+6.398 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][A] |
+core0/n158_s/COUT |
+
+
+6.398 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][B] |
+core0/n157_s/CIN |
+
+
+6.433 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][B] |
+core0/n157_s/COUT |
+
+
+6.433 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][A] |
+core0/n156_s/CIN |
+
+
+6.468 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][A] |
+core0/n156_s/COUT |
+
+
+6.468 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][B] |
+core0/n155_s/CIN |
+
+
+6.938 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C40[0][B] |
+core0/n155_s/SUM |
+
+
+7.428 |
+0.490 |
tNET |
FF |
1 |
-R15C33[1][B] |
-mem0/mem_s4605/I0 |
+R14C42[1][A] |
+core0/n225_s0/I0 |
-15.372 |
-0.549 |
+7.998 |
+0.570 |
tINS |
FR |
1 |
-R15C33[1][B] |
-mem0/mem_s4605/F |
+R14C42[1][A] |
+core0/n225_s0/F |
-15.372 |
+7.998 |
0.000 |
tNET |
RR |
1 |
-R15C33[1][B] |
-mem0/mem_mem_RAMREG_18_G[5]_s0/D |
+R14C42[1][A] |
+core0/reg_wb_data_19_s0/D |
Data Required Path:
@@ -6323,7 +6035,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -6333,8 +6045,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R15C33[1][B] |
-mem0/mem_mem_RAMREG_18_G[5]_s0/CLK |
+R14C42[1][A] |
+core0/reg_wb_data_19_s0/CLK |
10.891 |
@@ -6342,8 +6054,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R15C33[1][B] |
-mem0/mem_mem_RAMREG_18_G[5]_s0 |
+R14C42[1][A] |
+core0/reg_wb_data_19_s0 |
Path Statistics:
@@ -6358,7 +6070,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-12 |
+7 |
Arrival Clock Path Delay |
@@ -6366,7 +6078,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 4.955, 34.300%; route: 9.259, 64.094%; tC2Q: 0.232, 1.606% |
+cell: 2.763, 39.074%; route: 2.049, 28.969%; tC2Q: 2.260, 31.956% |
Required Clock Path Delay |
@@ -6378,11 +6090,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.448 |
+2.902 |
Data Arrival Time |
-15.339 |
+7.989 |
Data Required Time |
@@ -6390,11 +6102,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_18_G[5]_s0 |
+core0/reg_wb_data_24_s0 |
Launch Clk |
@@ -6448,7 +6160,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -6457,297 +6169,495 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.391 |
-1.510 |
-tNET |
-FF |
-1 |
-R40C15[0][B] |
-mem0/n65_s4/I0 |
-
-
-4.946 |
-0.555 |
-tINS |
-FF |
-26 |
-R40C15[0][B] |
-mem0/n65_s4/F |
-
-
-5.412 |
-0.466 |
-tNET |
-FF |
-1 |
-R38C14[3][B] |
-mem0/n54_s4/I1 |
-
-
-5.929 |
-0.517 |
-tINS |
-FF |
-8 |
-R38C14[3][B] |
-mem0/n54_s4/F |
-
-
-6.383 |
-0.454 |
-tNET |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/I1 |
-
-
-6.938 |
-0.555 |
-tINS |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/F |
-
-
-7.335 |
-0.397 |
+5.300 |
+0.660 |
tNET |
FF |
2 |
-R36C14[1][A] |
-mem0/n52_s3/I1 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-7.905 |
+5.870 |
0.570 |
tINS |
FR |
1 |
-R36C14[1][A] |
-mem0/n52_s3/COUT |
+R12C37[0][B] |
+core0/n173_s/COUT |
-7.905 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R36C14[1][B] |
-mem0/n51_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.940 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R36C14[1][B] |
-mem0/n51_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.940 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][A] |
-mem0/n50_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.976 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][A] |
-mem0/n50_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.976 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][B] |
-mem0/n49_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-8.011 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][B] |
-mem0/n49_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-8.011 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][A] |
-mem0/n48_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-8.046 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][A] |
-mem0/n48_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-8.046 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][B] |
-mem0/n47_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-8.081 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][B] |
-mem0/n47_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-8.081 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R36C15[1][A] |
-mem0/n46_s2/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-8.116 |
+6.081 |
0.035 |
tINS |
FF |
-44 |
-R36C15[1][A] |
-mem0/n46_s2/COUT |
+1 |
+R12C38[0][B] |
+core0/n167_s/COUT |
-10.584 |
-2.467 |
+6.081 |
+0.000 |
tNET |
FF |
-1 |
-R13C36[3][A] |
-mem0/mem_s6339/I1 |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
-11.139 |
-0.555 |
-tINS |
-FF |
-64 |
-R13C36[3][A] |
-mem0/mem_s6339/F |
-
-
-12.224 |
-1.085 |
-tNET |
-FF |
-1 |
-R15C28[2][A] |
-mem0/mem_s6061/I2 |
-
-
-12.595 |
-0.371 |
-tINS |
-FF |
-9 |
-R15C28[2][A] |
-mem0/mem_s6061/F |
-
-
-13.517 |
-0.922 |
-tNET |
-FF |
-1 |
-R17C29[3][A] |
-mem0/mem_s5929/I0 |
-
-
-13.888 |
-0.371 |
+6.116 |
+0.035 |
tINS |
FF |
1 |
-R17C29[3][A] |
-mem0/mem_s5929/F |
+R12C38[1][A] |
+core0/n166_s/COUT |
-13.892 |
-0.004 |
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.292 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/COUT |
+
+
+6.292 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][A] |
+core0/n160_s/CIN |
+
+
+6.327 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][A] |
+core0/n160_s/COUT |
+
+
+6.327 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][B] |
+core0/n159_s/CIN |
+
+
+6.363 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][B] |
+core0/n159_s/COUT |
+
+
+6.363 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][A] |
+core0/n158_s/CIN |
+
+
+6.398 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][A] |
+core0/n158_s/COUT |
+
+
+6.398 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][B] |
+core0/n157_s/CIN |
+
+
+6.433 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][B] |
+core0/n157_s/COUT |
+
+
+6.433 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][A] |
+core0/n156_s/CIN |
+
+
+6.468 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][A] |
+core0/n156_s/COUT |
+
+
+6.468 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][B] |
+core0/n155_s/CIN |
+
+
+6.503 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][B] |
+core0/n155_s/COUT |
+
+
+6.503 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][A] |
+core0/n154_s/CIN |
+
+
+6.539 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][A] |
+core0/n154_s/COUT |
+
+
+6.539 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][B] |
+core0/n153_s/CIN |
+
+
+6.574 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
+
+
+6.574 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
+
+
+6.609 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][A] |
+core0/n152_s/COUT |
+
+
+6.609 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][B] |
+core0/n151_s/CIN |
+
+
+6.644 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][B] |
+core0/n151_s/COUT |
+
+
+6.644 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][A] |
+core0/n150_s/CIN |
+
+
+7.114 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C41[0][A] |
+core0/n150_s/SUM |
+
+
+7.527 |
+0.413 |
tNET |
FF |
1 |
-R17C29[3][B] |
-mem0/mem_s4986/I3 |
+R13C42[1][B] |
+core0/n220_s0/I0 |
-14.354 |
+7.989 |
0.462 |
tINS |
FR |
-8 |
-R17C29[3][B] |
-mem0/mem_s4986/F |
+1 |
+R13C42[1][B] |
+core0/n220_s0/F |
-15.339 |
-0.985 |
+7.989 |
+0.000 |
tNET |
RR |
1 |
-R15C33[1][B] |
-mem0/mem_mem_RAMREG_18_G[5]_s0/CE |
+R13C42[1][B] |
+core0/reg_wb_data_24_s0/D |
Data Required Path:
@@ -6793,7 +6703,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -6803,8 +6713,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R15C33[1][B] |
-mem0/mem_mem_RAMREG_18_G[5]_s0/CLK |
+R13C42[1][B] |
+core0/reg_wb_data_24_s0/CLK |
10.891 |
@@ -6812,8 +6722,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R15C33[1][B] |
-mem0/mem_mem_RAMREG_18_G[5]_s0 |
+R13C42[1][B] |
+core0/reg_wb_data_24_s0 |
Path Statistics:
@@ -6828,7 +6738,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-12 |
+7 |
Arrival Clock Path Delay |
@@ -6836,7 +6746,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 4.722, 32.763%; route: 9.459, 65.628%; tC2Q: 0.232, 1.610% |
+cell: 2.831, 40.085%; route: 1.972, 27.919%; tC2Q: 2.260, 31.996% |
Required Clock Path Delay |
@@ -6848,11 +6758,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.448 |
+2.934 |
Data Arrival Time |
-15.339 |
+7.957 |
Data Required Time |
@@ -6860,11 +6770,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_18_G[1]_s0 |
+core0/reg_wb_data_20_s0 |
Launch Clk |
@@ -6918,7 +6828,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -6927,297 +6837,423 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.391 |
-1.510 |
-tNET |
-FF |
-1 |
-R40C15[0][B] |
-mem0/n65_s4/I0 |
-
-
-4.946 |
-0.555 |
-tINS |
-FF |
-26 |
-R40C15[0][B] |
-mem0/n65_s4/F |
-
-
-5.412 |
-0.466 |
-tNET |
-FF |
-1 |
-R38C14[3][B] |
-mem0/n54_s4/I1 |
-
-
-5.929 |
-0.517 |
-tINS |
-FF |
-8 |
-R38C14[3][B] |
-mem0/n54_s4/F |
-
-
-6.383 |
-0.454 |
-tNET |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/I1 |
-
-
-6.938 |
-0.555 |
-tINS |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/F |
-
-
-7.335 |
-0.397 |
+5.300 |
+0.660 |
tNET |
FF |
2 |
-R36C14[1][A] |
-mem0/n52_s3/I1 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-7.905 |
+5.870 |
0.570 |
tINS |
FR |
1 |
-R36C14[1][A] |
-mem0/n52_s3/COUT |
+R12C37[0][B] |
+core0/n173_s/COUT |
-7.905 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R36C14[1][B] |
-mem0/n51_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.940 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R36C14[1][B] |
-mem0/n51_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.940 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][A] |
-mem0/n50_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.976 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][A] |
-mem0/n50_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.976 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][B] |
-mem0/n49_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-8.011 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][B] |
-mem0/n49_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-8.011 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][A] |
-mem0/n48_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-8.046 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][A] |
-mem0/n48_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-8.046 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][B] |
-mem0/n47_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-8.081 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][B] |
-mem0/n47_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-8.081 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R36C15[1][A] |
-mem0/n46_s2/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-8.116 |
+6.081 |
0.035 |
tINS |
FF |
-44 |
-R36C15[1][A] |
-mem0/n46_s2/COUT |
+1 |
+R12C38[0][B] |
+core0/n167_s/COUT |
-10.584 |
-2.467 |
+6.081 |
+0.000 |
tNET |
FF |
-1 |
-R13C36[3][A] |
-mem0/mem_s6339/I1 |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
-11.139 |
-0.555 |
-tINS |
-FF |
-64 |
-R13C36[3][A] |
-mem0/mem_s6339/F |
-
-
-12.224 |
-1.085 |
-tNET |
-FF |
-1 |
-R15C28[2][A] |
-mem0/mem_s6061/I2 |
-
-
-12.595 |
-0.371 |
-tINS |
-FF |
-9 |
-R15C28[2][A] |
-mem0/mem_s6061/F |
-
-
-13.517 |
-0.922 |
-tNET |
-FF |
-1 |
-R17C29[3][A] |
-mem0/mem_s5929/I0 |
-
-
-13.888 |
-0.371 |
+6.116 |
+0.035 |
tINS |
FF |
1 |
-R17C29[3][A] |
-mem0/mem_s5929/F |
+R12C38[1][A] |
+core0/n166_s/COUT |
-13.892 |
-0.004 |
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.292 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/COUT |
+
+
+6.292 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][A] |
+core0/n160_s/CIN |
+
+
+6.327 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][A] |
+core0/n160_s/COUT |
+
+
+6.327 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][B] |
+core0/n159_s/CIN |
+
+
+6.363 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][B] |
+core0/n159_s/COUT |
+
+
+6.363 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][A] |
+core0/n158_s/CIN |
+
+
+6.398 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][A] |
+core0/n158_s/COUT |
+
+
+6.398 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][B] |
+core0/n157_s/CIN |
+
+
+6.433 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][B] |
+core0/n157_s/COUT |
+
+
+6.433 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][A] |
+core0/n156_s/CIN |
+
+
+6.468 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][A] |
+core0/n156_s/COUT |
+
+
+6.468 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][B] |
+core0/n155_s/CIN |
+
+
+6.503 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][B] |
+core0/n155_s/COUT |
+
+
+6.503 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][A] |
+core0/n154_s/CIN |
+
+
+6.973 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C40[1][A] |
+core0/n154_s/SUM |
+
+
+7.387 |
+0.413 |
tNET |
FF |
1 |
-R17C29[3][B] |
-mem0/mem_s4986/I3 |
+R13C39[0][B] |
+core0/n224_s0/I0 |
-14.354 |
-0.462 |
+7.957 |
+0.570 |
tINS |
FR |
-8 |
-R17C29[3][B] |
-mem0/mem_s4986/F |
+1 |
+R13C39[0][B] |
+core0/n224_s0/F |
-15.339 |
-0.985 |
+7.957 |
+0.000 |
tNET |
RR |
1 |
-R15C33[2][B] |
-mem0/mem_mem_RAMREG_18_G[1]_s0/CE |
+R13C39[0][B] |
+core0/reg_wb_data_20_s0/D |
Data Required Path:
@@ -7263,7 +7299,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -7273,8 +7309,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R15C33[2][B] |
-mem0/mem_mem_RAMREG_18_G[1]_s0/CLK |
+R13C39[0][B] |
+core0/reg_wb_data_20_s0/CLK |
10.891 |
@@ -7282,8 +7318,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R15C33[2][B] |
-mem0/mem_mem_RAMREG_18_G[1]_s0 |
+R13C39[0][B] |
+core0/reg_wb_data_20_s0 |
Path Statistics:
@@ -7298,7 +7334,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-12 |
+7 |
Arrival Clock Path Delay |
@@ -7306,7 +7342,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 4.722, 32.763%; route: 9.459, 65.628%; tC2Q: 0.232, 1.610% |
+cell: 2.799, 39.806%; route: 1.972, 28.049%; tC2Q: 2.260, 32.145% |
Required Clock Path Delay |
@@ -7318,11 +7354,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.434 |
+2.959 |
Data Arrival Time |
-15.324 |
+7.932 |
Data Required Time |
@@ -7330,11 +7366,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_19_G[6]_s0 |
+core0/reg_wb_data_13_s0 |
Launch Clk |
@@ -7388,7 +7424,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -7397,297 +7433,297 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.391 |
-1.510 |
-tNET |
-FF |
-1 |
-R40C15[0][B] |
-mem0/n65_s4/I0 |
-
-
-4.946 |
-0.555 |
-tINS |
-FF |
-26 |
-R40C15[0][B] |
-mem0/n65_s4/F |
-
-
-5.412 |
-0.466 |
-tNET |
-FF |
-1 |
-R38C14[3][B] |
-mem0/n54_s4/I1 |
-
-
-5.929 |
-0.517 |
-tINS |
-FF |
-8 |
-R38C14[3][B] |
-mem0/n54_s4/F |
-
-
-6.383 |
-0.454 |
-tNET |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/I1 |
-
-
-6.938 |
-0.555 |
-tINS |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/F |
-
-
-7.335 |
-0.397 |
+5.300 |
+0.660 |
tNET |
FF |
2 |
-R36C14[1][A] |
-mem0/n52_s3/I1 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-7.905 |
+5.870 |
0.570 |
tINS |
FR |
1 |
-R36C14[1][A] |
-mem0/n52_s3/COUT |
+R12C37[0][B] |
+core0/n173_s/COUT |
-7.905 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R36C14[1][B] |
-mem0/n51_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.940 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R36C14[1][B] |
-mem0/n51_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.940 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][A] |
-mem0/n50_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.976 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][A] |
-mem0/n50_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.976 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][B] |
-mem0/n49_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-8.011 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][B] |
-mem0/n49_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-8.011 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][A] |
-mem0/n48_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-8.046 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][A] |
-mem0/n48_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-8.046 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][B] |
-mem0/n47_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-8.081 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][B] |
-mem0/n47_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-8.081 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R36C15[1][A] |
-mem0/n46_s2/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-8.116 |
+6.081 |
0.035 |
tINS |
FF |
-44 |
-R36C15[1][A] |
-mem0/n46_s2/COUT |
+1 |
+R12C38[0][B] |
+core0/n167_s/COUT |
-10.584 |
-2.467 |
+6.081 |
+0.000 |
tNET |
FF |
-1 |
-R13C36[3][A] |
-mem0/mem_s6339/I1 |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
-11.139 |
-0.555 |
-tINS |
-FF |
-64 |
-R13C36[3][A] |
-mem0/mem_s6339/F |
-
-
-12.718 |
-1.579 |
-tNET |
-FF |
-1 |
-R36C24[3][A] |
-mem0/mem_s6063/I2 |
-
-
-13.273 |
-0.555 |
-tINS |
-FF |
-9 |
-R36C24[3][A] |
-mem0/mem_s6063/F |
-
-
-13.488 |
-0.215 |
-tNET |
-FF |
-1 |
-R36C25[3][B] |
-mem0/mem_s5328/I2 |
-
-
-14.043 |
-0.555 |
+6.116 |
+0.035 |
tINS |
FF |
1 |
-R36C25[3][B] |
-mem0/mem_s5328/F |
+R12C38[1][A] |
+core0/n166_s/COUT |
-14.775 |
-0.733 |
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.727 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/SUM |
+
+
+7.383 |
+0.656 |
tNET |
FF |
1 |
-R35C25[2][A] |
-mem0/mem_s4614/I0 |
+R15C40[0][A] |
+core0/n231_s0/I0 |
-15.324 |
+7.932 |
0.549 |
tINS |
FR |
1 |
-R35C25[2][A] |
-mem0/mem_s4614/F |
+R15C40[0][A] |
+core0/n231_s0/F |
-15.324 |
+7.932 |
0.000 |
tNET |
RR |
1 |
-R35C25[2][A] |
-mem0/mem_mem_RAMREG_19_G[6]_s0/D |
+R15C40[0][A] |
+core0/reg_wb_data_13_s0/D |
Data Required Path:
@@ -7733,7 +7769,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -7743,8 +7779,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R35C25[2][A] |
-mem0/mem_mem_RAMREG_19_G[6]_s0/CLK |
+R15C40[0][A] |
+core0/reg_wb_data_13_s0/CLK |
10.891 |
@@ -7752,8 +7788,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R35C25[2][A] |
-mem0/mem_mem_RAMREG_19_G[6]_s0 |
+R15C40[0][A] |
+core0/reg_wb_data_13_s0 |
Path Statistics:
@@ -7768,7 +7804,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-12 |
+6 |
Arrival Clock Path Delay |
@@ -7776,7 +7812,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.177, 35.956%; route: 8.989, 62.432%; tC2Q: 0.232, 1.611% |
+cell: 2.531, 36.129%; route: 2.215, 31.613%; tC2Q: 2.260, 32.258% |
Required Clock Path Delay |
@@ -7788,11 +7824,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.395 |
+3.005 |
Data Arrival Time |
-15.285 |
+7.886 |
Data Required Time |
@@ -7800,11 +7836,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_24_G[1]_s0 |
+core0/reg_wb_data_18_s0 |
Launch Clk |
@@ -7858,7 +7894,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -7867,549 +7903,387 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-7.786 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-7.822 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-7.822 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-7.857 |
+6.081 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
+R12C38[0][B] |
+core0/n167_s/COUT |
-7.857 |
+6.081 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
+R12C38[1][A] |
+core0/n166_s/CIN |
-7.892 |
+6.116 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
+R12C38[1][A] |
+core0/n166_s/COUT |
-7.892 |
+6.116 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
+R12C38[1][B] |
+core0/n165_s/CIN |
-7.927 |
+6.151 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
+R12C38[1][B] |
+core0/n165_s/COUT |
-7.927 |
+6.151 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
+R12C38[2][A] |
+core0/n164_s/CIN |
-7.962 |
+6.187 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
+R12C38[2][A] |
+core0/n164_s/COUT |
-7.962 |
+6.187 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
+R12C38[2][B] |
+core0/n163_s/CIN |
-7.998 |
+6.222 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
+R12C38[2][B] |
+core0/n163_s/COUT |
-7.998 |
+6.222 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
+R12C39[0][A] |
+core0/n162_s/CIN |
-8.033 |
+6.257 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
+R12C39[0][A] |
+core0/n162_s/COUT |
-8.033 |
+6.257 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
+R12C39[0][B] |
+core0/n161_s/CIN |
-8.068 |
+6.292 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
+R12C39[0][B] |
+core0/n161_s/COUT |
-8.068 |
+6.292 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
+R12C39[1][A] |
+core0/n160_s/CIN |
-8.103 |
+6.327 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
+R12C39[1][A] |
+core0/n160_s/COUT |
-8.103 |
+6.327 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
+R12C39[1][B] |
+core0/n159_s/CIN |
-8.138 |
+6.363 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
+R12C39[1][B] |
+core0/n159_s/COUT |
-8.138 |
+6.363 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
+R12C39[2][A] |
+core0/n158_s/CIN |
-8.174 |
+6.398 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
+R12C39[2][A] |
+core0/n158_s/COUT |
-8.174 |
+6.398 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
+R12C39[2][B] |
+core0/n157_s/CIN |
-8.209 |
+6.433 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
+R12C39[2][B] |
+core0/n157_s/COUT |
-8.209 |
+6.433 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
+R12C40[0][A] |
+core0/n156_s/CIN |
-8.244 |
-0.035 |
+6.903 |
+0.470 |
tINS |
FF |
1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
+R12C40[0][A] |
+core0/n156_s/SUM |
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
+7.316 |
+0.413 |
tNET |
FF |
1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
+R13C42[0][B] |
+core0/n226_s0/I0 |
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-11.252 |
-0.722 |
-tNET |
-FF |
-1 |
-R15C24[1][B] |
-mem0/mem_s5401/I0 |
-
-
-11.769 |
-0.517 |
-tINS |
-FF |
-9 |
-R15C24[1][B] |
-mem0/mem_s5401/F |
-
-
-13.705 |
-1.936 |
-tNET |
-FF |
-1 |
-R32C27[3][A] |
-mem0/mem_s5937/I3 |
-
-
-14.275 |
+7.886 |
0.570 |
tINS |
FR |
1 |
-R32C27[3][A] |
-mem0/mem_s5937/F |
+R13C42[0][B] |
+core0/n226_s0/F |
-14.276 |
-0.001 |
+7.886 |
+0.000 |
tNET |
RR |
1 |
-R32C27[3][B] |
-mem0/mem_s4992/I2 |
-
-
-14.738 |
-0.462 |
-tINS |
-RR |
-8 |
-R32C27[3][B] |
-mem0/mem_s4992/F |
-
-
-15.285 |
-0.547 |
-tNET |
-RR |
-1 |
-R29C28[0][B] |
-mem0/mem_mem_RAMREG_24_G[1]_s0/CE |
+R13C42[0][B] |
+core0/reg_wb_data_18_s0/D |
Data Required Path:
@@ -8455,7 +8329,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -8465,8 +8339,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R29C28[0][B] |
-mem0/mem_mem_RAMREG_24_G[1]_s0/CLK |
+R13C42[0][B] |
+core0/reg_wb_data_18_s0/CLK |
10.891 |
@@ -8474,8 +8348,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R29C28[0][B] |
-mem0/mem_mem_RAMREG_24_G[1]_s0 |
+R13C42[0][B] |
+core0/reg_wb_data_18_s0 |
Path Statistics:
@@ -8490,7 +8364,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+7 |
Arrival Clock Path Delay |
@@ -8498,7 +8372,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.403, 37.627%; route: 8.725, 60.758%; tC2Q: 0.232, 1.616% |
+cell: 2.728, 39.197%; route: 1.972, 28.333%; tC2Q: 2.260, 32.470% |
Required Clock Path Delay |
@@ -8510,11 +8384,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.315 |
+3.039 |
Data Arrival Time |
-15.206 |
+7.852 |
Data Required Time |
@@ -8522,11 +8396,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_30_G[1]_s0 |
+core0/reg_wb_data_27_s0 |
Launch Clk |
@@ -8580,7 +8454,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -8589,549 +8463,549 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-7.786 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-7.822 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-7.822 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-7.857 |
+6.081 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
+R12C38[0][B] |
+core0/n167_s/COUT |
-7.857 |
+6.081 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
+R12C38[1][A] |
+core0/n166_s/CIN |
-7.892 |
+6.116 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
+R12C38[1][A] |
+core0/n166_s/COUT |
-7.892 |
+6.116 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
+R12C38[1][B] |
+core0/n165_s/CIN |
-7.927 |
+6.151 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
+R12C38[1][B] |
+core0/n165_s/COUT |
-7.927 |
+6.151 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
+R12C38[2][A] |
+core0/n164_s/CIN |
-7.962 |
+6.187 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
+R12C38[2][A] |
+core0/n164_s/COUT |
-7.962 |
+6.187 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
+R12C38[2][B] |
+core0/n163_s/CIN |
-7.998 |
+6.222 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
+R12C38[2][B] |
+core0/n163_s/COUT |
-7.998 |
+6.222 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
+R12C39[0][A] |
+core0/n162_s/CIN |
-8.033 |
+6.257 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
+R12C39[0][A] |
+core0/n162_s/COUT |
-8.033 |
+6.257 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
+R12C39[0][B] |
+core0/n161_s/CIN |
-8.068 |
+6.292 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
+R12C39[0][B] |
+core0/n161_s/COUT |
-8.068 |
+6.292 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
+R12C39[1][A] |
+core0/n160_s/CIN |
-8.103 |
+6.327 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
+R12C39[1][A] |
+core0/n160_s/COUT |
-8.103 |
+6.327 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
+R12C39[1][B] |
+core0/n159_s/CIN |
-8.138 |
+6.363 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
+R12C39[1][B] |
+core0/n159_s/COUT |
-8.138 |
+6.363 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
+R12C39[2][A] |
+core0/n158_s/CIN |
-8.174 |
+6.398 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
+R12C39[2][A] |
+core0/n158_s/COUT |
-8.174 |
+6.398 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
+R12C39[2][B] |
+core0/n157_s/CIN |
-8.209 |
+6.433 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
+R12C39[2][B] |
+core0/n157_s/COUT |
-8.209 |
+6.433 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
+R12C40[0][A] |
+core0/n156_s/CIN |
-8.244 |
+6.468 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
+R12C40[0][A] |
+core0/n156_s/COUT |
-8.244 |
+6.468 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
+R12C40[0][B] |
+core0/n155_s/CIN |
-8.279 |
+6.503 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
+R12C40[0][B] |
+core0/n155_s/COUT |
-8.279 |
+6.503 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
+R12C40[1][A] |
+core0/n154_s/CIN |
-8.314 |
+6.539 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
+R12C40[1][A] |
+core0/n154_s/COUT |
-8.314 |
+6.539 |
0.000 |
tNET |
FF |
2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
+R12C40[1][B] |
+core0/n153_s/CIN |
-8.350 |
+6.574 |
0.035 |
tINS |
FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
-10.077 |
-1.727 |
+6.574 |
+0.000 |
tNET |
FF |
-1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
-10.530 |
-0.453 |
+6.609 |
+0.035 |
tINS |
FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
+1 |
+R12C40[2][A] |
+core0/n152_s/COUT |
-11.252 |
-0.722 |
+6.609 |
+0.000 |
tNET |
FF |
-1 |
-R15C24[1][A] |
-mem0/mem_s5463/I0 |
+2 |
+R12C40[2][B] |
+core0/n151_s/CIN |
-11.769 |
-0.517 |
+6.644 |
+0.035 |
tINS |
FF |
-9 |
-R15C24[1][A] |
-mem0/mem_s5463/F |
+1 |
+R12C40[2][B] |
+core0/n151_s/COUT |
-13.541 |
-1.772 |
+6.644 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][A] |
+core0/n150_s/CIN |
+
+
+6.679 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][A] |
+core0/n150_s/COUT |
+
+
+6.679 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][B] |
+core0/n149_s/CIN |
+
+
+6.715 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][B] |
+core0/n149_s/COUT |
+
+
+6.715 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][A] |
+core0/n148_s/CIN |
+
+
+6.750 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[1][A] |
+core0/n148_s/COUT |
+
+
+6.750 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][B] |
+core0/n147_s/CIN |
+
+
+7.220 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C41[1][B] |
+core0/n147_s/SUM |
+
+
+7.390 |
+0.170 |
tNET |
FF |
1 |
-R40C38[1][B] |
-mem0/mem_s5944/I2 |
+R12C42[1][A] |
+core0/n217_s0/I0 |
-14.090 |
-0.549 |
+7.852 |
+0.462 |
tINS |
FR |
1 |
-R40C38[1][B] |
-mem0/mem_s5944/F |
+R12C42[1][A] |
+core0/n217_s0/F |
-14.091 |
-0.001 |
+7.852 |
+0.000 |
tNET |
RR |
1 |
-R40C38[0][B] |
-mem0/mem_s4998/I3 |
-
-
-14.661 |
-0.570 |
-tINS |
-RR |
-8 |
-R40C38[0][B] |
-mem0/mem_s4998/F |
-
-
-15.206 |
-0.545 |
-tNET |
-RR |
-1 |
-R39C35[2][B] |
-mem0/mem_mem_RAMREG_30_G[1]_s0/CE |
+R12C42[1][A] |
+core0/reg_wb_data_27_s0/D |
Data Required Path:
@@ -9177,7 +9051,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -9187,8 +9061,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R39C35[2][B] |
-mem0/mem_mem_RAMREG_30_G[1]_s0/CLK |
+R12C42[1][A] |
+core0/reg_wb_data_27_s0/CLK |
10.891 |
@@ -9196,8 +9070,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R39C35[2][B] |
-mem0/mem_mem_RAMREG_30_G[1]_s0 |
+R12C42[1][A] |
+core0/reg_wb_data_27_s0 |
Path Statistics:
@@ -9212,7 +9086,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+7 |
Arrival Clock Path Delay |
@@ -9220,7 +9094,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.490, 38.445%; route: 8.558, 59.931%; tC2Q: 0.232, 1.625% |
+cell: 2.937, 42.403%; route: 1.729, 24.968%; tC2Q: 2.260, 32.629% |
Required Clock Path Delay |
@@ -9232,11 +9106,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.291 |
+3.044 |
Data Arrival Time |
-15.182 |
+7.847 |
Data Required Time |
@@ -9244,11 +9118,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_44_G[3]_s0 |
+core0/reg_wb_data_23_s0 |
Launch Clk |
@@ -9302,7 +9176,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -9311,297 +9185,477 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.391 |
-1.510 |
-tNET |
-FF |
-1 |
-R40C15[0][B] |
-mem0/n65_s4/I0 |
-
-
-4.946 |
-0.555 |
-tINS |
-FF |
-26 |
-R40C15[0][B] |
-mem0/n65_s4/F |
-
-
-5.412 |
-0.466 |
-tNET |
-FF |
-1 |
-R38C14[3][B] |
-mem0/n54_s4/I1 |
-
-
-5.929 |
-0.517 |
-tINS |
-FF |
-8 |
-R38C14[3][B] |
-mem0/n54_s4/F |
-
-
-6.383 |
-0.454 |
-tNET |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/I1 |
-
-
-6.938 |
-0.555 |
-tINS |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/F |
-
-
-7.335 |
-0.397 |
+5.300 |
+0.660 |
tNET |
FF |
2 |
-R36C14[1][A] |
-mem0/n52_s3/I1 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-7.905 |
+5.870 |
0.570 |
tINS |
FR |
1 |
-R36C14[1][A] |
-mem0/n52_s3/COUT |
+R12C37[0][B] |
+core0/n173_s/COUT |
-7.905 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R36C14[1][B] |
-mem0/n51_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.940 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R36C14[1][B] |
-mem0/n51_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.940 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][A] |
-mem0/n50_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.976 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][A] |
-mem0/n50_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.976 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][B] |
-mem0/n49_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-8.011 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][B] |
-mem0/n49_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-8.011 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][A] |
-mem0/n48_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-8.046 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][A] |
-mem0/n48_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-8.046 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][B] |
-mem0/n47_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-8.081 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][B] |
-mem0/n47_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-8.081 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R36C15[1][A] |
-mem0/n46_s2/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-8.116 |
+6.081 |
0.035 |
tINS |
FF |
-44 |
-R36C15[1][A] |
-mem0/n46_s2/COUT |
-
-
-9.852 |
-1.736 |
-tNET |
-FF |
1 |
-R13C17[0][A] |
-mem0/mem_s6342/I0 |
+R12C38[0][B] |
+core0/n167_s/COUT |
-10.369 |
-0.517 |
-tINS |
-FF |
-80 |
-R13C17[0][A] |
-mem0/mem_s6342/F |
-
-
-11.679 |
-1.310 |
-tNET |
-FF |
-1 |
-R22C35[1][B] |
-mem0/mem_s6203/I3 |
-
-
-12.234 |
-0.555 |
-tINS |
-FF |
-9 |
-R22C35[1][B] |
-mem0/mem_s6203/F |
-
-
-12.947 |
-0.712 |
-tNET |
-FF |
-1 |
-R21C42[3][B] |
-mem0/mem_s5648/I2 |
-
-
-13.464 |
-0.517 |
-tINS |
-FF |
-1 |
-R21C42[3][B] |
-mem0/mem_s5648/F |
-
-
-14.633 |
-1.170 |
-tNET |
-FF |
-1 |
-R24C33[1][A] |
-mem0/mem_s4811/I0 |
-
-
-15.182 |
-0.549 |
-tINS |
-FR |
-1 |
-R24C33[1][A] |
-mem0/mem_s4811/F |
-
-
-15.182 |
+6.081 |
0.000 |
tNET |
-RR |
+FF |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
+
+
+6.116 |
+0.035 |
+tINS |
+FF |
1 |
-R24C33[1][A] |
-mem0/mem_mem_RAMREG_44_G[3]_s0/D |
+R12C38[1][A] |
+core0/n166_s/COUT |
+
+
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.292 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/COUT |
+
+
+6.292 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][A] |
+core0/n160_s/CIN |
+
+
+6.327 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][A] |
+core0/n160_s/COUT |
+
+
+6.327 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][B] |
+core0/n159_s/CIN |
+
+
+6.363 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][B] |
+core0/n159_s/COUT |
+
+
+6.363 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][A] |
+core0/n158_s/CIN |
+
+
+6.398 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][A] |
+core0/n158_s/COUT |
+
+
+6.398 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][B] |
+core0/n157_s/CIN |
+
+
+6.433 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][B] |
+core0/n157_s/COUT |
+
+
+6.433 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][A] |
+core0/n156_s/CIN |
+
+
+6.468 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][A] |
+core0/n156_s/COUT |
+
+
+6.468 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][B] |
+core0/n155_s/CIN |
+
+
+6.503 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][B] |
+core0/n155_s/COUT |
+
+
+6.503 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][A] |
+core0/n154_s/CIN |
+
+
+6.539 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][A] |
+core0/n154_s/COUT |
+
+
+6.539 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][B] |
+core0/n153_s/CIN |
+
+
+6.574 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
+
+
+6.574 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
+
+
+6.609 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][A] |
+core0/n152_s/COUT |
+
+
+6.609 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][B] |
+core0/n151_s/CIN |
+
+
+7.079 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C40[2][B] |
+core0/n151_s/SUM |
+
+
+7.476 |
+0.397 |
+tNET |
+FF |
+1 |
+R14C40[2][A] |
+core0/n221_s0/I0 |
+
+
+7.847 |
+0.371 |
+tINS |
+FF |
+1 |
+R14C40[2][A] |
+core0/n221_s0/F |
+
+
+7.847 |
+0.000 |
+tNET |
+FF |
+1 |
+R14C40[2][A] |
+core0/reg_wb_data_23_s0/D |
Data Required Path:
@@ -9647,7 +9701,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -9657,8 +9711,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R24C33[1][A] |
-mem0/mem_mem_RAMREG_44_G[3]_s0/CLK |
+R14C40[2][A] |
+core0/reg_wb_data_23_s0/CLK |
10.891 |
@@ -9666,8 +9720,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R24C33[1][A] |
-mem0/mem_mem_RAMREG_44_G[3]_s0 |
+R14C40[2][A] |
+core0/reg_wb_data_23_s0 |
Path Statistics:
@@ -9682,7 +9736,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-12 |
+7 |
Arrival Clock Path Delay |
@@ -9690,7 +9744,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.101, 35.782%; route: 8.923, 62.590%; tC2Q: 0.232, 1.627% |
+cell: 2.705, 39.086%; route: 1.956, 28.260%; tC2Q: 2.260, 32.654% |
Required Clock Path Delay |
@@ -9702,11 +9756,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.262 |
+3.061 |
Data Arrival Time |
-15.153 |
+7.830 |
Data Required Time |
@@ -9714,11 +9768,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_51_G[7]_s0 |
+core0/reg_wb_data_17_s0 |
Launch Clk |
@@ -9772,7 +9826,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -9781,549 +9835,369 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-7.786 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-7.822 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-7.822 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-7.857 |
+6.081 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
+R12C38[0][B] |
+core0/n167_s/COUT |
-7.857 |
+6.081 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
+R12C38[1][A] |
+core0/n166_s/CIN |
-7.892 |
+6.116 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
+R12C38[1][A] |
+core0/n166_s/COUT |
-7.892 |
+6.116 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
+R12C38[1][B] |
+core0/n165_s/CIN |
-7.927 |
+6.151 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
+R12C38[1][B] |
+core0/n165_s/COUT |
-7.927 |
+6.151 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
+R12C38[2][A] |
+core0/n164_s/CIN |
-7.962 |
+6.187 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
+R12C38[2][A] |
+core0/n164_s/COUT |
-7.962 |
+6.187 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
+R12C38[2][B] |
+core0/n163_s/CIN |
-7.998 |
+6.222 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
+R12C38[2][B] |
+core0/n163_s/COUT |
-7.998 |
+6.222 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
+R12C39[0][A] |
+core0/n162_s/CIN |
-8.033 |
+6.257 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
+R12C39[0][A] |
+core0/n162_s/COUT |
-8.033 |
+6.257 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
+R12C39[0][B] |
+core0/n161_s/CIN |
-8.068 |
+6.292 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
+R12C39[0][B] |
+core0/n161_s/COUT |
-8.068 |
+6.292 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
+R12C39[1][A] |
+core0/n160_s/CIN |
-8.103 |
+6.327 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
+R12C39[1][A] |
+core0/n160_s/COUT |
-8.103 |
+6.327 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
+R12C39[1][B] |
+core0/n159_s/CIN |
-8.138 |
+6.363 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
+R12C39[1][B] |
+core0/n159_s/COUT |
-8.138 |
+6.363 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
+R12C39[2][A] |
+core0/n158_s/CIN |
-8.174 |
+6.398 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
+R12C39[2][A] |
+core0/n158_s/COUT |
-8.174 |
+6.398 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
+R12C39[2][B] |
+core0/n157_s/CIN |
-8.209 |
-0.035 |
+6.868 |
+0.470 |
tINS |
FF |
1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
+R12C39[2][B] |
+core0/n157_s/SUM |
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.425 |
-2.075 |
+7.281 |
+0.413 |
tNET |
FF |
1 |
-R15C23[0][A] |
-mem0/mem_s6068/I1 |
+R14C40[2][B] |
+core0/n227_s0/I0 |
-10.796 |
-0.371 |
-tINS |
-FF |
-11 |
-R15C23[0][A] |
-mem0/mem_s6068/F |
-
-
-11.918 |
-1.121 |
-tNET |
-FF |
-1 |
-R27C21[1][B] |
-mem0/mem_s5725/I2 |
-
-
-12.289 |
-0.371 |
-tINS |
-FF |
-9 |
-R27C21[1][B] |
-mem0/mem_s5725/F |
-
-
-13.538 |
-1.250 |
-tNET |
-FF |
-1 |
-R39C27[3][A] |
-mem0/mem_s5974/I2 |
-
-
-14.108 |
-0.570 |
+7.830 |
+0.549 |
tINS |
FR |
1 |
-R39C27[3][A] |
-mem0/mem_s5974/F |
+R14C40[2][B] |
+core0/n227_s0/F |
-14.110 |
-0.001 |
+7.830 |
+0.000 |
tNET |
RR |
1 |
-R39C27[2][B] |
-mem0/mem_s5019/I3 |
-
-
-14.572 |
-0.462 |
-tINS |
-RR |
-8 |
-R39C27[2][B] |
-mem0/mem_s5019/F |
-
-
-15.153 |
-0.581 |
-tNET |
-RR |
-1 |
-R40C21[2][A] |
-mem0/mem_mem_RAMREG_51_G[7]_s0/CE |
+R14C40[2][B] |
+core0/reg_wb_data_17_s0/D |
Data Required Path:
@@ -10369,7 +10243,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -10379,8 +10253,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R40C21[2][A] |
-mem0/mem_mem_RAMREG_51_G[7]_s0/CLK |
+R14C40[2][B] |
+core0/reg_wb_data_17_s0/CLK |
10.891 |
@@ -10388,8 +10262,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R40C21[2][A] |
-mem0/mem_mem_RAMREG_51_G[7]_s0 |
+R14C40[2][B] |
+core0/reg_wb_data_17_s0 |
Path Statistics:
@@ -10404,7 +10278,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+6 |
Arrival Clock Path Delay |
@@ -10412,7 +10286,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.175, 36.375%; route: 8.820, 61.994%; tC2Q: 0.232, 1.631% |
+cell: 2.672, 38.702%; route: 1.972, 28.564%; tC2Q: 2.260, 32.734% |
Required Clock Path Delay |
@@ -10424,11 +10298,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.262 |
+3.098 |
Data Arrival Time |
-15.153 |
+7.793 |
Data Required Time |
@@ -10436,11 +10310,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_51_G[3]_s0 |
+core0/reg_wb_data_21_s0 |
Launch Clk |
@@ -10494,7 +10368,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -10503,549 +10377,441 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-7.786 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-7.822 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-7.822 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-7.857 |
+6.081 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
+R12C38[0][B] |
+core0/n167_s/COUT |
-7.857 |
+6.081 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
+R12C38[1][A] |
+core0/n166_s/CIN |
-7.892 |
+6.116 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
+R12C38[1][A] |
+core0/n166_s/COUT |
-7.892 |
+6.116 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
+R12C38[1][B] |
+core0/n165_s/CIN |
-7.927 |
+6.151 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
+R12C38[1][B] |
+core0/n165_s/COUT |
-7.927 |
+6.151 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
+R12C38[2][A] |
+core0/n164_s/CIN |
-7.962 |
+6.187 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
+R12C38[2][A] |
+core0/n164_s/COUT |
-7.962 |
+6.187 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
+R12C38[2][B] |
+core0/n163_s/CIN |
-7.998 |
+6.222 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
+R12C38[2][B] |
+core0/n163_s/COUT |
-7.998 |
+6.222 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
+R12C39[0][A] |
+core0/n162_s/CIN |
-8.033 |
+6.257 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
+R12C39[0][A] |
+core0/n162_s/COUT |
-8.033 |
+6.257 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
+R12C39[0][B] |
+core0/n161_s/CIN |
-8.068 |
+6.292 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
+R12C39[0][B] |
+core0/n161_s/COUT |
-8.068 |
+6.292 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
+R12C39[1][A] |
+core0/n160_s/CIN |
-8.103 |
+6.327 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
+R12C39[1][A] |
+core0/n160_s/COUT |
-8.103 |
+6.327 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
+R12C39[1][B] |
+core0/n159_s/CIN |
-8.138 |
+6.363 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
+R12C39[1][B] |
+core0/n159_s/COUT |
-8.138 |
+6.363 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
+R12C39[2][A] |
+core0/n158_s/CIN |
-8.174 |
+6.398 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
+R12C39[2][A] |
+core0/n158_s/COUT |
-8.174 |
+6.398 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
+R12C39[2][B] |
+core0/n157_s/CIN |
-8.209 |
+6.433 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
+R12C39[2][B] |
+core0/n157_s/COUT |
-8.209 |
+6.433 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
+R12C40[0][A] |
+core0/n156_s/CIN |
-8.244 |
+6.468 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
+R12C40[0][A] |
+core0/n156_s/COUT |
-8.244 |
+6.468 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
+R12C40[0][B] |
+core0/n155_s/CIN |
-8.279 |
+6.503 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
+R12C40[0][B] |
+core0/n155_s/COUT |
-8.279 |
+6.503 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
+R12C40[1][A] |
+core0/n154_s/CIN |
-8.314 |
+6.539 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
+R12C40[1][A] |
+core0/n154_s/COUT |
-8.314 |
+6.539 |
0.000 |
tNET |
FF |
2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
+R12C40[1][B] |
+core0/n153_s/CIN |
-8.350 |
-0.035 |
+7.009 |
+0.470 |
tINS |
FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
+1 |
+R12C40[1][B] |
+core0/n153_s/SUM |
-10.425 |
-2.075 |
+7.422 |
+0.413 |
tNET |
FF |
1 |
-R15C23[0][A] |
-mem0/mem_s6068/I1 |
+R13C39[0][A] |
+core0/n223_s0/I0 |
-10.796 |
+7.793 |
0.371 |
tINS |
FF |
-11 |
-R15C23[0][A] |
-mem0/mem_s6068/F |
+1 |
+R13C39[0][A] |
+core0/n223_s0/F |
-11.918 |
-1.121 |
+7.793 |
+0.000 |
tNET |
FF |
1 |
-R27C21[1][B] |
-mem0/mem_s5725/I2 |
-
-
-12.289 |
-0.371 |
-tINS |
-FF |
-9 |
-R27C21[1][B] |
-mem0/mem_s5725/F |
-
-
-13.538 |
-1.250 |
-tNET |
-FF |
-1 |
-R39C27[3][A] |
-mem0/mem_s5974/I2 |
-
-
-14.108 |
-0.570 |
-tINS |
-FR |
-1 |
-R39C27[3][A] |
-mem0/mem_s5974/F |
-
-
-14.110 |
-0.001 |
-tNET |
-RR |
-1 |
-R39C27[2][B] |
-mem0/mem_s5019/I3 |
-
-
-14.572 |
-0.462 |
-tINS |
-RR |
-8 |
-R39C27[2][B] |
-mem0/mem_s5019/F |
-
-
-15.153 |
-0.581 |
-tNET |
-RR |
-1 |
-R40C21[0][B] |
-mem0/mem_mem_RAMREG_51_G[3]_s0/CE |
+R13C39[0][A] |
+core0/reg_wb_data_21_s0/D |
Data Required Path:
@@ -11091,7 +10857,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -11101,8 +10867,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R40C21[0][B] |
-mem0/mem_mem_RAMREG_51_G[3]_s0/CLK |
+R13C39[0][A] |
+core0/reg_wb_data_21_s0/CLK |
10.891 |
@@ -11110,8 +10876,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R40C21[0][B] |
-mem0/mem_mem_RAMREG_51_G[3]_s0 |
+R13C39[0][A] |
+core0/reg_wb_data_21_s0 |
Path Statistics:
@@ -11126,7 +10892,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+7 |
Arrival Clock Path Delay |
@@ -11134,7 +10900,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.175, 36.375%; route: 8.820, 61.994%; tC2Q: 0.232, 1.631% |
+cell: 2.635, 38.370%; route: 1.972, 28.719%; tC2Q: 2.260, 32.912% |
Required Clock Path Delay |
@@ -11146,11 +10912,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.258 |
+3.190 |
Data Arrival Time |
-15.149 |
+7.701 |
Data Required Time |
@@ -11158,11 +10924,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_51_G[5]_s0 |
+core0/reg_wb_data_30_s0 |
Launch Clk |
@@ -11216,7 +10982,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -11225,549 +10991,603 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-7.786 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-7.822 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-7.822 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-7.857 |
+6.081 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
+R12C38[0][B] |
+core0/n167_s/COUT |
-7.857 |
+6.081 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
+R12C38[1][A] |
+core0/n166_s/CIN |
-7.892 |
+6.116 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
+R12C38[1][A] |
+core0/n166_s/COUT |
-7.892 |
+6.116 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
+R12C38[1][B] |
+core0/n165_s/CIN |
-7.927 |
+6.151 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
+R12C38[1][B] |
+core0/n165_s/COUT |
-7.927 |
+6.151 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
+R12C38[2][A] |
+core0/n164_s/CIN |
-7.962 |
+6.187 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
+R12C38[2][A] |
+core0/n164_s/COUT |
-7.962 |
+6.187 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
+R12C38[2][B] |
+core0/n163_s/CIN |
-7.998 |
+6.222 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
+R12C38[2][B] |
+core0/n163_s/COUT |
-7.998 |
+6.222 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
+R12C39[0][A] |
+core0/n162_s/CIN |
-8.033 |
+6.257 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
+R12C39[0][A] |
+core0/n162_s/COUT |
-8.033 |
+6.257 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
+R12C39[0][B] |
+core0/n161_s/CIN |
-8.068 |
+6.292 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
+R12C39[0][B] |
+core0/n161_s/COUT |
-8.068 |
+6.292 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
+R12C39[1][A] |
+core0/n160_s/CIN |
-8.103 |
+6.327 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
+R12C39[1][A] |
+core0/n160_s/COUT |
-8.103 |
+6.327 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
+R12C39[1][B] |
+core0/n159_s/CIN |
-8.138 |
+6.363 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
+R12C39[1][B] |
+core0/n159_s/COUT |
-8.138 |
+6.363 |
0.000 |
tNET |
FF |
2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
+R12C39[2][A] |
+core0/n158_s/CIN |
-8.174 |
+6.398 |
0.035 |
tINS |
FF |
1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
+R12C39[2][A] |
+core0/n158_s/COUT |
-8.174 |
+6.398 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
+R12C39[2][B] |
+core0/n157_s/CIN |
-8.209 |
+6.433 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
+R12C39[2][B] |
+core0/n157_s/COUT |
-8.209 |
+6.433 |
0.000 |
tNET |
FF |
2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
+R12C40[0][A] |
+core0/n156_s/CIN |
-8.244 |
+6.468 |
0.035 |
tINS |
FF |
1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
+R12C40[0][A] |
+core0/n156_s/COUT |
-8.244 |
+6.468 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
+R12C40[0][B] |
+core0/n155_s/CIN |
-8.279 |
+6.503 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
+R12C40[0][B] |
+core0/n155_s/COUT |
-8.279 |
+6.503 |
0.000 |
tNET |
FF |
2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
+R12C40[1][A] |
+core0/n154_s/CIN |
-8.314 |
+6.539 |
0.035 |
tINS |
FF |
1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
+R12C40[1][A] |
+core0/n154_s/COUT |
-8.314 |
+6.539 |
0.000 |
tNET |
FF |
2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
+R12C40[1][B] |
+core0/n153_s/CIN |
-8.350 |
+6.574 |
0.035 |
tINS |
FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
-10.425 |
-2.075 |
+6.574 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
+
+
+6.609 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][A] |
+core0/n152_s/COUT |
+
+
+6.609 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][B] |
+core0/n151_s/CIN |
+
+
+6.644 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[2][B] |
+core0/n151_s/COUT |
+
+
+6.644 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][A] |
+core0/n150_s/CIN |
+
+
+6.679 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][A] |
+core0/n150_s/COUT |
+
+
+6.679 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[0][B] |
+core0/n149_s/CIN |
+
+
+6.715 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[0][B] |
+core0/n149_s/COUT |
+
+
+6.715 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][A] |
+core0/n148_s/CIN |
+
+
+6.750 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[1][A] |
+core0/n148_s/COUT |
+
+
+6.750 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[1][B] |
+core0/n147_s/CIN |
+
+
+6.785 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[1][B] |
+core0/n147_s/COUT |
+
+
+6.785 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[2][A] |
+core0/n146_s/CIN |
+
+
+6.820 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[2][A] |
+core0/n146_s/COUT |
+
+
+6.820 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C41[2][B] |
+core0/n145_s/CIN |
+
+
+6.855 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C41[2][B] |
+core0/n145_s/COUT |
+
+
+6.855 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C42[0][A] |
+core0/n144_s/CIN |
+
+
+7.325 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C42[0][A] |
+core0/n144_s/SUM |
+
+
+7.330 |
+0.004 |
tNET |
FF |
1 |
-R15C23[0][A] |
-mem0/mem_s6068/I1 |
+R12C42[1][B] |
+core0/n214_s0/I0 |
-10.796 |
+7.701 |
0.371 |
tINS |
FF |
-11 |
-R15C23[0][A] |
-mem0/mem_s6068/F |
+1 |
+R12C42[1][B] |
+core0/n214_s0/F |
-11.918 |
-1.121 |
+7.701 |
+0.000 |
tNET |
FF |
1 |
-R27C21[1][B] |
-mem0/mem_s5725/I2 |
-
-
-12.289 |
-0.371 |
-tINS |
-FF |
-9 |
-R27C21[1][B] |
-mem0/mem_s5725/F |
-
-
-13.538 |
-1.250 |
-tNET |
-FF |
-1 |
-R39C27[3][A] |
-mem0/mem_s5974/I2 |
-
-
-14.108 |
-0.570 |
-tINS |
-FR |
-1 |
-R39C27[3][A] |
-mem0/mem_s5974/F |
-
-
-14.110 |
-0.001 |
-tNET |
-RR |
-1 |
-R39C27[2][B] |
-mem0/mem_s5019/I3 |
-
-
-14.572 |
-0.462 |
-tINS |
-RR |
-8 |
-R39C27[2][B] |
-mem0/mem_s5019/F |
-
-
-15.149 |
-0.577 |
-tNET |
-RR |
-1 |
-R38C21[0][A] |
-mem0/mem_mem_RAMREG_51_G[5]_s0/CE |
+R12C42[1][B] |
+core0/reg_wb_data_30_s0/D |
Data Required Path:
@@ -11813,7 +11633,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -11823,8 +11643,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R38C21[0][A] |
-mem0/mem_mem_RAMREG_51_G[5]_s0/CLK |
+R12C42[1][B] |
+core0/reg_wb_data_30_s0/CLK |
10.891 |
@@ -11832,8 +11652,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R38C21[0][A] |
-mem0/mem_mem_RAMREG_51_G[5]_s0 |
+R12C42[1][B] |
+core0/reg_wb_data_30_s0 |
Path Statistics:
@@ -11848,7 +11668,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+8 |
Arrival Clock Path Delay |
@@ -11856,7 +11676,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.175, 36.385%; route: 8.816, 61.984%; tC2Q: 0.232, 1.631% |
+cell: 2.952, 43.567%; route: 1.563, 23.075%; tC2Q: 2.260, 33.358% |
Required Clock Path Delay |
@@ -11868,11 +11688,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.254 |
+3.218 |
Data Arrival Time |
-15.145 |
+7.673 |
Data Required Time |
@@ -11880,11 +11700,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_22_G[0]_s0 |
+core0/reg_wb_data_15_s0 |
Launch Clk |
@@ -11938,7 +11758,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -11947,297 +11767,333 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.391 |
-1.510 |
-tNET |
-FF |
-1 |
-R40C15[0][B] |
-mem0/n65_s4/I0 |
-
-
-4.946 |
-0.555 |
-tINS |
-FF |
-26 |
-R40C15[0][B] |
-mem0/n65_s4/F |
-
-
-5.412 |
-0.466 |
-tNET |
-FF |
-1 |
-R38C14[3][B] |
-mem0/n54_s4/I1 |
-
-
-5.929 |
-0.517 |
-tINS |
-FF |
-8 |
-R38C14[3][B] |
-mem0/n54_s4/F |
-
-
-6.383 |
-0.454 |
-tNET |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/I1 |
-
-
-6.938 |
-0.555 |
-tINS |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/F |
-
-
-7.335 |
-0.397 |
+5.300 |
+0.660 |
tNET |
FF |
2 |
-R36C14[1][A] |
-mem0/n52_s3/I1 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-7.905 |
+5.870 |
0.570 |
tINS |
FR |
1 |
-R36C14[1][A] |
-mem0/n52_s3/COUT |
+R12C37[0][B] |
+core0/n173_s/COUT |
-7.905 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R36C14[1][B] |
-mem0/n51_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.940 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R36C14[1][B] |
-mem0/n51_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.940 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][A] |
-mem0/n50_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.976 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][A] |
-mem0/n50_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.976 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][B] |
-mem0/n49_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-8.011 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][B] |
-mem0/n49_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-8.011 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][A] |
-mem0/n48_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-8.046 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][A] |
-mem0/n48_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-8.046 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][B] |
-mem0/n47_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-8.081 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][B] |
-mem0/n47_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-8.081 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R36C15[1][A] |
-mem0/n46_s2/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-8.116 |
+6.081 |
0.035 |
tINS |
FF |
-44 |
-R36C15[1][A] |
-mem0/n46_s2/COUT |
+1 |
+R12C38[0][B] |
+core0/n167_s/COUT |
-10.584 |
-2.467 |
+6.081 |
+0.000 |
tNET |
FF |
-1 |
-R13C36[3][A] |
-mem0/mem_s6339/I1 |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
-11.139 |
-0.555 |
+6.116 |
+0.035 |
tINS |
FF |
-64 |
-R13C36[3][A] |
-mem0/mem_s6339/F |
+1 |
+R12C38[1][A] |
+core0/n166_s/COUT |
-12.794 |
-1.656 |
+6.116 |
+0.000 |
tNET |
FF |
-1 |
-R18C24[2][B] |
-mem0/mem_s6071/I2 |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
-13.165 |
-0.371 |
+6.151 |
+0.035 |
tINS |
FF |
-9 |
-R18C24[2][B] |
-mem0/mem_s6071/F |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
-13.874 |
-0.709 |
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.292 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/COUT |
+
+
+6.292 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][A] |
+core0/n160_s/CIN |
+
+
+6.327 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][A] |
+core0/n160_s/COUT |
+
+
+6.327 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][B] |
+core0/n159_s/CIN |
+
+
+6.797 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C39[1][B] |
+core0/n159_s/SUM |
+
+
+7.211 |
+0.413 |
tNET |
FF |
1 |
-R14C21[3][B] |
-mem0/mem_s5366/I2 |
+R13C40[0][A] |
+core0/n229_s0/I0 |
-14.423 |
-0.549 |
+7.673 |
+0.462 |
tINS |
FR |
1 |
-R14C21[3][B] |
-mem0/mem_s5366/F |
+R13C40[0][A] |
+core0/n229_s0/F |
-14.596 |
-0.172 |
-tNET |
-RR |
-1 |
-R14C20[0][A] |
-mem0/mem_s4632/I0 |
-
-
-15.145 |
-0.549 |
-tINS |
-RR |
-1 |
-R14C20[0][A] |
-mem0/mem_s4632/F |
-
-
-15.145 |
+7.673 |
0.000 |
tNET |
RR |
1 |
-R14C20[0][A] |
-mem0/mem_mem_RAMREG_22_G[0]_s0/D |
+R13C40[0][A] |
+core0/reg_wb_data_15_s0/D |
Data Required Path:
@@ -12283,7 +12139,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -12293,8 +12149,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R14C20[0][A] |
-mem0/mem_mem_RAMREG_22_G[0]_s0/CLK |
+R13C40[0][A] |
+core0/reg_wb_data_15_s0/CLK |
10.891 |
@@ -12302,8 +12158,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R14C20[0][A] |
-mem0/mem_mem_RAMREG_22_G[0]_s0 |
+R13C40[0][A] |
+core0/reg_wb_data_15_s0 |
Path Statistics:
@@ -12318,7 +12174,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-12 |
+6 |
Arrival Clock Path Delay |
@@ -12326,7 +12182,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 4.987, 35.075%; route: 9.000, 63.293%; tC2Q: 0.232, 1.632% |
+cell: 2.515, 37.272%; route: 1.972, 29.230%; tC2Q: 2.260, 33.498% |
Required Clock Path Delay |
@@ -12338,11 +12194,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.249 |
+3.306 |
Data Arrival Time |
-15.140 |
+7.585 |
Data Required Time |
@@ -12350,11 +12206,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_40_G[7]_s0 |
+core0/reg_wb_data_22_s0 |
Launch Clk |
@@ -12408,7 +12264,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -12417,297 +12273,459 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.391 |
-1.510 |
-tNET |
-FF |
-1 |
-R40C15[0][B] |
-mem0/n65_s4/I0 |
-
-
-4.946 |
-0.555 |
-tINS |
-FF |
-26 |
-R40C15[0][B] |
-mem0/n65_s4/F |
-
-
-5.412 |
-0.466 |
-tNET |
-FF |
-1 |
-R38C14[3][B] |
-mem0/n54_s4/I1 |
-
-
-5.929 |
-0.517 |
-tINS |
-FF |
-8 |
-R38C14[3][B] |
-mem0/n54_s4/F |
-
-
-6.383 |
-0.454 |
-tNET |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/I1 |
-
-
-6.938 |
-0.555 |
-tINS |
-FF |
-1 |
-R36C15[3][A] |
-mem0/n53_s4/F |
-
-
-7.335 |
-0.397 |
+5.300 |
+0.660 |
tNET |
FF |
2 |
-R36C14[1][A] |
-mem0/n52_s3/I1 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-7.905 |
+5.870 |
0.570 |
tINS |
FR |
1 |
-R36C14[1][A] |
-mem0/n52_s3/COUT |
+R12C37[0][B] |
+core0/n173_s/COUT |
-7.905 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R36C14[1][B] |
-mem0/n51_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.940 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R36C14[1][B] |
-mem0/n51_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.940 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][A] |
-mem0/n50_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.976 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][A] |
-mem0/n50_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.976 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R36C14[2][B] |
-mem0/n49_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-8.011 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R36C14[2][B] |
-mem0/n49_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-8.011 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][A] |
-mem0/n48_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-8.046 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][A] |
-mem0/n48_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-8.046 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R36C15[0][B] |
-mem0/n47_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-8.081 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R36C15[0][B] |
-mem0/n47_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-8.081 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R36C15[1][A] |
-mem0/n46_s2/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-8.116 |
+6.081 |
0.035 |
tINS |
FF |
-44 |
-R36C15[1][A] |
-mem0/n46_s2/COUT |
-
-
-9.852 |
-1.736 |
-tNET |
-FF |
1 |
-R13C17[0][A] |
-mem0/mem_s6342/I0 |
+R12C38[0][B] |
+core0/n167_s/COUT |
-10.369 |
-0.517 |
-tINS |
-FF |
-80 |
-R13C17[0][A] |
-mem0/mem_s6342/F |
-
-
-12.492 |
-2.122 |
-tNET |
-FF |
-1 |
-R34C38[1][A] |
-mem0/mem_s6173/I3 |
-
-
-13.047 |
-0.555 |
-tINS |
-FF |
-9 |
-R34C38[1][A] |
-mem0/mem_s6173/F |
-
-
-13.482 |
-0.435 |
-tNET |
-FF |
-1 |
-R34C41[0][B] |
-mem0/mem_s5608/I2 |
-
-
-13.935 |
-0.453 |
-tINS |
-FF |
-1 |
-R34C41[0][B] |
-mem0/mem_s5608/F |
-
-
-14.591 |
-0.656 |
-tNET |
-FF |
-1 |
-R31C39[0][A] |
-mem0/mem_s4783/I0 |
-
-
-15.140 |
-0.549 |
-tINS |
-FR |
-1 |
-R31C39[0][A] |
-mem0/mem_s4783/F |
-
-
-15.140 |
+6.081 |
0.000 |
tNET |
-RR |
+FF |
+2 |
+R12C38[1][A] |
+core0/n166_s/CIN |
+
+
+6.116 |
+0.035 |
+tINS |
+FF |
1 |
-R31C39[0][A] |
-mem0/mem_mem_RAMREG_40_G[7]_s0/D |
+R12C38[1][A] |
+core0/n166_s/COUT |
+
+
+6.116 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[1][B] |
+core0/n165_s/CIN |
+
+
+6.151 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[1][B] |
+core0/n165_s/COUT |
+
+
+6.151 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][A] |
+core0/n164_s/CIN |
+
+
+6.187 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][A] |
+core0/n164_s/COUT |
+
+
+6.187 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C38[2][B] |
+core0/n163_s/CIN |
+
+
+6.222 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C38[2][B] |
+core0/n163_s/COUT |
+
+
+6.222 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][A] |
+core0/n162_s/CIN |
+
+
+6.257 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][A] |
+core0/n162_s/COUT |
+
+
+6.257 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[0][B] |
+core0/n161_s/CIN |
+
+
+6.292 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[0][B] |
+core0/n161_s/COUT |
+
+
+6.292 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][A] |
+core0/n160_s/CIN |
+
+
+6.327 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][A] |
+core0/n160_s/COUT |
+
+
+6.327 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[1][B] |
+core0/n159_s/CIN |
+
+
+6.363 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[1][B] |
+core0/n159_s/COUT |
+
+
+6.363 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][A] |
+core0/n158_s/CIN |
+
+
+6.398 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][A] |
+core0/n158_s/COUT |
+
+
+6.398 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C39[2][B] |
+core0/n157_s/CIN |
+
+
+6.433 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C39[2][B] |
+core0/n157_s/COUT |
+
+
+6.433 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][A] |
+core0/n156_s/CIN |
+
+
+6.468 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][A] |
+core0/n156_s/COUT |
+
+
+6.468 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[0][B] |
+core0/n155_s/CIN |
+
+
+6.503 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[0][B] |
+core0/n155_s/COUT |
+
+
+6.503 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][A] |
+core0/n154_s/CIN |
+
+
+6.539 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][A] |
+core0/n154_s/COUT |
+
+
+6.539 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[1][B] |
+core0/n153_s/CIN |
+
+
+6.574 |
+0.035 |
+tINS |
+FF |
+1 |
+R12C40[1][B] |
+core0/n153_s/COUT |
+
+
+6.574 |
+0.000 |
+tNET |
+FF |
+2 |
+R12C40[2][A] |
+core0/n152_s/CIN |
+
+
+7.044 |
+0.470 |
+tINS |
+FF |
+1 |
+R12C40[2][A] |
+core0/n152_s/SUM |
+
+
+7.214 |
+0.170 |
+tNET |
+FF |
+1 |
+R13C40[0][B] |
+core0/n222_s0/I0 |
+
+
+7.585 |
+0.371 |
+tINS |
+FF |
+1 |
+R13C40[0][B] |
+core0/n222_s0/F |
+
+
+7.585 |
+0.000 |
+tNET |
+FF |
+1 |
+R13C40[0][B] |
+core0/reg_wb_data_22_s0/D |
Data Required Path:
@@ -12753,7 +12771,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -12763,8 +12781,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R31C39[0][A] |
-mem0/mem_mem_RAMREG_40_G[7]_s0/CLK |
+R13C40[0][B] |
+core0/reg_wb_data_22_s0/CLK |
10.891 |
@@ -12772,8 +12790,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R31C39[0][A] |
-mem0/mem_mem_RAMREG_40_G[7]_s0 |
+R13C40[0][B] |
+core0/reg_wb_data_22_s0 |
Path Statistics:
@@ -12788,7 +12806,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-12 |
+7 |
Arrival Clock Path Delay |
@@ -12796,7 +12814,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.037, 35.438%; route: 8.945, 62.930%; tC2Q: 0.232, 1.632% |
+cell: 2.670, 40.094%; route: 1.729, 25.969%; tC2Q: 2.260, 33.937% |
Required Clock Path Delay |
@@ -12808,11 +12826,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.226 |
+3.345 |
Data Arrival Time |
-15.117 |
+7.546 |
Data Required Time |
@@ -12820,11 +12838,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_13_G[5]_s0 |
+core0/reg_wb_data_14_s0 |
Launch Clk |
@@ -12878,7 +12896,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -12887,549 +12905,315 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
+6.011 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
+R12C37[2][B] |
+core0/n169_s/COUT |
-7.786 |
+6.011 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C38[0][A] |
+core0/n168_s/CIN |
-7.822 |
+6.046 |
0.035 |
tINS |
FF |
1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
+R12C38[0][A] |
+core0/n168_s/COUT |
-7.822 |
+6.046 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
+R12C38[0][B] |
+core0/n167_s/CIN |
-7.857 |
+6.081 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
+R12C38[0][B] |
+core0/n167_s/COUT |
-7.857 |
+6.081 |
0.000 |
tNET |
FF |
2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
+R12C38[1][A] |
+core0/n166_s/CIN |
-7.892 |
+6.116 |
0.035 |
tINS |
FF |
1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
+R12C38[1][A] |
+core0/n166_s/COUT |
-7.892 |
+6.116 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
+R12C38[1][B] |
+core0/n165_s/CIN |
-7.927 |
+6.151 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
+R12C38[1][B] |
+core0/n165_s/COUT |
-7.927 |
+6.151 |
0.000 |
tNET |
FF |
2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
+R12C38[2][A] |
+core0/n164_s/CIN |
-7.962 |
+6.187 |
0.035 |
tINS |
FF |
1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
+R12C38[2][A] |
+core0/n164_s/COUT |
-7.962 |
+6.187 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
+R12C38[2][B] |
+core0/n163_s/CIN |
-7.998 |
+6.222 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
+R12C38[2][B] |
+core0/n163_s/COUT |
-7.998 |
+6.222 |
0.000 |
tNET |
FF |
2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
+R12C39[0][A] |
+core0/n162_s/CIN |
-8.033 |
+6.257 |
0.035 |
tINS |
FF |
1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
+R12C39[0][A] |
+core0/n162_s/COUT |
-8.033 |
+6.257 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
+R12C39[0][B] |
+core0/n161_s/CIN |
-8.068 |
+6.292 |
0.035 |
tINS |
FF |
1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
+R12C39[0][B] |
+core0/n161_s/COUT |
-8.068 |
+6.292 |
0.000 |
tNET |
FF |
2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
+R12C39[1][A] |
+core0/n160_s/CIN |
-8.103 |
-0.035 |
+6.762 |
+0.470 |
tINS |
FF |
1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
+R12C39[1][A] |
+core0/n160_s/SUM |
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
+7.175 |
+0.413 |
tNET |
FF |
1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
+R15C39[0][B] |
+core0/n230_s0/I0 |
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-12.251 |
-1.722 |
-tNET |
-FF |
-1 |
-R32C35[1][A] |
-mem0/mem_s5246/I0 |
-
-
-12.622 |
-0.371 |
-tINS |
-FF |
-9 |
-R32C35[1][A] |
-mem0/mem_s5246/F |
-
-
-13.835 |
-1.212 |
-tNET |
-FF |
-1 |
-R39C40[1][A] |
-mem0/mem_s5920/I3 |
-
-
-14.206 |
+7.546 |
0.371 |
tINS |
FF |
1 |
-R39C40[1][A] |
-mem0/mem_s5920/F |
+R15C39[0][B] |
+core0/n230_s0/F |
-14.210 |
-0.004 |
+7.546 |
+0.000 |
tNET |
FF |
1 |
-R39C40[0][B] |
-mem0/mem_s4981/I3 |
-
-
-14.537 |
-0.327 |
-tINS |
-FR |
-8 |
-R39C40[0][B] |
-mem0/mem_s4981/F |
-
-
-15.117 |
-0.580 |
-tNET |
-RR |
-1 |
-R30C41[2][B] |
-mem0/mem_mem_RAMREG_13_G[5]_s0/CE |
+R15C39[0][B] |
+core0/reg_wb_data_14_s0/D |
Data Required Path:
@@ -13475,7 +13259,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -13485,8 +13269,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R30C41[2][B] |
-mem0/mem_mem_RAMREG_13_G[5]_s0/CLK |
+R15C39[0][B] |
+core0/reg_wb_data_14_s0/CLK |
10.891 |
@@ -13494,8 +13278,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R30C41[2][B] |
-mem0/mem_mem_RAMREG_13_G[5]_s0 |
+R15C39[0][B] |
+core0/reg_wb_data_14_s0 |
Path Statistics:
@@ -13510,7 +13294,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+6 |
Arrival Clock Path Delay |
@@ -13518,7 +13302,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 4.923, 34.692%; route: 9.036, 63.673%; tC2Q: 0.232, 1.635% |
+cell: 2.388, 36.076%; route: 1.972, 29.787%; tC2Q: 2.260, 34.137% |
Required Clock Path Delay |
@@ -13530,11 +13314,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.226 |
+3.370 |
Data Arrival Time |
-15.117 |
+7.521 |
Data Required Time |
@@ -13542,11 +13326,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/rs1_3_s2 |
To |
-mem0/mem_mem_RAMREG_13_G[3]_s0 |
+core0/alu_out_3_s1 |
Launch Clk |
@@ -13600,7 +13384,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -13610,548 +13394,188 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+R11C43[1][A] |
+core0/rs1_3_s2/CLK |
1.158 |
0.232 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+3 |
+R11C43[1][A] |
+core0/rs1_3_s2/Q |
-2.326 |
-1.168 |
+1.819 |
+0.661 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R14C41[3][A] |
+core0/register_rs1_data[0]_DOAL_G_0_s4/I0 |
-2.881 |
-0.555 |
-tINS |
-FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
-
-
-4.580 |
-1.699 |
-tNET |
-FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
-
-
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
+2.368 |
0.549 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
+1 |
+R14C41[3][A] |
+core0/register_rs1_data[0]_DOAL_G_0_s4/F |
-6.333 |
-0.178 |
+2.370 |
+0.001 |
tNET |
RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R14C41[0][B] |
+core0/register_rs1_data[0]_DOAL_G_0_s3/I2 |
-6.903 |
-0.570 |
+2.832 |
+0.462 |
tINS |
RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
+R14C41[0][B] |
+core0/register_rs1_data[0]_DOAL_G_0_s3/F |
-7.076 |
+3.004 |
0.172 |
tNET |
RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
+1 |
+R14C42[2][B] |
+core0/register_rs1_data[0]_DOAL_G_0_s1/I3 |
-7.646 |
+3.375 |
+0.371 |
+tINS |
+RF |
+32 |
+R14C42[2][B] |
+core0/register_rs1_data[0]_DOAL_G_0_s1/F |
+
+
+4.093 |
+0.717 |
+tNET |
+FF |
+1 |
+R13C39[3][B] |
+core0/register_rs1_data[0]_DOAL_G_0_s0/I2 |
+
+
+4.546 |
+0.453 |
+tINS |
+FF |
+2 |
+R13C39[3][B] |
+core0/register_rs1_data[0]_DOAL_G_0_s0/F |
+
+
+4.963 |
+0.418 |
+tNET |
+FF |
+2 |
+R13C41[0][A] |
+core0/n105_s/I0 |
+
+
+5.533 |
0.570 |
tINS |
-RR |
+FR |
1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
+R13C41[0][A] |
+core0/n105_s/COUT |
-7.646 |
+5.533 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R13C41[0][B] |
+core0/n104_s/CIN |
-7.681 |
+5.568 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R13C41[0][B] |
+core0/n104_s/COUT |
-7.681 |
+5.568 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R13C41[1][A] |
+core0/n103_s/CIN |
-7.716 |
+5.603 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R13C41[1][A] |
+core0/n103_s/COUT |
-7.716 |
+5.603 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R13C41[1][B] |
+core0/n102_s/CIN |
-7.751 |
-0.035 |
+6.073 |
+0.470 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R13C41[1][B] |
+core0/n102_s/SUM |
-7.751 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
-
-
-7.786 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
-
-
-7.786 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
-
-
-7.822 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
-
-
-7.822 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
-
-
-7.857 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
-
-
-7.857 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
-
-
-7.892 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
-
-
-7.892 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
-
-
-7.927 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
-
-
-7.927 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
-
-
-7.962 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
-
-
-7.962 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
-
-
-7.998 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
-
-
-7.998 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
-
-
-8.033 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
-
-
-8.033 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
-
-
-8.068 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
-
-
-8.068 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
-
-
-8.103 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
-
-
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
+6.972 |
+0.899 |
tNET |
FF |
1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
+R12C43[1][A] |
+core0/n203_s2/I1 |
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-12.251 |
-1.722 |
-tNET |
-FF |
-1 |
-R32C35[1][A] |
-mem0/mem_s5246/I0 |
-
-
-12.622 |
-0.371 |
-tINS |
-FF |
-9 |
-R32C35[1][A] |
-mem0/mem_s5246/F |
-
-
-13.835 |
-1.212 |
-tNET |
-FF |
-1 |
-R39C40[1][A] |
-mem0/mem_s5920/I3 |
-
-
-14.206 |
-0.371 |
-tINS |
-FF |
-1 |
-R39C40[1][A] |
-mem0/mem_s5920/F |
-
-
-14.210 |
-0.004 |
-tNET |
-FF |
-1 |
-R39C40[0][B] |
-mem0/mem_s4981/I3 |
-
-
-14.537 |
-0.327 |
+7.521 |
+0.549 |
tINS |
FR |
-8 |
-R39C40[0][B] |
-mem0/mem_s4981/F |
+1 |
+R12C43[1][A] |
+core0/n203_s2/F |
-15.117 |
-0.580 |
+7.521 |
+0.000 |
tNET |
RR |
1 |
-R30C41[1][B] |
-mem0/mem_mem_RAMREG_13_G[3]_s0/CE |
+R12C43[1][A] |
+core0/alu_out_3_s1/D |
Data Required Path:
@@ -14197,7 +13621,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -14207,8 +13631,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R30C41[1][B] |
-mem0/mem_mem_RAMREG_13_G[3]_s0/CLK |
+R12C43[1][A] |
+core0/alu_out_3_s1/CLK |
10.891 |
@@ -14216,8 +13640,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R30C41[1][B] |
-mem0/mem_mem_RAMREG_13_G[3]_s0 |
+R12C43[1][A] |
+core0/alu_out_3_s1 |
Path Statistics:
@@ -14232,7 +13656,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+8 |
Arrival Clock Path Delay |
@@ -14240,7 +13664,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 4.923, 34.692%; route: 9.036, 63.673%; tC2Q: 0.232, 1.635% |
+cell: 3.494, 52.984%; route: 2.869, 43.499%; tC2Q: 0.232, 3.518% |
Required Clock Path Delay |
@@ -14252,11 +13676,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.226 |
+3.374 |
Data Arrival Time |
-15.117 |
+7.517 |
Data Required Time |
@@ -14264,11 +13688,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_13_G[0]_s0 |
+core0/alu_out_5_s1 |
Launch Clk |
@@ -14322,7 +13746,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -14331,549 +13755,153 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
+5.975 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
+R12C37[2][A] |
+core0/n170_s/COUT |
-7.751 |
+5.975 |
0.000 |
tNET |
FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/CIN |
-7.786 |
-0.035 |
+6.445 |
+0.470 |
tINS |
FF |
-1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
-
-
-7.786 |
-0.000 |
-tNET |
-FF |
2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
+R12C37[2][B] |
+core0/n169_s/SUM |
-7.822 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
-
-
-7.822 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
-
-
-7.857 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
-
-
-7.857 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
-
-
-7.892 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
-
-
-7.892 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
-
-
-7.927 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
-
-
-7.927 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
-
-
-7.962 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
-
-
-7.962 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
-
-
-7.998 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
-
-
-7.998 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
-
-
-8.033 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
-
-
-8.033 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
-
-
-8.068 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
-
-
-8.068 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
-
-
-8.103 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
-
-
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
+6.968 |
+0.522 |
tNET |
FF |
1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
+R12C43[2][A] |
+core0/n201_s2/I0 |
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-12.251 |
-1.722 |
-tNET |
-FF |
-1 |
-R32C35[1][A] |
-mem0/mem_s5246/I0 |
-
-
-12.622 |
-0.371 |
-tINS |
-FF |
-9 |
-R32C35[1][A] |
-mem0/mem_s5246/F |
-
-
-13.835 |
-1.212 |
-tNET |
-FF |
-1 |
-R39C40[1][A] |
-mem0/mem_s5920/I3 |
-
-
-14.206 |
-0.371 |
-tINS |
-FF |
-1 |
-R39C40[1][A] |
-mem0/mem_s5920/F |
-
-
-14.210 |
-0.004 |
-tNET |
-FF |
-1 |
-R39C40[0][B] |
-mem0/mem_s4981/I3 |
-
-
-14.537 |
-0.327 |
+7.517 |
+0.549 |
tINS |
FR |
-8 |
-R39C40[0][B] |
-mem0/mem_s4981/F |
+1 |
+R12C43[2][A] |
+core0/n201_s2/F |
-15.117 |
-0.580 |
+7.517 |
+0.000 |
tNET |
RR |
1 |
-R30C41[1][A] |
-mem0/mem_mem_RAMREG_13_G[0]_s0/CE |
+R12C43[2][A] |
+core0/alu_out_5_s1/D |
Data Required Path:
@@ -14919,7 +13947,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -14929,8 +13957,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R30C41[1][A] |
-mem0/mem_mem_RAMREG_13_G[0]_s0/CLK |
+R12C43[2][A] |
+core0/alu_out_5_s1/CLK |
10.891 |
@@ -14938,8 +13966,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R30C41[1][A] |
-mem0/mem_mem_RAMREG_13_G[0]_s0 |
+R12C43[2][A] |
+core0/alu_out_5_s1 |
Path Statistics:
@@ -14954,7 +13982,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+5 |
Arrival Clock Path Delay |
@@ -14962,7 +13990,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 4.923, 34.692%; route: 9.036, 63.673%; tC2Q: 0.232, 1.635% |
+cell: 2.250, 34.132%; route: 2.081, 31.578%; tC2Q: 2.260, 34.290% |
Required Clock Path Delay |
@@ -14974,11 +14002,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.204 |
+3.390 |
Data Arrival Time |
-15.095 |
+7.501 |
Data Required Time |
@@ -14986,11 +14014,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_15_G[4]_s0 |
+core0/alu_out_2_s1 |
Launch Clk |
@@ -15044,7 +14072,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -15053,549 +14081,99 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
+5.870 |
+0.570 |
tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
+FR |
+1 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-5.606 |
-0.573 |
+5.870 |
+0.000 |
+tNET |
+RR |
+2 |
+R12C37[1][A] |
+core0/n172_s/CIN |
+
+
+6.340 |
+0.470 |
+tINS |
+RF |
+2 |
+R12C37[1][A] |
+core0/n172_s/SUM |
+
+
+6.952 |
+0.612 |
tNET |
FF |
1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
+R12C43[0][B] |
+core0/n204_s2/I0 |
-6.155 |
+7.501 |
0.549 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C43[0][B] |
+core0/n204_s2/F |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+7.501 |
0.000 |
tNET |
RR |
-2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
-
-
-7.681 |
-0.035 |
-tINS |
-RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
-
-
-7.681 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
-
-
-7.716 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
-
-
-7.716 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
-
-
-7.751 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
-
-
-7.751 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
-
-
-7.786 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
-
-
-7.786 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
-
-
-7.822 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
-
-
-7.822 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
-
-
-7.857 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
-
-
-7.857 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
-
-
-7.892 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
-
-
-7.892 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
-
-
-7.927 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
-
-
-7.927 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
-
-
-7.962 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
-
-
-7.962 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
-
-
-7.998 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
-
-
-7.998 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
-
-
-8.033 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
-
-
-8.033 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
-
-
-8.068 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
-
-
-8.068 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
-
-
-8.103 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
-
-
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
-tNET |
-FF |
-1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
-
-
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-12.531 |
-2.002 |
-tNET |
-FF |
-1 |
-R38C35[0][B] |
-mem0/mem_s5264/I0 |
-
-
-13.086 |
-0.555 |
-tINS |
-FF |
-9 |
-R38C35[0][B] |
-mem0/mem_s5264/F |
-
-
-13.623 |
-0.537 |
-tNET |
-FF |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/I3 |
-
-
-14.193 |
-0.570 |
-tINS |
-FR |
-1 |
-R36C39[0][B] |
-mem0/mem_s5923/F |
-
-
-14.195 |
-0.001 |
-tNET |
-RR |
-1 |
-R36C39[3][A] |
-mem0/mem_s4983/I3 |
-
-
-14.765 |
-0.570 |
-tINS |
-RR |
-8 |
-R36C39[3][A] |
-mem0/mem_s4983/F |
-
-
-15.095 |
-0.331 |
-tNET |
-RR |
-1 |
-R35C39[2][A] |
-mem0/mem_mem_RAMREG_15_G[4]_s0/CE |
+R12C43[0][B] |
+core0/alu_out_2_s1/D |
Data Required Path:
@@ -15641,7 +14219,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -15651,8 +14229,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R35C39[2][A] |
-mem0/mem_mem_RAMREG_15_G[4]_s0/CLK |
+R12C43[0][B] |
+core0/alu_out_2_s1/CLK |
10.891 |
@@ -15660,8 +14238,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R35C39[2][A] |
-mem0/mem_mem_RAMREG_15_G[4]_s0 |
+R12C43[0][B] |
+core0/alu_out_2_s1 |
Path Statistics:
@@ -15676,7 +14254,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+5 |
Arrival Clock Path Delay |
@@ -15684,7 +14262,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.549, 39.162%; route: 8.388, 59.200%; tC2Q: 0.232, 1.637% |
+cell: 2.144, 32.608%; route: 2.171, 33.021%; tC2Q: 2.260, 34.372% |
Required Clock Path Delay |
@@ -15696,11 +14274,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.198 |
+3.491 |
Data Arrival Time |
-15.089 |
+7.400 |
Data Required Time |
@@ -15708,11 +14286,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_51_G[6]_s0 |
+core0/reg_wb_data_2_s0 |
Launch Clk |
@@ -15766,7 +14344,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -15775,549 +14353,81 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
-0.035 |
+6.340 |
+0.470 |
tINS |
RF |
-1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
-
-
-7.681 |
-0.000 |
-tNET |
-FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/SUM |
-7.716 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
-
-
-7.716 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
-
-
-7.751 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
-
-
-7.751 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
-
-
-7.786 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
-
-
-7.786 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
-
-
-7.822 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
-
-
-7.822 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
-
-
-7.857 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
-
-
-7.857 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
-
-
-7.892 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
-
-
-7.892 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
-
-
-7.927 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
-
-
-7.927 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
-
-
-7.962 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
-
-
-7.962 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
-
-
-7.998 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
-
-
-7.998 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
-
-
-8.033 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
-
-
-8.033 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
-
-
-8.068 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
-
-
-8.068 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
-
-
-8.103 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
-
-
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.425 |
-2.075 |
+7.400 |
+1.060 |
tNET |
FF |
1 |
-R15C23[0][A] |
-mem0/mem_s6068/I1 |
-
-
-10.796 |
-0.371 |
-tINS |
-FF |
-11 |
-R15C23[0][A] |
-mem0/mem_s6068/F |
-
-
-11.918 |
-1.121 |
-tNET |
-FF |
-1 |
-R27C21[1][B] |
-mem0/mem_s5725/I2 |
-
-
-12.289 |
-0.371 |
-tINS |
-FF |
-9 |
-R27C21[1][B] |
-mem0/mem_s5725/F |
-
-
-13.538 |
-1.250 |
-tNET |
-FF |
-1 |
-R39C27[3][A] |
-mem0/mem_s5974/I2 |
-
-
-14.108 |
-0.570 |
-tINS |
-FR |
-1 |
-R39C27[3][A] |
-mem0/mem_s5974/F |
-
-
-14.110 |
-0.001 |
-tNET |
-RR |
-1 |
-R39C27[2][B] |
-mem0/mem_s5019/I3 |
-
-
-14.572 |
-0.462 |
-tINS |
-RR |
-8 |
-R39C27[2][B] |
-mem0/mem_s5019/F |
-
-
-15.089 |
-0.517 |
-tNET |
-RR |
-1 |
-R38C25[2][A] |
-mem0/mem_mem_RAMREG_51_G[6]_s0/CE |
+R12C42[2][B] |
+core0/reg_wb_data_2_s0/D |
Data Required Path:
@@ -16363,7 +14473,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -16373,8 +14483,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R38C25[2][A] |
-mem0/mem_mem_RAMREG_51_G[6]_s0/CLK |
+R12C42[2][B] |
+core0/reg_wb_data_2_s0/CLK |
10.891 |
@@ -16382,8 +14492,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R38C25[2][A] |
-mem0/mem_mem_RAMREG_51_G[6]_s0 |
+R12C42[2][B] |
+core0/reg_wb_data_2_s0 |
Path Statistics:
@@ -16398,7 +14508,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+4 |
Arrival Clock Path Delay |
@@ -16406,7 +14516,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.175, 36.540%; route: 8.756, 61.822%; tC2Q: 0.232, 1.638% |
+cell: 1.595, 24.638%; route: 2.619, 40.453%; tC2Q: 2.260, 34.910% |
Required Clock Path Delay |
@@ -16418,11 +14528,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
--4.185 |
+3.496 |
Data Arrival Time |
-15.076 |
+7.395 |
Data Required Time |
@@ -16430,11 +14540,11 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
From |
-core0/reg_raddr_4_s0 |
+core0/register_register_0_0_s |
To |
-mem0/mem_mem_RAMREG_24_G[5]_s0 |
+core0/alu_out_4_s1 |
Launch Clk |
@@ -16488,7 +14598,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -16497,549 +14607,135 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.243 |
tNET |
RR |
-1 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/CLK |
+32 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKB |
-1.158 |
-0.232 |
+3.186 |
+2.260 |
tC2Q |
RF |
-190 |
-R32C18[2][A] |
-core0/reg_raddr_4_s0/Q |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DO[1] |
-2.326 |
-1.168 |
+4.084 |
+0.899 |
tNET |
FF |
1 |
-R13C17[1][A] |
-mem0/mem_s5980/I0 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/I1 |
-2.881 |
+4.639 |
0.555 |
tINS |
FF |
-17 |
-R13C17[1][A] |
-mem0/mem_s5980/F |
+2 |
+R13C41[3][B] |
+core0/register_rs1_data[0]_DOAL_G_1_s0/F |
-4.580 |
-1.699 |
+5.300 |
+0.660 |
tNET |
FF |
-1 |
-R40C12[3][B] |
-mem0/n107_s5/I0 |
+2 |
+R12C37[0][B] |
+core0/n173_s/I0 |
-5.033 |
-0.453 |
-tINS |
-FF |
-4 |
-R40C12[3][B] |
-mem0/n107_s5/F |
-
-
-5.606 |
-0.573 |
-tNET |
-FF |
-1 |
-R40C9[0][A] |
-mem0/n104_s5/I0 |
-
-
-6.155 |
-0.549 |
+5.870 |
+0.570 |
tINS |
FR |
-4 |
-R40C9[0][A] |
-mem0/n104_s5/F |
-
-
-6.333 |
-0.178 |
-tNET |
-RR |
1 |
-R41C9[3][B] |
-mem0/n102_s5/I2 |
+R12C37[0][B] |
+core0/n173_s/COUT |
-6.903 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C9[3][B] |
-mem0/n102_s5/F |
-
-
-7.076 |
-0.172 |
-tNET |
-RR |
-2 |
-R41C10[0][A] |
-mem0/n101_s3/I1 |
-
-
-7.646 |
-0.570 |
-tINS |
-RR |
-1 |
-R41C10[0][A] |
-mem0/n101_s3/COUT |
-
-
-7.646 |
+5.870 |
0.000 |
tNET |
RR |
2 |
-R41C10[0][B] |
-mem0/n100_s3/CIN |
+R12C37[1][A] |
+core0/n172_s/CIN |
-7.681 |
+5.905 |
0.035 |
tINS |
RF |
1 |
-R41C10[0][B] |
-mem0/n100_s3/COUT |
+R12C37[1][A] |
+core0/n172_s/COUT |
-7.681 |
+5.905 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][A] |
-mem0/n99_s3/CIN |
+R12C37[1][B] |
+core0/n171_s/CIN |
-7.716 |
+5.940 |
0.035 |
tINS |
FF |
1 |
-R41C10[1][A] |
-mem0/n99_s3/COUT |
+R12C37[1][B] |
+core0/n171_s/COUT |
-7.716 |
+5.940 |
0.000 |
tNET |
FF |
2 |
-R41C10[1][B] |
-mem0/n98_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/CIN |
-7.751 |
-0.035 |
+6.410 |
+0.470 |
tINS |
FF |
-1 |
-R41C10[1][B] |
-mem0/n98_s3/COUT |
-
-
-7.751 |
-0.000 |
-tNET |
-FF |
2 |
-R41C10[2][A] |
-mem0/n97_s3/CIN |
+R12C37[2][A] |
+core0/n170_s/SUM |
-7.786 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][A] |
-mem0/n97_s3/COUT |
-
-
-7.786 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C10[2][B] |
-mem0/n96_s3/CIN |
-
-
-7.822 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C10[2][B] |
-mem0/n96_s3/COUT |
-
-
-7.822 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][A] |
-mem0/n95_s3/CIN |
-
-
-7.857 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][A] |
-mem0/n95_s3/COUT |
-
-
-7.857 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[0][B] |
-mem0/n94_s3/CIN |
-
-
-7.892 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[0][B] |
-mem0/n94_s3/COUT |
-
-
-7.892 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][A] |
-mem0/n93_s3/CIN |
-
-
-7.927 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][A] |
-mem0/n93_s3/COUT |
-
-
-7.927 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[1][B] |
-mem0/n92_s3/CIN |
-
-
-7.962 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[1][B] |
-mem0/n92_s3/COUT |
-
-
-7.962 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][A] |
-mem0/n91_s3/CIN |
-
-
-7.998 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][A] |
-mem0/n91_s3/COUT |
-
-
-7.998 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C11[2][B] |
-mem0/n90_s3/CIN |
-
-
-8.033 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C11[2][B] |
-mem0/n90_s3/COUT |
-
-
-8.033 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][A] |
-mem0/n89_s3/CIN |
-
-
-8.068 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][A] |
-mem0/n89_s3/COUT |
-
-
-8.068 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[0][B] |
-mem0/n88_s3/CIN |
-
-
-8.103 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[0][B] |
-mem0/n88_s3/COUT |
-
-
-8.103 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][A] |
-mem0/n87_s3/CIN |
-
-
-8.138 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][A] |
-mem0/n87_s3/COUT |
-
-
-8.138 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[1][B] |
-mem0/n86_s3/CIN |
-
-
-8.174 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[1][B] |
-mem0/n86_s3/COUT |
-
-
-8.174 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][A] |
-mem0/n85_s3/CIN |
-
-
-8.209 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][A] |
-mem0/n85_s3/COUT |
-
-
-8.209 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C12[2][B] |
-mem0/n84_s3/CIN |
-
-
-8.244 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C12[2][B] |
-mem0/n84_s3/COUT |
-
-
-8.244 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][A] |
-mem0/n83_s3/CIN |
-
-
-8.279 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][A] |
-mem0/n83_s3/COUT |
-
-
-8.279 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[0][B] |
-mem0/n82_s3/CIN |
-
-
-8.314 |
-0.035 |
-tINS |
-FF |
-1 |
-R41C13[0][B] |
-mem0/n82_s3/COUT |
-
-
-8.314 |
-0.000 |
-tNET |
-FF |
-2 |
-R41C13[1][A] |
-mem0/n81_s2/CIN |
-
-
-8.350 |
-0.035 |
-tINS |
-FF |
-16 |
-R41C13[1][A] |
-mem0/n81_s2/COUT |
-
-
-10.077 |
-1.727 |
+6.933 |
+0.522 |
tNET |
FF |
1 |
-R15C14[1][B] |
-mem0/mem_s5990/I0 |
+R12C43[1][B] |
+core0/n202_s2/I0 |
-10.530 |
-0.453 |
-tINS |
-FF |
-24 |
-R15C14[1][B] |
-mem0/mem_s5990/F |
-
-
-11.252 |
-0.722 |
-tNET |
-FF |
-1 |
-R15C24[1][B] |
-mem0/mem_s5401/I0 |
-
-
-11.769 |
-0.517 |
-tINS |
-FF |
-9 |
-R15C24[1][B] |
-mem0/mem_s5401/F |
-
-
-13.705 |
-1.936 |
-tNET |
-FF |
-1 |
-R32C27[3][A] |
-mem0/mem_s5937/I3 |
-
-
-14.275 |
-0.570 |
+7.395 |
+0.462 |
tINS |
FR |
1 |
-R32C27[3][A] |
-mem0/mem_s5937/F |
+R12C43[1][B] |
+core0/n202_s2/F |
-14.276 |
-0.001 |
+7.395 |
+0.000 |
tNET |
RR |
1 |
-R32C27[3][B] |
-mem0/mem_s4992/I2 |
-
-
-14.738 |
-0.462 |
-tINS |
-RR |
-8 |
-R32C27[3][B] |
-mem0/mem_s4992/F |
-
-
-15.076 |
-0.338 |
-tNET |
-RR |
-1 |
-R32C26[2][B] |
-mem0/mem_mem_RAMREG_24_G[5]_s0/CE |
+R12C43[1][B] |
+core0/alu_out_4_s1/D |
Data Required Path:
@@ -17085,7 +14781,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.683 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -17095,8 +14791,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R32C26[2][B] |
-mem0/mem_mem_RAMREG_24_G[5]_s0/CLK |
+R12C43[1][B] |
+core0/alu_out_4_s1/CLK |
10.891 |
@@ -17104,8 +14800,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tSu |
|
1 |
-R32C26[2][B] |
-mem0/mem_mem_RAMREG_24_G[5]_s0 |
+R12C43[1][B] |
+core0/alu_out_4_s1 |
Path Statistics:
@@ -17120,7 +14816,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-13 |
+5 |
Arrival Clock Path Delay |
@@ -17128,7 +14824,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 5.403, 38.183%; route: 8.515, 60.177%; tC2Q: 0.232, 1.640% |
+cell: 2.127, 32.888%; route: 2.081, 32.175%; tC2Q: 2.260, 34.937% |
Required Clock Path Delay |
@@ -17142,19 +14838,19 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.346 |
+0.199 |
Data Arrival Time |
-1.323 |
+1.308 |
Data Required Time |
-0.978 |
+1.109 |
From |
-core0/rs2_4_s0 |
+core0/reg_wb_data_30_s0 |
To |
@@ -17212,7 +14908,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -17222,8 +14918,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R30C18[1][B] |
-core0/rs2_4_s0/CLK |
+R12C42[1][B] |
+core0/reg_wb_data_30_s0/CLK |
1.062 |
@@ -17231,17 +14927,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R30C18[1][B] |
-core0/rs2_4_s0/Q |
+R12C42[1][B] |
+core0/reg_wb_data_30_s0/Q |
-1.323 |
-0.262 |
+1.308 |
+0.246 |
tNET |
RR |
1 |
-BSRAM_R28[5] |
-core0/register_register_0_0_s/ADB[9] |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[30] |
Data Required Path:
@@ -17287,7 +14983,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -17297,16 +14993,816 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-BSRAM_R28[5] |
-core0/register_register_0_0_s/CLKB |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.978 |
-0.118 |
+1.109 |
+0.249 |
tHld |
|
1 |
-BSRAM_R28[5] |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
+
+
+Path Statistics:
+
+
+Clock Skew |
+0.000 |
+
+
+Hold Relationship |
+0.000 |
+
+
+Logic Level |
+1 |
+
+
+Arrival Clock Path Delay |
+cell: 0.675, 78.568%; route: 0.184, 21.432% |
+
+
+Arrival Data Path Delay |
+cell: 0.000, 0.000%; route: 0.246, 54.955%; tC2Q: 0.202, 45.045% |
+
+
+Required Clock Path Delay |
+cell: 0.675, 78.568%; route: 0.184, 21.432% |
+
+
+Path2
+Path Summary:
+
+
+Slack |
+0.203 |
+
+
+Data Arrival Time |
+1.312 |
+
+
+Data Required Time |
+1.109 |
+
+
+From |
+core0/reg_wb_data_7_s0 |
+
+
+To |
+core0/register_register_0_0_s |
+
+
+Launch Clk |
+clock:[R] |
+
+
+Latch Clk |
+clock:[R] |
+
+
+Data Arrival Path:
+
+
+AT |
+DELAY |
+TYPE |
+RF |
+FANOUT |
+LOC |
+NODE |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+active clock edge time |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+clock |
+
+
+0.000 |
+0.000 |
+tCL |
+RR |
+1 |
+IOT27[A] |
+clock_ibuf/I |
+
+
+0.675 |
+0.675 |
+tINS |
+RR |
+206 |
+IOT27[A] |
+clock_ibuf/O |
+
+
+0.860 |
+0.184 |
+tNET |
+RR |
+1 |
+R12C38[0][B] |
+core0/reg_wb_data_7_s0/CLK |
+
+
+1.062 |
+0.202 |
+tC2Q |
+RR |
+2 |
+R12C38[0][B] |
+core0/reg_wb_data_7_s0/Q |
+
+
+1.312 |
+0.250 |
+tNET |
+RR |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[7] |
+
+
+Data Required Path:
+
+
+AT |
+DELAY |
+TYPE |
+RF |
+FANOUT |
+LOC |
+NODE |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+active clock edge time |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+clock |
+
+
+0.000 |
+0.000 |
+tCL |
+RR |
+1 |
+IOT27[A] |
+clock_ibuf/I |
+
+
+0.675 |
+0.675 |
+tINS |
+RR |
+206 |
+IOT27[A] |
+clock_ibuf/O |
+
+
+0.860 |
+0.184 |
+tNET |
+RR |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
+
+
+1.109 |
+0.249 |
+tHld |
+ |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
+
+
+Path Statistics:
+
+
+Clock Skew |
+0.000 |
+
+
+Hold Relationship |
+0.000 |
+
+
+Logic Level |
+1 |
+
+
+Arrival Clock Path Delay |
+cell: 0.675, 78.568%; route: 0.184, 21.432% |
+
+
+Arrival Data Path Delay |
+cell: 0.000, 0.000%; route: 0.250, 55.351%; tC2Q: 0.202, 44.649% |
+
+
+Required Clock Path Delay |
+cell: 0.675, 78.568%; route: 0.184, 21.432% |
+
+
+Path3
+Path Summary:
+
+
+Slack |
+0.203 |
+
+
+Data Arrival Time |
+1.312 |
+
+
+Data Required Time |
+1.109 |
+
+
+From |
+core0/reg_wb_data_6_s0 |
+
+
+To |
+core0/register_register_0_0_s |
+
+
+Launch Clk |
+clock:[R] |
+
+
+Latch Clk |
+clock:[R] |
+
+
+Data Arrival Path:
+
+
+AT |
+DELAY |
+TYPE |
+RF |
+FANOUT |
+LOC |
+NODE |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+active clock edge time |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+clock |
+
+
+0.000 |
+0.000 |
+tCL |
+RR |
+1 |
+IOT27[A] |
+clock_ibuf/I |
+
+
+0.675 |
+0.675 |
+tINS |
+RR |
+206 |
+IOT27[A] |
+clock_ibuf/O |
+
+
+0.860 |
+0.184 |
+tNET |
+RR |
+1 |
+R12C38[0][A] |
+core0/reg_wb_data_6_s0/CLK |
+
+
+1.062 |
+0.202 |
+tC2Q |
+RR |
+2 |
+R12C38[0][A] |
+core0/reg_wb_data_6_s0/Q |
+
+
+1.312 |
+0.250 |
+tNET |
+RR |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[6] |
+
+
+Data Required Path:
+
+
+AT |
+DELAY |
+TYPE |
+RF |
+FANOUT |
+LOC |
+NODE |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+active clock edge time |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+clock |
+
+
+0.000 |
+0.000 |
+tCL |
+RR |
+1 |
+IOT27[A] |
+clock_ibuf/I |
+
+
+0.675 |
+0.675 |
+tINS |
+RR |
+206 |
+IOT27[A] |
+clock_ibuf/O |
+
+
+0.860 |
+0.184 |
+tNET |
+RR |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
+
+
+1.109 |
+0.249 |
+tHld |
+ |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
+
+
+Path Statistics:
+
+
+Clock Skew |
+0.000 |
+
+
+Hold Relationship |
+0.000 |
+
+
+Logic Level |
+1 |
+
+
+Arrival Clock Path Delay |
+cell: 0.675, 78.568%; route: 0.184, 21.432% |
+
+
+Arrival Data Path Delay |
+cell: 0.000, 0.000%; route: 0.250, 55.351%; tC2Q: 0.202, 44.649% |
+
+
+Required Clock Path Delay |
+cell: 0.675, 78.568%; route: 0.184, 21.432% |
+
+
+Path4
+Path Summary:
+
+
+Slack |
+0.213 |
+
+
+Data Arrival Time |
+1.322 |
+
+
+Data Required Time |
+1.109 |
+
+
+From |
+core0/reg_wb_data_9_s0 |
+
+
+To |
+core0/register_register_0_0_s |
+
+
+Launch Clk |
+clock:[R] |
+
+
+Latch Clk |
+clock:[R] |
+
+
+Data Arrival Path:
+
+
+AT |
+DELAY |
+TYPE |
+RF |
+FANOUT |
+LOC |
+NODE |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+active clock edge time |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+clock |
+
+
+0.000 |
+0.000 |
+tCL |
+RR |
+1 |
+IOT27[A] |
+clock_ibuf/I |
+
+
+0.675 |
+0.675 |
+tINS |
+RR |
+206 |
+IOT27[A] |
+clock_ibuf/O |
+
+
+0.860 |
+0.184 |
+tNET |
+RR |
+1 |
+R12C38[1][B] |
+core0/reg_wb_data_9_s0/CLK |
+
+
+1.062 |
+0.202 |
+tC2Q |
+RR |
+2 |
+R12C38[1][B] |
+core0/reg_wb_data_9_s0/Q |
+
+
+1.322 |
+0.260 |
+tNET |
+RR |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[9] |
+
+
+Data Required Path:
+
+
+AT |
+DELAY |
+TYPE |
+RF |
+FANOUT |
+LOC |
+NODE |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+active clock edge time |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+clock |
+
+
+0.000 |
+0.000 |
+tCL |
+RR |
+1 |
+IOT27[A] |
+clock_ibuf/I |
+
+
+0.675 |
+0.675 |
+tINS |
+RR |
+206 |
+IOT27[A] |
+clock_ibuf/O |
+
+
+0.860 |
+0.184 |
+tNET |
+RR |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
+
+
+1.109 |
+0.249 |
+tHld |
+ |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
+
+
+Path Statistics:
+
+
+Clock Skew |
+0.000 |
+
+
+Hold Relationship |
+0.000 |
+
+
+Logic Level |
+1 |
+
+
+Arrival Clock Path Delay |
+cell: 0.675, 78.568%; route: 0.184, 21.432% |
+
+
+Arrival Data Path Delay |
+cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686% |
+
+
+Required Clock Path Delay |
+cell: 0.675, 78.568%; route: 0.184, 21.432% |
+
+
+Path5
+Path Summary:
+
+
+Slack |
+0.215 |
+
+
+Data Arrival Time |
+1.323 |
+
+
+Data Required Time |
+1.109 |
+
+
+From |
+core0/reg_wb_data_31_s0 |
+
+
+To |
+core0/register_register_0_0_s |
+
+
+Launch Clk |
+clock:[R] |
+
+
+Latch Clk |
+clock:[R] |
+
+
+Data Arrival Path:
+
+
+AT |
+DELAY |
+TYPE |
+RF |
+FANOUT |
+LOC |
+NODE |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+active clock edge time |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+clock |
+
+
+0.000 |
+0.000 |
+tCL |
+RR |
+1 |
+IOT27[A] |
+clock_ibuf/I |
+
+
+0.675 |
+0.675 |
+tINS |
+RR |
+206 |
+IOT27[A] |
+clock_ibuf/O |
+
+
+0.860 |
+0.184 |
+tNET |
+RR |
+1 |
+R11C42[0][A] |
+core0/reg_wb_data_31_s0/CLK |
+
+
+1.062 |
+0.202 |
+tC2Q |
+RR |
+2 |
+R11C42[0][A] |
+core0/reg_wb_data_31_s0/Q |
+
+
+1.323 |
+0.262 |
+tNET |
+RR |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[31] |
+
+
+Data Required Path:
+
+
+AT |
+DELAY |
+TYPE |
+RF |
+FANOUT |
+LOC |
+NODE |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+active clock edge time |
+
+
+0.000 |
+0.000 |
+ |
+ |
+ |
+ |
+clock |
+
+
+0.000 |
+0.000 |
+tCL |
+RR |
+1 |
+IOT27[A] |
+clock_ibuf/I |
+
+
+0.675 |
+0.675 |
+tINS |
+RR |
+206 |
+IOT27[A] |
+clock_ibuf/O |
+
+
+0.860 |
+0.184 |
+tNET |
+RR |
+1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
+
+
+1.109 |
+0.249 |
+tHld |
+ |
+1 |
+BSRAM_R10[11] |
core0/register_register_0_0_s |
@@ -17337,882 +15833,28 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
cell: 0.675, 78.568%; route: 0.184, 21.432% |
-Path2
-Path Summary:
-
-
-Slack |
-0.359 |
-
-
-Data Arrival Time |
-1.337 |
-
-
-Data Required Time |
-0.978 |
-
-
-From |
-core0/rd_0_s0 |
-
-
-To |
-core0/register_register_0_0_s |
-
-
-Launch Clk |
-clock:[R] |
-
-
-Latch Clk |
-clock:[R] |
-
-
-Data Arrival Path:
-
-
-AT |
-DELAY |
-TYPE |
-RF |
-FANOUT |
-LOC |
-NODE |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-active clock edge time |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-clock |
-
-
-0.000 |
-0.000 |
-tCL |
-RR |
-1 |
-IOT27[A] |
-clock_ibuf/I |
-
-
-0.675 |
-0.675 |
-tINS |
-RR |
-759 |
-IOT27[A] |
-clock_ibuf/O |
-
-
-0.860 |
-0.184 |
-tNET |
-RR |
-1 |
-R27C22[2][A] |
-core0/rd_0_s0/CLK |
-
-
-1.062 |
-0.202 |
-tC2Q |
-RR |
-4 |
-R27C22[2][A] |
-core0/rd_0_s0/Q |
-
-
-1.337 |
-0.275 |
-tNET |
-RR |
-1 |
-BSRAM_R28[5] |
-core0/register_register_0_0_s/ADA[5] |
-
-
-Data Required Path:
-
-
-AT |
-DELAY |
-TYPE |
-RF |
-FANOUT |
-LOC |
-NODE |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-active clock edge time |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-clock |
-
-
-0.000 |
-0.000 |
-tCL |
-RR |
-1 |
-IOT27[A] |
-clock_ibuf/I |
-
-
-0.675 |
-0.675 |
-tINS |
-RR |
-759 |
-IOT27[A] |
-clock_ibuf/O |
-
-
-0.860 |
-0.184 |
-tNET |
-RR |
-1 |
-BSRAM_R28[5] |
-core0/register_register_0_0_s/CLKA |
-
-
-0.978 |
-0.118 |
-tHld |
- |
-1 |
-BSRAM_R28[5] |
-core0/register_register_0_0_s |
-
-
-Path Statistics:
-
-
-Clock Skew |
-0.000 |
-
-
-Hold Relationship |
-0.000 |
-
-
-Logic Level |
-1 |
-
-
-Arrival Clock Path Delay |
-cell: 0.675, 78.568%; route: 0.184, 21.432% |
-
-
-Arrival Data Path Delay |
-cell: 0.000, 0.000%; route: 0.275, 57.645%; tC2Q: 0.202, 42.355% |
-
-
-Required Clock Path Delay |
-cell: 0.675, 78.568%; route: 0.184, 21.432% |
-
-
-Path3
-Path Summary:
-
-
-Slack |
-0.425 |
-
-
-Data Arrival Time |
-1.296 |
-
-
-Data Required Time |
-0.871 |
-
-
-From |
-core0/alu_out_0_s1 |
-
-
-To |
-core0/alu_out_0_s1 |
-
-
-Launch Clk |
-clock:[R] |
-
-
-Latch Clk |
-clock:[R] |
-
-
-Data Arrival Path:
-
-
-AT |
-DELAY |
-TYPE |
-RF |
-FANOUT |
-LOC |
-NODE |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-active clock edge time |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-clock |
-
-
-0.000 |
-0.000 |
-tCL |
-RR |
-1 |
-IOT27[A] |
-clock_ibuf/I |
-
-
-0.675 |
-0.675 |
-tINS |
-RR |
-759 |
-IOT27[A] |
-clock_ibuf/O |
-
-
-0.860 |
-0.184 |
-tNET |
-RR |
-1 |
-R32C18[0][A] |
-core0/alu_out_0_s1/CLK |
-
-
-1.062 |
-0.202 |
-tC2Q |
-RR |
-2 |
-R32C18[0][A] |
-core0/alu_out_0_s1/Q |
-
-
-1.064 |
-0.002 |
-tNET |
-RR |
-1 |
-R32C18[0][A] |
-core0/n586_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R32C18[0][A] |
-core0/n586_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R32C18[0][A] |
-core0/alu_out_0_s1/D |
-
-
-Data Required Path:
-
-
-AT |
-DELAY |
-TYPE |
-RF |
-FANOUT |
-LOC |
-NODE |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-active clock edge time |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-clock |
-
-
-0.000 |
-0.000 |
-tCL |
-RR |
-1 |
-IOT27[A] |
-clock_ibuf/I |
-
-
-0.675 |
-0.675 |
-tINS |
-RR |
-759 |
-IOT27[A] |
-clock_ibuf/O |
-
-
-0.860 |
-0.184 |
-tNET |
-RR |
-1 |
-R32C18[0][A] |
-core0/alu_out_0_s1/CLK |
-
-
-0.871 |
-0.011 |
-tHld |
- |
-1 |
-R32C18[0][A] |
-core0/alu_out_0_s1 |
-
-
-Path Statistics:
-
-
-Clock Skew |
-0.000 |
-
-
-Hold Relationship |
-0.000 |
-
-
-Logic Level |
-2 |
-
-
-Arrival Clock Path Delay |
-cell: 0.675, 78.568%; route: 0.184, 21.432% |
-
-
-Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
-
-
-Required Clock Path Delay |
-cell: 0.675, 78.568%; route: 0.184, 21.432% |
-
-
-Path4
-Path Summary:
-
-
-Slack |
-0.425 |
-
-
-Data Arrival Time |
-1.296 |
-
-
-Data Required Time |
-0.871 |
-
-
-From |
-core0/alu_out_3_s1 |
-
-
-To |
-core0/alu_out_3_s1 |
-
-
-Launch Clk |
-clock:[R] |
-
-
-Latch Clk |
-clock:[R] |
-
-
-Data Arrival Path:
-
-
-AT |
-DELAY |
-TYPE |
-RF |
-FANOUT |
-LOC |
-NODE |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-active clock edge time |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-clock |
-
-
-0.000 |
-0.000 |
-tCL |
-RR |
-1 |
-IOT27[A] |
-clock_ibuf/I |
-
-
-0.675 |
-0.675 |
-tINS |
-RR |
-759 |
-IOT27[A] |
-clock_ibuf/O |
-
-
-0.860 |
-0.184 |
-tNET |
-RR |
-1 |
-R32C18[1][A] |
-core0/alu_out_3_s1/CLK |
-
-
-1.062 |
-0.202 |
-tC2Q |
-RR |
-2 |
-R32C18[1][A] |
-core0/alu_out_3_s1/Q |
-
-
-1.064 |
-0.002 |
-tNET |
-RR |
-1 |
-R32C18[1][A] |
-core0/n580_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R32C18[1][A] |
-core0/n580_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R32C18[1][A] |
-core0/alu_out_3_s1/D |
-
-
-Data Required Path:
-
-
-AT |
-DELAY |
-TYPE |
-RF |
-FANOUT |
-LOC |
-NODE |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-active clock edge time |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-clock |
-
-
-0.000 |
-0.000 |
-tCL |
-RR |
-1 |
-IOT27[A] |
-clock_ibuf/I |
-
-
-0.675 |
-0.675 |
-tINS |
-RR |
-759 |
-IOT27[A] |
-clock_ibuf/O |
-
-
-0.860 |
-0.184 |
-tNET |
-RR |
-1 |
-R32C18[1][A] |
-core0/alu_out_3_s1/CLK |
-
-
-0.871 |
-0.011 |
-tHld |
- |
-1 |
-R32C18[1][A] |
-core0/alu_out_3_s1 |
-
-
-Path Statistics:
-
-
-Clock Skew |
-0.000 |
-
-
-Hold Relationship |
-0.000 |
-
-
-Logic Level |
-2 |
-
-
-Arrival Clock Path Delay |
-cell: 0.675, 78.568%; route: 0.184, 21.432% |
-
-
-Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
-
-
-Required Clock Path Delay |
-cell: 0.675, 78.568%; route: 0.184, 21.432% |
-
-
-Path5
-Path Summary:
-
-
-Slack |
-0.425 |
-
-
-Data Arrival Time |
-1.296 |
-
-
-Data Required Time |
-0.871 |
-
-
-From |
-core0/alu_out_5_s1 |
-
-
-To |
-core0/alu_out_5_s1 |
-
-
-Launch Clk |
-clock:[R] |
-
-
-Latch Clk |
-clock:[R] |
-
-
-Data Arrival Path:
-
-
-AT |
-DELAY |
-TYPE |
-RF |
-FANOUT |
-LOC |
-NODE |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-active clock edge time |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-clock |
-
-
-0.000 |
-0.000 |
-tCL |
-RR |
-1 |
-IOT27[A] |
-clock_ibuf/I |
-
-
-0.675 |
-0.675 |
-tINS |
-RR |
-759 |
-IOT27[A] |
-clock_ibuf/O |
-
-
-0.860 |
-0.184 |
-tNET |
-RR |
-1 |
-R29C17[0][A] |
-core0/alu_out_5_s1/CLK |
-
-
-1.062 |
-0.202 |
-tC2Q |
-RR |
-2 |
-R29C17[0][A] |
-core0/alu_out_5_s1/Q |
-
-
-1.064 |
-0.002 |
-tNET |
-RR |
-1 |
-R29C17[0][A] |
-core0/n576_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R29C17[0][A] |
-core0/n576_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R29C17[0][A] |
-core0/alu_out_5_s1/D |
-
-
-Data Required Path:
-
-
-AT |
-DELAY |
-TYPE |
-RF |
-FANOUT |
-LOC |
-NODE |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-active clock edge time |
-
-
-0.000 |
-0.000 |
- |
- |
- |
- |
-clock |
-
-
-0.000 |
-0.000 |
-tCL |
-RR |
-1 |
-IOT27[A] |
-clock_ibuf/I |
-
-
-0.675 |
-0.675 |
-tINS |
-RR |
-759 |
-IOT27[A] |
-clock_ibuf/O |
-
-
-0.860 |
-0.184 |
-tNET |
-RR |
-1 |
-R29C17[0][A] |
-core0/alu_out_5_s1/CLK |
-
-
-0.871 |
-0.011 |
-tHld |
- |
-1 |
-R29C17[0][A] |
-core0/alu_out_5_s1 |
-
-
-Path Statistics:
-
-
-Clock Skew |
-0.000 |
-
-
-Hold Relationship |
-0.000 |
-
-
-Logic Level |
-2 |
-
-
-Arrival Clock Path Delay |
-cell: 0.675, 78.568%; route: 0.184, 21.432% |
-
-
-Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
-
-
-Required Clock Path Delay |
-cell: 0.675, 78.568%; route: 0.184, 21.432% |
-
-
Path6
Path Summary:
Slack |
-0.425 |
+0.215 |
Data Arrival Time |
-1.296 |
+1.323 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_6_s1 |
+core0/reg_wb_data_21_s0 |
To |
-core0/alu_out_6_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -18266,7 +15908,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -18276,8 +15918,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R32C15[0][A] |
-core0/alu_out_6_s1/CLK |
+R13C39[0][A] |
+core0/reg_wb_data_21_s0/CLK |
1.062 |
@@ -18285,35 +15927,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R32C15[0][A] |
-core0/alu_out_6_s1/Q |
+R13C39[0][A] |
+core0/reg_wb_data_21_s0/Q |
-1.064 |
-0.002 |
+1.323 |
+0.262 |
tNET |
RR |
1 |
-R32C15[0][A] |
-core0/n574_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R32C15[0][A] |
-core0/n574_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R32C15[0][A] |
-core0/alu_out_6_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[21] |
Data Required Path:
@@ -18359,7 +15983,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -18369,17 +15993,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R32C15[0][A] |
-core0/alu_out_6_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R32C15[0][A] |
-core0/alu_out_6_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -18394,7 +16018,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -18402,7 +16026,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571% |
Required Clock Path Delay |
@@ -18414,23 +16038,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.215 |
Data Arrival Time |
-1.296 |
+1.323 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_7_s1 |
+core0/reg_wb_data_20_s0 |
To |
-core0/alu_out_7_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -18484,7 +16108,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -18494,8 +16118,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R34C13[0][A] |
-core0/alu_out_7_s1/CLK |
+R13C39[0][B] |
+core0/reg_wb_data_20_s0/CLK |
1.062 |
@@ -18503,35 +16127,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R34C13[0][A] |
-core0/alu_out_7_s1/Q |
+R13C39[0][B] |
+core0/reg_wb_data_20_s0/Q |
-1.064 |
-0.002 |
+1.323 |
+0.262 |
tNET |
RR |
1 |
-R34C13[0][A] |
-core0/n572_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R34C13[0][A] |
-core0/n572_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R34C13[0][A] |
-core0/alu_out_7_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[20] |
Data Required Path:
@@ -18577,7 +16183,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -18587,17 +16193,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R34C13[0][A] |
-core0/alu_out_7_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R34C13[0][A] |
-core0/alu_out_7_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -18612,7 +16218,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -18620,7 +16226,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571% |
Required Clock Path Delay |
@@ -18632,23 +16238,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.215 |
Data Arrival Time |
-1.296 |
+1.323 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_9_s1 |
+core0/reg_wb_data_11_s0 |
To |
-core0/alu_out_9_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -18702,7 +16308,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -18712,8 +16318,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R33C12[1][A] |
-core0/alu_out_9_s1/CLK |
+R12C38[2][B] |
+core0/reg_wb_data_11_s0/CLK |
1.062 |
@@ -18721,35 +16327,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R33C12[1][A] |
-core0/alu_out_9_s1/Q |
+R12C38[2][B] |
+core0/reg_wb_data_11_s0/Q |
-1.064 |
-0.002 |
+1.323 |
+0.262 |
tNET |
RR |
1 |
-R33C12[1][A] |
-core0/n568_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R33C12[1][A] |
-core0/n568_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R33C12[1][A] |
-core0/alu_out_9_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[11] |
Data Required Path:
@@ -18795,7 +16383,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -18805,17 +16393,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R33C12[1][A] |
-core0/alu_out_9_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R33C12[1][A] |
-core0/alu_out_9_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -18830,7 +16418,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -18838,7 +16426,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571% |
Required Clock Path Delay |
@@ -18850,23 +16438,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.215 |
Data Arrival Time |
-1.296 |
+1.323 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_11_s1 |
+core0/reg_wb_data_10_s0 |
To |
-core0/alu_out_11_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -18920,7 +16508,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -18930,8 +16518,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R33C12[0][A] |
-core0/alu_out_11_s1/CLK |
+R12C38[2][A] |
+core0/reg_wb_data_10_s0/CLK |
1.062 |
@@ -18939,35 +16527,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R33C12[0][A] |
-core0/alu_out_11_s1/Q |
+R12C38[2][A] |
+core0/reg_wb_data_10_s0/Q |
-1.064 |
-0.002 |
+1.323 |
+0.262 |
tNET |
RR |
1 |
-R33C12[0][A] |
-core0/n564_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R33C12[0][A] |
-core0/n564_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R33C12[0][A] |
-core0/alu_out_11_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[10] |
Data Required Path:
@@ -19013,7 +16583,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -19023,17 +16593,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R33C12[0][A] |
-core0/alu_out_11_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R33C12[0][A] |
-core0/alu_out_11_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -19048,7 +16618,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -19056,7 +16626,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571% |
Required Clock Path Delay |
@@ -19068,23 +16638,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.215 |
Data Arrival Time |
-1.296 |
+1.323 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_12_s1 |
+core0/reg_wb_data_8_s0 |
To |
-core0/alu_out_12_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -19138,7 +16708,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -19148,8 +16718,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R33C13[0][A] |
-core0/alu_out_12_s1/CLK |
+R12C38[1][A] |
+core0/reg_wb_data_8_s0/CLK |
1.062 |
@@ -19157,35 +16727,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R33C13[0][A] |
-core0/alu_out_12_s1/Q |
+R12C38[1][A] |
+core0/reg_wb_data_8_s0/Q |
-1.064 |
-0.002 |
+1.323 |
+0.262 |
tNET |
RR |
1 |
-R33C13[0][A] |
-core0/n562_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R33C13[0][A] |
-core0/n562_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R33C13[0][A] |
-core0/alu_out_12_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[8] |
Data Required Path:
@@ -19231,7 +16783,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -19241,17 +16793,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R33C13[0][A] |
-core0/alu_out_12_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R33C13[0][A] |
-core0/alu_out_12_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -19266,7 +16818,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -19274,7 +16826,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571% |
Required Clock Path Delay |
@@ -19286,23 +16838,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.215 |
Data Arrival Time |
-1.296 |
+1.323 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_13_s1 |
+core0/reg_wb_data_5_s0 |
To |
-core0/alu_out_13_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -19356,7 +16908,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -19366,8 +16918,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R29C13[0][A] |
-core0/alu_out_13_s1/CLK |
+R13C38[2][A] |
+core0/reg_wb_data_5_s0/CLK |
1.062 |
@@ -19375,35 +16927,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R29C13[0][A] |
-core0/alu_out_13_s1/Q |
+R13C38[2][A] |
+core0/reg_wb_data_5_s0/Q |
-1.064 |
-0.002 |
+1.323 |
+0.262 |
tNET |
RR |
1 |
-R29C13[0][A] |
-core0/n560_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R29C13[0][A] |
-core0/n560_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R29C13[0][A] |
-core0/alu_out_13_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[5] |
Data Required Path:
@@ -19449,7 +16983,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -19459,17 +16993,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R29C13[0][A] |
-core0/alu_out_13_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R29C13[0][A] |
-core0/alu_out_13_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -19484,7 +17018,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -19492,7 +17026,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571% |
Required Clock Path Delay |
@@ -19504,23 +17038,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.215 |
Data Arrival Time |
-1.296 |
+1.323 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_14_s1 |
+core0/reg_wb_data_4_s0 |
To |
-core0/alu_out_14_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -19574,7 +17108,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -19584,8 +17118,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R33C13[1][A] |
-core0/alu_out_14_s1/CLK |
+R13C38[1][A] |
+core0/reg_wb_data_4_s0/CLK |
1.062 |
@@ -19593,35 +17127,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R33C13[1][A] |
-core0/alu_out_14_s1/Q |
+R13C38[1][A] |
+core0/reg_wb_data_4_s0/Q |
-1.064 |
-0.002 |
+1.323 |
+0.262 |
tNET |
RR |
1 |
-R33C13[1][A] |
-core0/n558_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R33C13[1][A] |
-core0/n558_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R33C13[1][A] |
-core0/alu_out_14_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[4] |
Data Required Path:
@@ -19667,7 +17183,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -19677,17 +17193,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R33C13[1][A] |
-core0/alu_out_14_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R33C13[1][A] |
-core0/alu_out_14_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -19702,7 +17218,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -19710,7 +17226,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.262, 56.429%; tC2Q: 0.202, 43.571% |
Required Clock Path Delay |
@@ -19722,23 +17238,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.227 |
Data Arrival Time |
-1.296 |
+1.335 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_23_s1 |
+core0/reg_wb_data_29_s0 |
To |
-core0/alu_out_23_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -19792,7 +17308,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -19802,8 +17318,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R31C12[0][A] |
-core0/alu_out_23_s1/CLK |
+R14C42[0][B] |
+core0/reg_wb_data_29_s0/CLK |
1.062 |
@@ -19811,35 +17327,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R31C12[0][A] |
-core0/alu_out_23_s1/Q |
+R14C42[0][B] |
+core0/reg_wb_data_29_s0/Q |
-1.064 |
-0.002 |
+1.335 |
+0.274 |
tNET |
RR |
1 |
-R31C12[0][A] |
-core0/n540_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R31C12[0][A] |
-core0/n540_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R31C12[0][A] |
-core0/alu_out_23_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[29] |
Data Required Path:
@@ -19885,7 +17383,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -19895,17 +17393,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R31C12[0][A] |
-core0/alu_out_23_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R31C12[0][A] |
-core0/alu_out_23_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -19920,7 +17418,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -19928,7 +17426,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.274, 57.536%; tC2Q: 0.202, 42.464% |
Required Clock Path Delay |
@@ -19940,23 +17438,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.321 |
Data Arrival Time |
-1.296 |
+1.430 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_25_s1 |
+core0/reg_wb_data_25_s0 |
To |
-core0/alu_out_25_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -20010,7 +17508,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20020,8 +17518,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R31C12[1][A] |
-core0/alu_out_25_s1/CLK |
+R13C42[0][A] |
+core0/reg_wb_data_25_s0/CLK |
1.062 |
@@ -20029,35 +17527,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R31C12[1][A] |
-core0/alu_out_25_s1/Q |
+R13C42[0][A] |
+core0/reg_wb_data_25_s0/Q |
-1.064 |
-0.002 |
+1.430 |
+0.368 |
tNET |
RR |
1 |
-R31C12[1][A] |
-core0/n536_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R31C12[1][A] |
-core0/n536_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R31C12[1][A] |
-core0/alu_out_25_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[25] |
Data Required Path:
@@ -20103,7 +17583,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20113,17 +17593,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R31C12[1][A] |
-core0/alu_out_25_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R31C12[1][A] |
-core0/alu_out_25_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -20138,7 +17618,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -20146,7 +17626,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.368, 64.589%; tC2Q: 0.202, 35.411% |
Required Clock Path Delay |
@@ -20158,23 +17638,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.321 |
Data Arrival Time |
-1.296 |
+1.430 |
Data Required Time |
-0.871 |
+1.109 |
From |
-core0/alu_out_27_s1 |
+core0/reg_wb_data_24_s0 |
To |
-core0/alu_out_27_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -20228,7 +17708,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20238,8 +17718,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R32C13[0][A] |
-core0/alu_out_27_s1/CLK |
+R13C42[1][B] |
+core0/reg_wb_data_24_s0/CLK |
1.062 |
@@ -20247,35 +17727,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R32C13[0][A] |
-core0/alu_out_27_s1/Q |
+R13C42[1][B] |
+core0/reg_wb_data_24_s0/Q |
-1.064 |
-0.002 |
+1.430 |
+0.368 |
tNET |
RR |
1 |
-R32C13[0][A] |
-core0/n532_s5/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R32C13[0][A] |
-core0/n532_s5/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R32C13[0][A] |
-core0/alu_out_27_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[24] |
Data Required Path:
@@ -20321,7 +17783,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20331,17 +17793,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R32C13[0][A] |
-core0/alu_out_27_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R32C13[0][A] |
-core0/alu_out_27_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -20356,7 +17818,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -20364,7 +17826,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.368, 64.589%; tC2Q: 0.202, 35.411% |
Required Clock Path Delay |
@@ -20376,23 +17838,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.325 |
Data Arrival Time |
-1.296 |
+1.434 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/led_flag_s1 |
+core0/reg_wb_data_27_s0 |
To |
-uart0/led_flag_s1 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -20446,7 +17908,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20456,8 +17918,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R21C27[0][A] |
-uart0/led_flag_s1/CLK |
+R12C42[1][A] |
+core0/reg_wb_data_27_s0/CLK |
1.062 |
@@ -20465,35 +17927,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R21C27[0][A] |
-uart0/led_flag_s1/Q |
+R12C42[1][A] |
+core0/reg_wb_data_27_s0/Q |
-1.064 |
-0.002 |
+1.434 |
+0.372 |
tNET |
RR |
1 |
-R21C27[0][A] |
-uart0/n79_s2/I0 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
-1 |
-R21C27[0][A] |
-uart0/n79_s2/F |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R21C27[0][A] |
-uart0/led_flag_s1/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[27] |
Data Required Path:
@@ -20539,7 +17983,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20549,17 +17993,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R21C27[0][A] |
-uart0/led_flag_s1/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R21C27[0][A] |
-uart0/led_flag_s1 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -20574,7 +18018,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -20582,7 +18026,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.372, 64.834%; tC2Q: 0.202, 35.166% |
Required Clock Path Delay |
@@ -20594,23 +18038,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.337 |
Data Arrival Time |
-1.296 |
+1.445 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/clock_count_2_s0 |
+core0/reg_wb_data_17_s0 |
To |
-uart0/clock_count_2_s0 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -20664,7 +18108,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20674,8 +18118,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C27[1][A] |
-uart0/clock_count_2_s0/CLK |
+R14C40[2][B] |
+core0/reg_wb_data_17_s0/CLK |
1.062 |
@@ -20683,35 +18127,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R23C27[1][A] |
-uart0/clock_count_2_s0/Q |
+R14C40[2][B] |
+core0/reg_wb_data_17_s0/Q |
-1.064 |
-0.002 |
+1.445 |
+0.384 |
tNET |
RR |
-2 |
-R23C27[1][A] |
-uart0/n44_s/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
1 |
-R23C27[1][A] |
-uart0/n44_s/SUM |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R23C27[1][A] |
-uart0/clock_count_2_s0/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[17] |
Data Required Path:
@@ -20757,7 +18183,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20767,17 +18193,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C27[1][A] |
-uart0/clock_count_2_s0/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R23C27[1][A] |
-uart0/clock_count_2_s0 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -20792,7 +18218,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -20800,7 +18226,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494% |
Required Clock Path Delay |
@@ -20812,23 +18238,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.337 |
Data Arrival Time |
-1.296 |
+1.445 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/clock_count_6_s0 |
+core0/reg_wb_data_15_s0 |
To |
-uart0/clock_count_6_s0 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -20882,7 +18308,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20892,44 +18318,26 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C28[0][A] |
-uart0/clock_count_6_s0/CLK |
+R13C40[0][A] |
+core0/reg_wb_data_15_s0/CLK |
1.062 |
0.202 |
tC2Q |
RR |
-3 |
-R23C28[0][A] |
-uart0/clock_count_6_s0/Q |
+2 |
+R13C40[0][A] |
+core0/reg_wb_data_15_s0/Q |
-1.064 |
-0.002 |
+1.445 |
+0.384 |
tNET |
RR |
-2 |
-R23C28[0][A] |
-uart0/n40_s/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
1 |
-R23C28[0][A] |
-uart0/n40_s/SUM |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R23C28[0][A] |
-uart0/clock_count_6_s0/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[15] |
Data Required Path:
@@ -20975,7 +18383,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -20985,17 +18393,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C28[0][A] |
-uart0/clock_count_6_s0/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R23C28[0][A] |
-uart0/clock_count_6_s0 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -21010,7 +18418,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -21018,7 +18426,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494% |
Required Clock Path Delay |
@@ -21030,23 +18438,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.337 |
Data Arrival Time |
-1.296 |
+1.445 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/clock_count_8_s0 |
+core0/reg_wb_data_14_s0 |
To |
-uart0/clock_count_8_s0 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -21100,7 +18508,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -21110,8 +18518,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C28[1][A] |
-uart0/clock_count_8_s0/CLK |
+R15C39[0][B] |
+core0/reg_wb_data_14_s0/CLK |
1.062 |
@@ -21119,35 +18527,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R23C28[1][A] |
-uart0/clock_count_8_s0/Q |
+R15C39[0][B] |
+core0/reg_wb_data_14_s0/Q |
-1.064 |
-0.002 |
+1.445 |
+0.384 |
tNET |
RR |
-2 |
-R23C28[1][A] |
-uart0/n38_s/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
1 |
-R23C28[1][A] |
-uart0/n38_s/SUM |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R23C28[1][A] |
-uart0/clock_count_8_s0/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[14] |
Data Required Path:
@@ -21193,7 +18583,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -21203,17 +18593,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C28[1][A] |
-uart0/clock_count_8_s0/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R23C28[1][A] |
-uart0/clock_count_8_s0 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -21228,7 +18618,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -21236,7 +18626,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494% |
Required Clock Path Delay |
@@ -21248,23 +18638,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.337 |
Data Arrival Time |
-1.296 |
+1.445 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/clock_count_12_s0 |
+core0/reg_wb_data_0_s0 |
To |
-uart0/clock_count_12_s0 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -21318,7 +18708,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -21328,8 +18718,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C29[0][A] |
-uart0/clock_count_12_s0/CLK |
+R13C39[2][A] |
+core0/reg_wb_data_0_s0/CLK |
1.062 |
@@ -21337,35 +18727,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R23C29[0][A] |
-uart0/clock_count_12_s0/Q |
+R13C39[2][A] |
+core0/reg_wb_data_0_s0/Q |
-1.064 |
-0.002 |
+1.445 |
+0.384 |
tNET |
RR |
-2 |
-R23C29[0][A] |
-uart0/n34_s/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
1 |
-R23C29[0][A] |
-uart0/n34_s/SUM |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R23C29[0][A] |
-uart0/clock_count_12_s0/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[0] |
Data Required Path:
@@ -21411,7 +18783,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -21421,17 +18793,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C29[0][A] |
-uart0/clock_count_12_s0/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R23C29[0][A] |
-uart0/clock_count_12_s0 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -21446,7 +18818,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -21454,7 +18826,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.384, 65.506%; tC2Q: 0.202, 34.494% |
Required Clock Path Delay |
@@ -21466,23 +18838,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.353 |
Data Arrival Time |
-1.296 |
+1.461 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/clock_count_14_s0 |
+core0/reg_wb_data_23_s0 |
To |
-uart0/clock_count_14_s0 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -21536,7 +18908,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -21546,8 +18918,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C29[1][A] |
-uart0/clock_count_14_s0/CLK |
+R14C40[2][A] |
+core0/reg_wb_data_23_s0/CLK |
1.062 |
@@ -21555,35 +18927,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R23C29[1][A] |
-uart0/clock_count_14_s0/Q |
+R14C40[2][A] |
+core0/reg_wb_data_23_s0/Q |
-1.064 |
-0.002 |
+1.461 |
+0.400 |
tNET |
RR |
-2 |
-R23C29[1][A] |
-uart0/n32_s/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
1 |
-R23C29[1][A] |
-uart0/n32_s/SUM |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R23C29[1][A] |
-uart0/clock_count_14_s0/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[23] |
Data Required Path:
@@ -21629,7 +18983,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -21639,17 +18993,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C29[1][A] |
-uart0/clock_count_14_s0/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R23C29[1][A] |
-uart0/clock_count_14_s0 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -21664,7 +19018,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -21672,7 +19026,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.400, 66.427%; tC2Q: 0.202, 33.573% |
Required Clock Path Delay |
@@ -21684,23 +19038,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.353 |
Data Arrival Time |
-1.296 |
+1.461 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/clock_count_18_s0 |
+core0/reg_wb_data_1_s0 |
To |
-uart0/clock_count_18_s0 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -21754,7 +19108,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -21764,8 +19118,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C30[0][A] |
-uart0/clock_count_18_s0/CLK |
+R12C42[2][A] |
+core0/reg_wb_data_1_s0/CLK |
1.062 |
@@ -21773,35 +19127,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R23C30[0][A] |
-uart0/clock_count_18_s0/Q |
+R12C42[2][A] |
+core0/reg_wb_data_1_s0/Q |
-1.064 |
-0.002 |
+1.461 |
+0.400 |
tNET |
RR |
-2 |
-R23C30[0][A] |
-uart0/n28_s/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
1 |
-R23C30[0][A] |
-uart0/n28_s/SUM |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R23C30[0][A] |
-uart0/clock_count_18_s0/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[1] |
Data Required Path:
@@ -21847,7 +19183,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -21857,17 +19193,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C30[0][A] |
-uart0/clock_count_18_s0/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R23C30[0][A] |
-uart0/clock_count_18_s0 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -21882,7 +19218,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -21890,7 +19226,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.400, 66.427%; tC2Q: 0.202, 33.573% |
Required Clock Path Delay |
@@ -21902,23 +19238,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.364 |
Data Arrival Time |
-1.296 |
+1.473 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/clock_count_20_s0 |
+core0/reg_wb_data_19_s0 |
To |
-uart0/clock_count_20_s0 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -21972,7 +19308,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -21982,8 +19318,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C30[1][A] |
-uart0/clock_count_20_s0/CLK |
+R14C42[1][A] |
+core0/reg_wb_data_19_s0/CLK |
1.062 |
@@ -21991,35 +19327,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R23C30[1][A] |
-uart0/clock_count_20_s0/Q |
+R14C42[1][A] |
+core0/reg_wb_data_19_s0/Q |
-1.064 |
-0.002 |
+1.473 |
+0.411 |
tNET |
RR |
-2 |
-R23C30[1][A] |
-uart0/n26_s/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
1 |
-R23C30[1][A] |
-uart0/n26_s/SUM |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R23C30[1][A] |
-uart0/clock_count_20_s0/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[19] |
Data Required Path:
@@ -22065,7 +19383,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -22075,17 +19393,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C30[1][A] |
-uart0/clock_count_20_s0/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R23C30[1][A] |
-uart0/clock_count_20_s0 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -22100,7 +19418,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -22108,7 +19426,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.411, 67.040%; tC2Q: 0.202, 32.960% |
Required Clock Path Delay |
@@ -22120,23 +19438,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.364 |
Data Arrival Time |
-1.296 |
+1.473 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/clock_count_24_s0 |
+core0/reg_wb_data_13_s0 |
To |
-uart0/clock_count_24_s0 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -22190,7 +19508,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -22200,8 +19518,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C31[0][A] |
-uart0/clock_count_24_s0/CLK |
+R15C40[0][A] |
+core0/reg_wb_data_13_s0/CLK |
1.062 |
@@ -22209,35 +19527,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R23C31[0][A] |
-uart0/clock_count_24_s0/Q |
+R15C40[0][A] |
+core0/reg_wb_data_13_s0/Q |
-1.064 |
-0.002 |
+1.473 |
+0.411 |
tNET |
RR |
-2 |
-R23C31[0][A] |
-uart0/n22_s/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
1 |
-R23C31[0][A] |
-uart0/n22_s/SUM |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R23C31[0][A] |
-uart0/clock_count_24_s0/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[13] |
Data Required Path:
@@ -22283,7 +19583,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -22293,17 +19593,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C31[0][A] |
-uart0/clock_count_24_s0/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R23C31[0][A] |
-uart0/clock_count_24_s0 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -22318,7 +19618,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -22326,7 +19626,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.411, 67.040%; tC2Q: 0.202, 32.960% |
Required Clock Path Delay |
@@ -22338,23 +19638,23 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Slack |
-0.425 |
+0.364 |
Data Arrival Time |
-1.296 |
+1.473 |
Data Required Time |
-0.871 |
+1.109 |
From |
-uart0/clock_count_26_s0 |
+core0/reg_wb_data_3_s0 |
To |
-uart0/clock_count_26_s0 |
+core0/register_register_0_0_s |
Launch Clk |
@@ -22408,7 +19708,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -22418,8 +19718,8 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C31[1][A] |
-uart0/clock_count_26_s0/CLK |
+R13C38[2][B] |
+core0/reg_wb_data_3_s0/CLK |
1.062 |
@@ -22427,35 +19727,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tC2Q |
RR |
2 |
-R23C31[1][A] |
-uart0/clock_count_26_s0/Q |
+R13C38[2][B] |
+core0/reg_wb_data_3_s0/Q |
-1.064 |
-0.002 |
+1.473 |
+0.411 |
tNET |
RR |
-2 |
-R23C31[1][A] |
-uart0/n20_s/I1 |
-
-
-1.296 |
-0.232 |
-tINS |
-RF |
1 |
-R23C31[1][A] |
-uart0/n20_s/SUM |
-
-
-1.296 |
-0.000 |
-tNET |
-FF |
-1 |
-R23C31[1][A] |
-uart0/clock_count_26_s0/D |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/DI[3] |
Data Required Path:
@@ -22501,7 +19783,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.675 |
tINS |
RR |
-759 |
+206 |
IOT27[A] |
clock_ibuf/O |
@@ -22511,17 +19793,17 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
tNET |
RR |
1 |
-R23C31[1][A] |
-uart0/clock_count_26_s0/CLK |
+BSRAM_R10[11] |
+core0/register_register_0_0_s/CLKA |
-0.871 |
-0.011 |
+1.109 |
+0.249 |
tHld |
|
1 |
-R23C31[1][A] |
-uart0/clock_count_26_s0 |
+BSRAM_R10[11] |
+core0/register_register_0_0_s |
Path Statistics:
@@ -22536,7 +19818,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Logic Level |
-2 |
+1 |
Arrival Clock Path Delay |
@@ -22544,7 +19826,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Arrival Data Path Delay |
-cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
+cell: 0.000, 0.000%; route: 0.411, 67.040%; tC2Q: 0.202, 32.960% |
Required Clock Path Delay |
@@ -23174,7 +20456,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Objects: |
-mem0/mem_mem_RAMREG_0_G[4]_s0 |
+core0/reg_inst_28_s0 |
Late clock Path:
@@ -23219,7 +20501,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.261 |
tNET |
FF |
-mem0/mem_mem_RAMREG_0_G[4]_s0/CLK |
+core0/reg_inst_28_s0/CLK |
Early clock Path:
@@ -23264,7 +20546,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.184 |
tNET |
RR |
-mem0/mem_mem_RAMREG_0_G[4]_s0/CLK |
+core0/reg_inst_28_s0/CLK |
MPW7
@@ -23292,7 +20574,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Objects: |
-mem0/mem_mem_RAMREG_8_G[4]_s0 |
+core0/reg_wb_data_11_s0 |
Late clock Path:
@@ -23337,7 +20619,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.261 |
tNET |
FF |
-mem0/mem_mem_RAMREG_8_G[4]_s0/CLK |
+core0/reg_wb_data_11_s0/CLK |
Early clock Path:
@@ -23382,7 +20664,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.184 |
tNET |
RR |
-mem0/mem_mem_RAMREG_8_G[4]_s0/CLK |
+core0/reg_wb_data_11_s0/CLK |
MPW8
@@ -23410,7 +20692,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Objects: |
-mem0/mem_mem_RAMREG_24_G[4]_s0 |
+core0/reg_wb_data_12_s0 |
Late clock Path:
@@ -23455,7 +20737,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.261 |
tNET |
FF |
-mem0/mem_mem_RAMREG_24_G[4]_s0/CLK |
+core0/reg_wb_data_12_s0/CLK |
Early clock Path:
@@ -23500,7 +20782,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.184 |
tNET |
RR |
-mem0/mem_mem_RAMREG_24_G[4]_s0/CLK |
+core0/reg_wb_data_12_s0/CLK |
MPW9
@@ -23528,7 +20810,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Objects: |
-mem0/mem_mem_RAMREG_56_G[4]_s0 |
+core0/reg_inst_29_s0 |
Late clock Path:
@@ -23573,7 +20855,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.261 |
tNET |
FF |
-mem0/mem_mem_RAMREG_56_G[4]_s0/CLK |
+core0/reg_inst_29_s0/CLK |
Early clock Path:
@@ -23618,7 +20900,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.184 |
tNET |
RR |
-mem0/mem_mem_RAMREG_56_G[4]_s0/CLK |
+core0/reg_inst_29_s0/CLK |
MPW10
@@ -23646,7 +20928,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
Objects: |
-mem0/mem_mem_RAMREG_56_G[3]_s0 |
+core0/reg_wb_data_13_s0 |
Late clock Path:
@@ -23691,7 +20973,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.261 |
tNET |
FF |
-mem0/mem_mem_RAMREG_56_G[3]_s0/CLK |
+core0/reg_wb_data_13_s0/CLK |
Early clock Path:
@@ -23736,7 +21018,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
0.184 |
tNET |
RR |
-mem0/mem_mem_RAMREG_56_G[3]_s0/CLK |
+core0/reg_wb_data_13_s0/CLK |
@@ -23749,64 +21031,64 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
MAX DELAY |
-759 |
+206 |
clock_d |
--4.604 |
+2.196 |
0.261 |
-558 |
-raddr[5] |
--4.197 |
-1.942 |
+36 |
+n312_5 |
+8.189 |
+0.966 |
-260 |
-pc[5] |
-3.634 |
-2.206 |
+32 |
+n12_17 |
+6.024 |
+0.698 |
-257 |
-n36_15 |
-1.639 |
-2.760 |
+32 |
+register_rs1_data[0]_DOAL_G_0_3 |
+2.347 |
+0.934 |
-256 |
-n155_9 |
-2.875 |
-2.261 |
+25 |
+i_imm[7] |
+5.967 |
+0.956 |
-256 |
-n36_7 |
-1.639 |
-2.471 |
+23 |
+pc[2] |
+7.004 |
+0.919 |
-256 |
-n107_7 |
--0.070 |
-2.596 |
+22 |
+n213_4 |
+6.135 |
+0.725 |
-256 |
-n236_6 |
-2.990 |
-1.907 |
+21 |
+n314_3 |
+6.491 |
+0.967 |
-190 |
-raddr[4] |
--4.604 |
-1.840 |
+21 |
+reg_wb_data_31_6 |
+6.385 |
+0.755 |
-160 |
-n196_6 |
-3.511 |
-1.495 |
+21 |
+pc[0] |
+7.332 |
+0.559 |
@@ -23817,44 +21099,44 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
ROUTE CONGESTIONS |
-R31C39 |
-94.44% |
+R11C38 |
+84.72% |
-R24C33 |
-90.28% |
+R11C39 |
+83.33% |
-R18C35 |
-88.89% |
+R12C38 |
+83.33% |
-R32C18 |
-87.50% |
+R11C37 |
+81.94% |
-R33C38 |
-87.50% |
+R13C45 |
+81.94% |
-R34C35 |
-87.50% |
+R13C42 |
+80.56% |
-R32C20 |
-87.50% |
+R13C44 |
+80.56% |
-R32C27 |
-87.50% |
+R12C44 |
+80.56% |
-R29C39 |
-86.11% |
+R13C37 |
+80.56% |
-R30C18 |
-86.11% |
+R12C43 |
+79.17% |
diff --git a/src/core.v b/src/core.v
index e3b9936..a6a581c 100644
--- a/src/core.v
+++ b/src/core.v
@@ -30,6 +30,9 @@ module CORE(
reg [31:0] reg_wdata;
reg reg_wen;
+ reg [31:0] reg_wb_data;
+ reg reg_wb_wen;
+
reg [6:0] opcode;
reg [4:0] rd;
reg [2:0] funct3;
@@ -62,7 +65,10 @@ module CORE(
for (i=0;i<32;i=i+1) register[i] <= 31'b0;
register[0] <= 32'b00000000000000000000000000000000;
register[1] <= 32'b00000000000000000000000000000000;
- register[2] <= 32'b00000000000000000000000001000001;
+ register[2] <= 32'b00000000000000000000000000000000;
+
+ reg_wb_data = 0;
+ reg_wb_wen = 0;
pc = 0;
reg_inst = 0;
@@ -79,7 +85,7 @@ module CORE(
ST_IF: begin
reg_tx_start <= 1;
reg_tx_data <= rdata[31:24];
- REGISTER_TEST <= register[1][31:0];
+ REGISTER_TEST <= register[4][31:0];
reg_inst <= inst;
pc_p4 <= pc + 4;
@@ -104,13 +110,18 @@ module CORE(
end
ST_EX: begin
-
- case (opcode)
- `OP_SW:
- alu_out = rs1_data + s_imm_sext;
- `OP_LW:
- alu_out = rs1_data + i_imm_sext;
- endcase
+ if ((reg_inst & `MASK_OP_SW) == `OP_SW)
+ alu_out = rs1_data + s_imm_sext;
+ if ((reg_inst & `MASK_OP_LW) == `OP_LW)
+ alu_out = rs1_data + i_imm_sext;
+ if ((reg_inst & `MASK_OP_LUI) == `OP_LUI) begin
+ reg_wb_data[31:12] = u_imm[31:12];
+ reg_wb_wen = 1;
+ end
+ if ((reg_inst & `MASK_OP_ADDI) == `OP_ADDI) begin
+ reg_wb_data = rs1_data + i_imm_sext;
+ reg_wb_wen = 1;
+ end
stage <= ST_ACCESS;
end
@@ -127,7 +138,10 @@ module CORE(
if (opcode == `OP_LW)
register[rd] <= rdata;
+ if (reg_wb_wen == 1)
+ register[rd] <= reg_wb_data;
+ reg_wb_wen = 0;
pc = pc_p4;
alu_out = 0;
reg_wen = 0;
diff --git a/src/defs.vh b/src/defs.vh
index d580a0d..70b44b7 100644
--- a/src/defs.vh
+++ b/src/defs.vh
@@ -1,2 +1,11 @@
-`define OP_SW 7'b0100011
-`define OP_LW 7'b0000011
\ No newline at end of file
+`define OP_SW 32'b00000000000000000010000000100011
+`define MASK_OP_SW 32'b00000000000000000111000001111111
+
+`define OP_LW 32'b00000000000000000010000000000011
+`define MASK_OP_LW 32'b00000000000000000111000001111111
+
+`define OP_LUI 32'b00000000000000000000000000110111
+`define MASK_OP_LUI 32'b00000000000000000000000001111111
+
+`define OP_ADDI 32'b00000000000000000000000000010011
+`define MASK_OP_ADDI 32'b00000000000000000111000001111111
\ No newline at end of file
diff --git a/src/memory.v b/src/memory.v
index 83424a3..bdf2d95 100644
--- a/src/memory.v
+++ b/src/memory.v
@@ -17,15 +17,17 @@ module MEMORY(
integer i;
initial begin
for (i=0;i<64;i=i+1) mem[i] <= 0;
- mem[0] <= 8'b00000000;
- mem[1] <= 8'b00100000;
- mem[2] <= 8'b10100010;
- mem[3] <= 8'b00100011;
- mem[0] <= 8'b00000000;
- mem[1] <= 8'b00100000;
- mem[2] <= 8'b10100010;
- mem[3] <= 8'b00100011;
+ mem[0] <= 8'b1101_1101;
+ mem[1] <= 8'b0000_0000;
+ mem[2] <= 8'b0000_0010;
+ mem[3] <= 8'b0011_0111;
+
+ mem[4] <= 8'b0000_0011;
+ mem[5] <= 8'b0011_0010;
+ mem[6] <= 8'b0000_0010;
+ mem[7] <= 8'b0001_0011;
+
reg_raddr <= 32'b0;
end
diff --git a/src/tb_memory.o b/src/tb_memory.o
index ac10e8f..4ef133e 100644
--- a/src/tb_memory.o
+++ b/src/tb_memory.o
@@ -7,30 +7,30 @@
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
-S_0000028ded9179d0 .scope module, "memory_tb" "memory_tb" 2 1;
+S_0000021801ba52c0 .scope module, "memory_tb" "memory_tb" 2 1;
.timescale 0 0;
-P_0000028ded909940 .param/l "RATE" 0 2 3, +C4<00000000000000000000000000000001>;
-v0000028ded9740b0_0 .net "LED", 0 0, L_0000028ded902c40; 1 drivers
-v0000028ded974fb0_0 .net "TX", 0 0, L_0000028ded9028c0; 1 drivers
-v0000028ded973930_0 .var "clk", 0 0;
-S_0000028ded8e7f90 .scope module, "top" "TOP" 2 17, 3 1 0, S_0000028ded9179d0;
+P_0000021801be7060 .param/l "RATE" 0 2 3, +C4<00000000000000000000000000000001>;
+v0000021801c530f0_0 .net "LED", 0 0, L_0000021801be1260; 1 drivers
+v0000021801c521f0_0 .net "TX", 0 0, L_0000021801be13b0; 1 drivers
+v0000021801c51d90_0 .var "clk", 0 0;
+S_0000021801bc85c0 .scope module, "top" "TOP" 2 17, 3 1 0, S_0000021801ba52c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /OUTPUT 1 "LED";
.port_info 2 /OUTPUT 1 "tx";
-v0000028ded974330_0 .net "LED", 0 0, L_0000028ded902c40; alias, 1 drivers
-v0000028ded974470_0 .net "clock", 0 0, v0000028ded973930_0; 1 drivers
-v0000028ded973ed0_0 .net "iaddr", 31 0, v0000028ded970320_0; 1 drivers
-v0000028ded9743d0_0 .net "inst", 31 0, L_0000028ded974c90; 1 drivers
-v0000028ded973890_0 .net "raddr", 31 0, v0000028ded96f1a0_0; 1 drivers
-v0000028ded974d30_0 .net "rdata", 31 0, L_0000028ded973b10; 1 drivers
-v0000028ded974970_0 .net "tx", 0 0, L_0000028ded9028c0; alias, 1 drivers
-v0000028ded973f70_0 .net "tx_busy", 0 0, L_0000028ded9739d0; 1 drivers
-v0000028ded974650_0 .net "tx_data", 7 0, L_0000028ded9033b0; 1 drivers
-v0000028ded9748d0_0 .net "tx_start", 0 0, L_0000028ded902930; 1 drivers
-v0000028ded974dd0_0 .net "wdata", 31 0, L_0000028ded903500; 1 drivers
-v0000028ded974a10_0 .net "wen", 0 0, L_0000028ded9027e0; 1 drivers
-S_0000028ded8e8120 .scope module, "core0" "CORE" 3 36, 4 1 0, S_0000028ded8e7f90;
+v0000021801c520b0_0 .net "LED", 0 0, L_0000021801be1260; alias, 1 drivers
+v0000021801c51b10_0 .net "clock", 0 0, v0000021801c51d90_0; 1 drivers
+v0000021801c51ed0_0 .net "iaddr", 31 0, v0000021801c4e5a0_0; 1 drivers
+v0000021801c53550_0 .net "inst", 31 0, L_0000021801c52ab0; 1 drivers
+v0000021801c52970_0 .net "raddr", 31 0, v0000021801c4d380_0; 1 drivers
+v0000021801c523d0_0 .net "rdata", 31 0, L_0000021801c52a10; 1 drivers
+v0000021801c525b0_0 .net "tx", 0 0, L_0000021801be13b0; alias, 1 drivers
+v0000021801c52f10_0 .net "tx_busy", 0 0, L_0000021801c52dd0; 1 drivers
+v0000021801c51bb0_0 .net "tx_data", 7 0, L_0000021801be1420; 1 drivers
+v0000021801c51f70_0 .net "tx_start", 0 0, L_0000021801be1a40; 1 drivers
+v0000021801c52c90_0 .net "wdata", 31 0, L_0000021801be1b20; 1 drivers
+v0000021801c52d30_0 .net "wen", 0 0, L_0000021801be1880; 1 drivers
+S_0000021801bc8750 .scope module, "core0" "CORE" 3 36, 4 3 0, S_0000021801bc85c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /OUTPUT 1 "tx_start";
@@ -41,105 +41,107 @@ S_0000028ded8e8120 .scope module, "core0" "CORE" 3 36, 4 1 0, S_0000028ded8e7f90
.port_info 6 /OUTPUT 32 "wdata";
.port_info 7 /INPUT 32 "inst";
.port_info 8 /INPUT 32 "rdata";
-P_0000028ded906fb0 .param/l "ST_ACCESS" 1 4 54, +C4<00000000000000000000000000000011>;
-P_0000028ded906fe8 .param/l "ST_EX" 1 4 53, +C4<00000000000000000000000000000010>;
-P_0000028ded907020 .param/l "ST_ID" 1 4 52, +C4<00000000000000000000000000000001>;
-P_0000028ded907058 .param/l "ST_IF" 1 4 51, +C4<00000000000000000000000000000000>;
-P_0000028ded907090 .param/l "ST_WB" 1 4 55, +C4<00000000000000000000000000000100>;
-L_0000028ded9030a0 .functor BUFZ 32, L_0000028ded975730, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
-L_0000028ded902af0 .functor BUFZ 32, L_0000028ded973d90, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
-L_0000028ded902930 .functor BUFZ 1, v0000028ded96f2e0_0, C4<0>, C4<0>, C4<0>;
-L_0000028ded9033b0 .functor BUFZ 8, v0000028ded970640_0, C4<00000000>, C4<00000000>, C4<00000000>;
-L_0000028ded903500 .functor BUFZ 32, v0000028ded970820_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
-L_0000028ded9027e0 .functor BUFZ 1, v0000028ded96fa60_0, C4<0>, C4<0>, C4<0>;
-v0000028ded900080_0 .var "REGISTER_TEST", 31 0;
-v0000028ded8ffc20_0 .net *"_ivl_0", 31 0, L_0000028ded975730; 1 drivers
-v0000028ded900620_0 .net *"_ivl_10", 6 0, L_0000028ded973e30; 1 drivers
-L_0000028ded9803e8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
-v0000028ded8ff7c0_0 .net *"_ivl_13", 1 0, L_0000028ded9803e8; 1 drivers
-v0000028ded8ffe00_0 .net *"_ivl_17", 0 0, L_0000028ded975550; 1 drivers
-v0000028ded8ff860_0 .net *"_ivl_18", 19 0, L_0000028ded9752d0; 1 drivers
-v0000028ded970460_0 .net *"_ivl_2", 6 0, L_0000028ded973c50; 1 drivers
-v0000028ded970780_0 .net *"_ivl_21", 10 0, L_0000028ded975410; 1 drivers
-v0000028ded9706e0_0 .net *"_ivl_22", 30 0, L_0000028ded9754b0; 1 drivers
-L_0000028ded980430 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
-v0000028ded96f100_0 .net *"_ivl_27", 0 0, L_0000028ded980430; 1 drivers
-v0000028ded970e60_0 .net *"_ivl_29", 0 0, L_0000028ded974150; 1 drivers
-v0000028ded96f920_0 .net *"_ivl_30", 19 0, L_0000028ded9746f0; 1 drivers
-v0000028ded9703c0_0 .net *"_ivl_33", 10 0, L_0000028ded974290; 1 drivers
-v0000028ded970500_0 .net *"_ivl_34", 30 0, L_0000028ded9d8a50; 1 drivers
-L_0000028ded980478 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
-v0000028ded96fb00_0 .net *"_ivl_39", 0 0, L_0000028ded980478; 1 drivers
-L_0000028ded9803a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
-v0000028ded96fec0_0 .net *"_ivl_5", 1 0, L_0000028ded9803a0; 1 drivers
-v0000028ded9708c0_0 .net *"_ivl_8", 31 0, L_0000028ded973d90; 1 drivers
-v0000028ded970a00_0 .var "alu_out", 31 0;
-v0000028ded96f6a0_0 .var "b_imm", 12 0;
-v0000028ded96ff60_0 .net "clock", 0 0, v0000028ded973930_0; alias, 1 drivers
-v0000028ded96f560_0 .var "funct3", 2 0;
-v0000028ded96fce0_0 .var "funct7", 6 0;
-v0000028ded9705a0_0 .var/i "i", 31 0;
-v0000028ded9700a0_0 .var "i_imm", 11 0;
-v0000028ded96f600_0 .net "i_imm_sext", 31 0, L_0000028ded975690; 1 drivers
-v0000028ded970000_0 .net "iaddr", 31 0, v0000028ded970320_0; alias, 1 drivers
-v0000028ded9701e0_0 .net "inst", 31 0, L_0000028ded974c90; alias, 1 drivers
-v0000028ded970aa0_0 .var "j_imm", 20 0;
-v0000028ded96f740_0 .var "opcode", 6 0;
-v0000028ded96f7e0_0 .var "pc", 31 0;
-v0000028ded970140_0 .var "pc_p4", 31 0;
-v0000028ded96fe20_0 .net "raddr", 31 0, v0000028ded96f1a0_0; alias, 1 drivers
-v0000028ded970280_0 .var "rd", 4 0;
-v0000028ded970b40_0 .net "rdata", 31 0, L_0000028ded973b10; alias, 1 drivers
-v0000028ded970320_0 .var "reg_iaddr", 31 0;
-v0000028ded96f880_0 .var "reg_inst", 31 0;
-v0000028ded96f1a0_0 .var "reg_raddr", 31 0;
-v0000028ded970640_0 .var "reg_tx_data", 7 0;
-v0000028ded96f2e0_0 .var "reg_tx_start", 0 0;
-v0000028ded970820_0 .var "reg_wdata", 31 0;
-v0000028ded96fa60_0 .var "reg_wen", 0 0;
-v0000028ded970be0 .array "register", 0 31, 31 0;
-v0000028ded96fba0_0 .var "rs1", 4 0;
-v0000028ded96f9c0_0 .net "rs1_data", 31 0, L_0000028ded9030a0; 1 drivers
-v0000028ded96fd80_0 .var "rs2", 4 0;
-v0000028ded970960_0 .net "rs2_data", 31 0, L_0000028ded902af0; 1 drivers
-v0000028ded970c80_0 .var "s_imm", 11 0;
-v0000028ded970d20_0 .net "s_imm_sext", 31 0, L_0000028ded9d8e10; 1 drivers
-v0000028ded970dc0_0 .var "stage", 3 0;
-v0000028ded970f00_0 .net "tx_data", 7 0, L_0000028ded9033b0; alias, 1 drivers
-v0000028ded96f060_0 .net "tx_start", 0 0, L_0000028ded902930; alias, 1 drivers
-v0000028ded96f240_0 .var "u_imm", 31 0;
-v0000028ded96f380_0 .net "wdata", 31 0, L_0000028ded903500; alias, 1 drivers
-v0000028ded96f420_0 .net "wen", 0 0, L_0000028ded9027e0; alias, 1 drivers
-E_0000028ded909700 .event posedge, v0000028ded96ff60_0;
-L_0000028ded975730 .array/port v0000028ded970be0, L_0000028ded973c50;
-L_0000028ded973c50 .concat [ 5 2 0 0], v0000028ded96fba0_0, L_0000028ded9803a0;
-L_0000028ded973d90 .array/port v0000028ded970be0, L_0000028ded973e30;
-L_0000028ded973e30 .concat [ 5 2 0 0], v0000028ded96fd80_0, L_0000028ded9803e8;
-L_0000028ded975550 .part v0000028ded9700a0_0, 11, 1;
-LS_0000028ded9752d0_0_0 .concat [ 1 1 1 1], L_0000028ded975550, L_0000028ded975550, L_0000028ded975550, L_0000028ded975550;
-LS_0000028ded9752d0_0_4 .concat [ 1 1 1 1], L_0000028ded975550, L_0000028ded975550, L_0000028ded975550, L_0000028ded975550;
-LS_0000028ded9752d0_0_8 .concat [ 1 1 1 1], L_0000028ded975550, L_0000028ded975550, L_0000028ded975550, L_0000028ded975550;
-LS_0000028ded9752d0_0_12 .concat [ 1 1 1 1], L_0000028ded975550, L_0000028ded975550, L_0000028ded975550, L_0000028ded975550;
-LS_0000028ded9752d0_0_16 .concat [ 1 1 1 1], L_0000028ded975550, L_0000028ded975550, L_0000028ded975550, L_0000028ded975550;
-LS_0000028ded9752d0_1_0 .concat [ 4 4 4 4], LS_0000028ded9752d0_0_0, LS_0000028ded9752d0_0_4, LS_0000028ded9752d0_0_8, LS_0000028ded9752d0_0_12;
-LS_0000028ded9752d0_1_4 .concat [ 4 0 0 0], LS_0000028ded9752d0_0_16;
-L_0000028ded9752d0 .concat [ 16 4 0 0], LS_0000028ded9752d0_1_0, LS_0000028ded9752d0_1_4;
-L_0000028ded975410 .part v0000028ded9700a0_0, 0, 11;
-L_0000028ded9754b0 .concat [ 11 20 0 0], L_0000028ded975410, L_0000028ded9752d0;
-L_0000028ded975690 .concat [ 31 1 0 0], L_0000028ded9754b0, L_0000028ded980430;
-L_0000028ded974150 .part v0000028ded970c80_0, 11, 1;
-LS_0000028ded9746f0_0_0 .concat [ 1 1 1 1], L_0000028ded974150, L_0000028ded974150, L_0000028ded974150, L_0000028ded974150;
-LS_0000028ded9746f0_0_4 .concat [ 1 1 1 1], L_0000028ded974150, L_0000028ded974150, L_0000028ded974150, L_0000028ded974150;
-LS_0000028ded9746f0_0_8 .concat [ 1 1 1 1], L_0000028ded974150, L_0000028ded974150, L_0000028ded974150, L_0000028ded974150;
-LS_0000028ded9746f0_0_12 .concat [ 1 1 1 1], L_0000028ded974150, L_0000028ded974150, L_0000028ded974150, L_0000028ded974150;
-LS_0000028ded9746f0_0_16 .concat [ 1 1 1 1], L_0000028ded974150, L_0000028ded974150, L_0000028ded974150, L_0000028ded974150;
-LS_0000028ded9746f0_1_0 .concat [ 4 4 4 4], LS_0000028ded9746f0_0_0, LS_0000028ded9746f0_0_4, LS_0000028ded9746f0_0_8, LS_0000028ded9746f0_0_12;
-LS_0000028ded9746f0_1_4 .concat [ 4 0 0 0], LS_0000028ded9746f0_0_16;
-L_0000028ded9746f0 .concat [ 16 4 0 0], LS_0000028ded9746f0_1_0, LS_0000028ded9746f0_1_4;
-L_0000028ded974290 .part v0000028ded970c80_0, 0, 11;
-L_0000028ded9d8a50 .concat [ 11 20 0 0], L_0000028ded974290, L_0000028ded9746f0;
-L_0000028ded9d8e10 .concat [ 31 1 0 0], L_0000028ded9d8a50, L_0000028ded980478;
-S_0000028ded8c6d00 .scope module, "mem0" "MEMORY" 3 26, 5 1 0, S_0000028ded8e7f90;
+P_0000021801bec390 .param/l "ST_ACCESS" 1 4 59, +C4<00000000000000000000000000000011>;
+P_0000021801bec3c8 .param/l "ST_EX" 1 4 58, +C4<00000000000000000000000000000010>;
+P_0000021801bec400 .param/l "ST_ID" 1 4 57, +C4<00000000000000000000000000000001>;
+P_0000021801bec438 .param/l "ST_IF" 1 4 56, +C4<00000000000000000000000000000000>;
+P_0000021801bec470 .param/l "ST_WB" 1 4 60, +C4<00000000000000000000000000000100>;
+L_0000021801be1490 .functor BUFZ 32, L_0000021801c52b50, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+L_0000021801be1110 .functor BUFZ 32, L_0000021801c53190, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+L_0000021801be1a40 .functor BUFZ 1, v0000021801c4df60_0, C4<0>, C4<0>, C4<0>;
+L_0000021801be1420 .functor BUFZ 8, v0000021801c4ed20_0, C4<00000000>, C4<00000000>, C4<00000000>;
+L_0000021801be1b20 .functor BUFZ 32, v0000021801c4de20_0, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
+L_0000021801be1880 .functor BUFZ 1, v0000021801c4d920_0, C4<0>, C4<0>, C4<0>;
+v0000021801be51d0_0 .var "REGISTER_TEST", 31 0;
+v0000021801be5770_0 .net *"_ivl_0", 31 0, L_0000021801c52b50; 1 drivers
+v0000021801be5810_0 .net *"_ivl_10", 6 0, L_0000021801c51c50; 1 drivers
+L_0000021801c603e8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
+v0000021801be5a90_0 .net *"_ivl_13", 1 0, L_0000021801c603e8; 1 drivers
+v0000021801be5db0_0 .net *"_ivl_17", 0 0, L_0000021801c53230; 1 drivers
+v0000021801be5e50_0 .net *"_ivl_18", 19 0, L_0000021801c51890; 1 drivers
+v0000021801c4d4c0_0 .net *"_ivl_2", 6 0, L_0000021801c53690; 1 drivers
+v0000021801c4e960_0 .net *"_ivl_21", 10 0, L_0000021801c51930; 1 drivers
+v0000021801c4da60_0 .net *"_ivl_22", 30 0, L_0000021801c519d0; 1 drivers
+L_0000021801c60430 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000021801c4d560_0 .net *"_ivl_27", 0 0, L_0000021801c60430; 1 drivers
+v0000021801c4d600_0 .net *"_ivl_29", 0 0, L_0000021801c52010; 1 drivers
+v0000021801c4eb40_0 .net *"_ivl_30", 19 0, L_0000021801cb8550; 1 drivers
+v0000021801c4d420_0 .net *"_ivl_33", 10 0, L_0000021801cb9ef0; 1 drivers
+v0000021801c4e140_0 .net *"_ivl_34", 30 0, L_0000021801cb8d70; 1 drivers
+L_0000021801c60478 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
+v0000021801c4e640_0 .net *"_ivl_39", 0 0, L_0000021801c60478; 1 drivers
+L_0000021801c603a0 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>;
+v0000021801c4e6e0_0 .net *"_ivl_5", 1 0, L_0000021801c603a0; 1 drivers
+v0000021801c4e1e0_0 .net *"_ivl_8", 31 0, L_0000021801c53190; 1 drivers
+v0000021801c4e820_0 .var "alu_out", 31 0;
+v0000021801c4e780_0 .var "b_imm", 12 0;
+v0000021801c4e500_0 .net "clock", 0 0, v0000021801c51d90_0; alias, 1 drivers
+v0000021801c4e280_0 .var "funct3", 2 0;
+v0000021801c4e320_0 .var "funct7", 6 0;
+v0000021801c4e8c0_0 .var/i "i", 31 0;
+v0000021801c4d740_0 .var "i_imm", 11 0;
+v0000021801c4ea00_0 .net "i_imm_sext", 31 0, L_0000021801c51a70; 1 drivers
+v0000021801c4d7e0_0 .net "iaddr", 31 0, v0000021801c4e5a0_0; alias, 1 drivers
+v0000021801c4ef00_0 .net "inst", 31 0, L_0000021801c52ab0; alias, 1 drivers
+v0000021801c4ec80_0 .var "j_imm", 20 0;
+v0000021801c4e460_0 .var "opcode", 6 0;
+v0000021801c4d9c0_0 .var "pc", 31 0;
+v0000021801c4d880_0 .var "pc_p4", 31 0;
+v0000021801c4dc40_0 .net "raddr", 31 0, v0000021801c4d380_0; alias, 1 drivers
+v0000021801c4d6a0_0 .var "rd", 4 0;
+v0000021801c4e3c0_0 .net "rdata", 31 0, L_0000021801c52a10; alias, 1 drivers
+v0000021801c4e5a0_0 .var "reg_iaddr", 31 0;
+v0000021801c4db00_0 .var "reg_inst", 31 0;
+v0000021801c4d380_0 .var "reg_raddr", 31 0;
+v0000021801c4ed20_0 .var "reg_tx_data", 7 0;
+v0000021801c4df60_0 .var "reg_tx_start", 0 0;
+v0000021801c4eaa0_0 .var "reg_wb_data", 31 0;
+v0000021801c4ebe0_0 .var "reg_wb_wen", 0 0;
+v0000021801c4de20_0 .var "reg_wdata", 31 0;
+v0000021801c4d920_0 .var "reg_wen", 0 0;
+v0000021801c4ee60 .array "register", 0 31, 31 0;
+v0000021801c4e000_0 .var "rs1", 4 0;
+v0000021801c4edc0_0 .net "rs1_data", 31 0, L_0000021801be1490; 1 drivers
+v0000021801c4d060_0 .var "rs2", 4 0;
+v0000021801c4d100_0 .net "rs2_data", 31 0, L_0000021801be1110; 1 drivers
+v0000021801c4d2e0_0 .var "s_imm", 11 0;
+v0000021801c4dba0_0 .net "s_imm_sext", 31 0, L_0000021801cb9e50; 1 drivers
+v0000021801c4e0a0_0 .var "stage", 3 0;
+v0000021801c4d240_0 .net "tx_data", 7 0, L_0000021801be1420; alias, 1 drivers
+v0000021801c4d1a0_0 .net "tx_start", 0 0, L_0000021801be1a40; alias, 1 drivers
+v0000021801c4dce0_0 .var "u_imm", 31 0;
+v0000021801c4dd80_0 .net "wdata", 31 0, L_0000021801be1b20; alias, 1 drivers
+v0000021801c4dec0_0 .net "wen", 0 0, L_0000021801be1880; alias, 1 drivers
+E_0000021801be73e0 .event posedge, v0000021801c4e500_0;
+L_0000021801c52b50 .array/port v0000021801c4ee60, L_0000021801c53690;
+L_0000021801c53690 .concat [ 5 2 0 0], v0000021801c4e000_0, L_0000021801c603a0;
+L_0000021801c53190 .array/port v0000021801c4ee60, L_0000021801c51c50;
+L_0000021801c51c50 .concat [ 5 2 0 0], v0000021801c4d060_0, L_0000021801c603e8;
+L_0000021801c53230 .part v0000021801c4d740_0, 11, 1;
+LS_0000021801c51890_0_0 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
+LS_0000021801c51890_0_4 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
+LS_0000021801c51890_0_8 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
+LS_0000021801c51890_0_12 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
+LS_0000021801c51890_0_16 .concat [ 1 1 1 1], L_0000021801c53230, L_0000021801c53230, L_0000021801c53230, L_0000021801c53230;
+LS_0000021801c51890_1_0 .concat [ 4 4 4 4], LS_0000021801c51890_0_0, LS_0000021801c51890_0_4, LS_0000021801c51890_0_8, LS_0000021801c51890_0_12;
+LS_0000021801c51890_1_4 .concat [ 4 0 0 0], LS_0000021801c51890_0_16;
+L_0000021801c51890 .concat [ 16 4 0 0], LS_0000021801c51890_1_0, LS_0000021801c51890_1_4;
+L_0000021801c51930 .part v0000021801c4d740_0, 0, 11;
+L_0000021801c519d0 .concat [ 11 20 0 0], L_0000021801c51930, L_0000021801c51890;
+L_0000021801c51a70 .concat [ 31 1 0 0], L_0000021801c519d0, L_0000021801c60430;
+L_0000021801c52010 .part v0000021801c4d2e0_0, 11, 1;
+LS_0000021801cb8550_0_0 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
+LS_0000021801cb8550_0_4 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
+LS_0000021801cb8550_0_8 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
+LS_0000021801cb8550_0_12 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
+LS_0000021801cb8550_0_16 .concat [ 1 1 1 1], L_0000021801c52010, L_0000021801c52010, L_0000021801c52010, L_0000021801c52010;
+LS_0000021801cb8550_1_0 .concat [ 4 4 4 4], LS_0000021801cb8550_0_0, LS_0000021801cb8550_0_4, LS_0000021801cb8550_0_8, LS_0000021801cb8550_0_12;
+LS_0000021801cb8550_1_4 .concat [ 4 0 0 0], LS_0000021801cb8550_0_16;
+L_0000021801cb8550 .concat [ 16 4 0 0], LS_0000021801cb8550_1_0, LS_0000021801cb8550_1_4;
+L_0000021801cb9ef0 .part v0000021801c4d2e0_0, 0, 11;
+L_0000021801cb8d70 .concat [ 11 20 0 0], L_0000021801cb9ef0, L_0000021801cb8550;
+L_0000021801cb9e50 .concat [ 31 1 0 0], L_0000021801cb8d70, L_0000021801c60478;
+S_0000021801ba6d00 .scope module, "mem0" "MEMORY" 3 26, 5 1 0, S_0000021801bc85c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /INPUT 32 "raddr";
@@ -148,67 +150,67 @@ S_0000028ded8c6d00 .scope module, "mem0" "MEMORY" 3 26, 5 1 0, S_0000028ded8e7f9
.port_info 4 /INPUT 32 "wdata";
.port_info 5 /OUTPUT 32 "inst";
.port_info 6 /OUTPUT 32 "rdata";
-v0000028ded96fc40_0 .net *"_ivl_0", 7 0, L_0000028ded9755f0; 1 drivers
-v0000028ded96f4c0_0 .net *"_ivl_10", 31 0, L_0000028ded974b50; 1 drivers
-v0000028ded972150_0 .net *"_ivl_12", 7 0, L_0000028ded973a70; 1 drivers
-L_0000028ded9801f0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
-v0000028ded9712f0_0 .net/2u *"_ivl_14", 31 0, L_0000028ded9801f0; 1 drivers
-v0000028ded9719d0_0 .net *"_ivl_16", 31 0, L_0000028ded974790; 1 drivers
-v0000028ded972bf0_0 .net *"_ivl_18", 7 0, L_0000028ded975370; 1 drivers
-L_0000028ded980160 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
-v0000028ded972830_0 .net/2u *"_ivl_2", 31 0, L_0000028ded980160; 1 drivers
-L_0000028ded980238 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>;
-v0000028ded972dd0_0 .net/2u *"_ivl_20", 31 0, L_0000028ded980238; 1 drivers
-v0000028ded971bb0_0 .net *"_ivl_22", 31 0, L_0000028ded974bf0; 1 drivers
-v0000028ded972b50_0 .net *"_ivl_26", 7 0, L_0000028ded973bb0; 1 drivers
-L_0000028ded980280 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
-v0000028ded972c90_0 .net/2u *"_ivl_28", 31 0, L_0000028ded980280; 1 drivers
-v0000028ded972510_0 .net *"_ivl_30", 31 0, L_0000028ded974e70; 1 drivers
-v0000028ded972e70_0 .net *"_ivl_32", 7 0, L_0000028ded974f10; 1 drivers
-L_0000028ded9802c8 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
-v0000028ded972470_0 .net/2u *"_ivl_34", 31 0, L_0000028ded9802c8; 1 drivers
-v0000028ded972ab0_0 .net *"_ivl_36", 31 0, L_0000028ded975050; 1 drivers
-v0000028ded972d30_0 .net *"_ivl_38", 7 0, L_0000028ded974010; 1 drivers
-v0000028ded972330_0 .net *"_ivl_4", 31 0, L_0000028ded974510; 1 drivers
-L_0000028ded980310 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
-v0000028ded972f10_0 .net/2u *"_ivl_40", 31 0, L_0000028ded980310; 1 drivers
-v0000028ded9711b0_0 .net *"_ivl_42", 31 0, L_0000028ded9741f0; 1 drivers
-v0000028ded9725b0_0 .net *"_ivl_44", 7 0, L_0000028ded9745b0; 1 drivers
-L_0000028ded980358 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>;
-v0000028ded972790_0 .net/2u *"_ivl_46", 31 0, L_0000028ded980358; 1 drivers
-v0000028ded971070_0 .net *"_ivl_48", 31 0, L_0000028ded975190; 1 drivers
-v0000028ded972290_0 .net *"_ivl_6", 7 0, L_0000028ded974ab0; 1 drivers
-L_0000028ded9801a8 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
-v0000028ded971430_0 .net/2u *"_ivl_8", 31 0, L_0000028ded9801a8; 1 drivers
-v0000028ded972650_0 .net "clock", 0 0, v0000028ded973930_0; alias, 1 drivers
-v0000028ded972010_0 .var/i "i", 31 0;
-v0000028ded9726f0_0 .net "iaddr", 31 0, v0000028ded970320_0; alias, 1 drivers
-v0000028ded971750_0 .net "inst", 31 0, L_0000028ded974c90; alias, 1 drivers
-v0000028ded9720b0 .array "mem", 0 32, 7 0;
-v0000028ded9721f0_0 .net "raddr", 31 0, v0000028ded96f1a0_0; alias, 1 drivers
-v0000028ded971110_0 .net "rdata", 31 0, L_0000028ded973b10; alias, 1 drivers
-v0000028ded971250_0 .var "reg_raddr", 31 0;
-v0000028ded971390_0 .net "wdata", 31 0, L_0000028ded903500; alias, 1 drivers
-v0000028ded9714d0_0 .net "wen", 0 0, L_0000028ded9027e0; alias, 1 drivers
-L_0000028ded9755f0 .array/port v0000028ded9720b0, L_0000028ded974510;
-L_0000028ded974510 .arith/sum 32, v0000028ded970320_0, L_0000028ded980160;
-L_0000028ded974ab0 .array/port v0000028ded9720b0, L_0000028ded974b50;
-L_0000028ded974b50 .arith/sum 32, v0000028ded970320_0, L_0000028ded9801a8;
-L_0000028ded973a70 .array/port v0000028ded9720b0, L_0000028ded974790;
-L_0000028ded974790 .arith/sum 32, v0000028ded970320_0, L_0000028ded9801f0;
-L_0000028ded975370 .array/port v0000028ded9720b0, L_0000028ded974bf0;
-L_0000028ded974bf0 .arith/sum 32, v0000028ded970320_0, L_0000028ded980238;
-L_0000028ded974c90 .concat [ 8 8 8 8], L_0000028ded975370, L_0000028ded973a70, L_0000028ded974ab0, L_0000028ded9755f0;
-L_0000028ded973bb0 .array/port v0000028ded9720b0, L_0000028ded974e70;
-L_0000028ded974e70 .arith/sum 32, v0000028ded96f1a0_0, L_0000028ded980280;
-L_0000028ded974f10 .array/port v0000028ded9720b0, L_0000028ded975050;
-L_0000028ded975050 .arith/sum 32, v0000028ded96f1a0_0, L_0000028ded9802c8;
-L_0000028ded974010 .array/port v0000028ded9720b0, L_0000028ded9741f0;
-L_0000028ded9741f0 .arith/sum 32, v0000028ded96f1a0_0, L_0000028ded980310;
-L_0000028ded9745b0 .array/port v0000028ded9720b0, L_0000028ded975190;
-L_0000028ded975190 .arith/sum 32, v0000028ded96f1a0_0, L_0000028ded980358;
-L_0000028ded973b10 .concat [ 8 8 8 8], L_0000028ded9745b0, L_0000028ded974010, L_0000028ded974f10, L_0000028ded973bb0;
-S_0000028ded8df9d0 .scope module, "uart0" "UART" 3 11, 6 1 0, S_0000028ded8e7f90;
+v0000021801c4fed0_0 .net *"_ivl_0", 7 0, L_0000021801c528d0; 1 drivers
+v0000021801c4f250_0 .net *"_ivl_10", 31 0, L_0000021801c52e70; 1 drivers
+v0000021801c50330_0 .net *"_ivl_12", 7 0, L_0000021801c534b0; 1 drivers
+L_0000021801c601f0 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
+v0000021801c4f570_0 .net/2u *"_ivl_14", 31 0, L_0000021801c601f0; 1 drivers
+v0000021801c4fc50_0 .net *"_ivl_16", 31 0, L_0000021801c535f0; 1 drivers
+v0000021801c50bf0_0 .net *"_ivl_18", 7 0, L_0000021801c53410; 1 drivers
+L_0000021801c60160 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000021801c50e70_0 .net/2u *"_ivl_2", 31 0, L_0000021801c60160; 1 drivers
+L_0000021801c60238 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>;
+v0000021801c50b50_0 .net/2u *"_ivl_20", 31 0, L_0000021801c60238; 1 drivers
+v0000021801c4fe30_0 .net *"_ivl_22", 31 0, L_0000021801c51e30; 1 drivers
+v0000021801c50d30_0 .net *"_ivl_26", 7 0, L_0000021801c53370; 1 drivers
+L_0000021801c60280 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000021801c50150_0 .net/2u *"_ivl_28", 31 0, L_0000021801c60280; 1 drivers
+v0000021801c50470_0 .net *"_ivl_30", 31 0, L_0000021801c52290; 1 drivers
+v0000021801c505b0_0 .net *"_ivl_32", 7 0, L_0000021801c53050; 1 drivers
+L_0000021801c602c8 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0000021801c506f0_0 .net/2u *"_ivl_34", 31 0, L_0000021801c602c8; 1 drivers
+v0000021801c4f110_0 .net *"_ivl_36", 31 0, L_0000021801c52330; 1 drivers
+v0000021801c4f6b0_0 .net *"_ivl_38", 7 0, L_0000021801c526f0; 1 drivers
+v0000021801c50510_0 .net *"_ivl_4", 31 0, L_0000021801c52650; 1 drivers
+L_0000021801c60310 .functor BUFT 1, C4<00000000000000000000000000000010>, C4<0>, C4<0>, C4<0>;
+v0000021801c50650_0 .net/2u *"_ivl_40", 31 0, L_0000021801c60310; 1 drivers
+v0000021801c508d0_0 .net *"_ivl_42", 31 0, L_0000021801c52bf0; 1 drivers
+v0000021801c4f070_0 .net *"_ivl_44", 7 0, L_0000021801c53730; 1 drivers
+L_0000021801c60358 .functor BUFT 1, C4<00000000000000000000000000000011>, C4<0>, C4<0>, C4<0>;
+v0000021801c50ab0_0 .net/2u *"_ivl_46", 31 0, L_0000021801c60358; 1 drivers
+v0000021801c4f930_0 .net *"_ivl_48", 31 0, L_0000021801c52470; 1 drivers
+v0000021801c4f610_0 .net *"_ivl_6", 7 0, L_0000021801c52fb0; 1 drivers
+L_0000021801c601a8 .functor BUFT 1, C4<00000000000000000000000000000001>, C4<0>, C4<0>, C4<0>;
+v0000021801c4f750_0 .net/2u *"_ivl_8", 31 0, L_0000021801c601a8; 1 drivers
+v0000021801c50c90_0 .net "clock", 0 0, v0000021801c51d90_0; alias, 1 drivers
+v0000021801c50790_0 .var/i "i", 31 0;
+v0000021801c4ff70_0 .net "iaddr", 31 0, v0000021801c4e5a0_0; alias, 1 drivers
+v0000021801c500b0_0 .net "inst", 31 0, L_0000021801c52ab0; alias, 1 drivers
+v0000021801c4f7f0 .array "mem", 0 32, 7 0;
+v0000021801c4fcf0_0 .net "raddr", 31 0, v0000021801c4d380_0; alias, 1 drivers
+v0000021801c50a10_0 .net "rdata", 31 0, L_0000021801c52a10; alias, 1 drivers
+v0000021801c50970_0 .var "reg_raddr", 31 0;
+v0000021801c50dd0_0 .net "wdata", 31 0, L_0000021801be1b20; alias, 1 drivers
+v0000021801c50830_0 .net "wen", 0 0, L_0000021801be1880; alias, 1 drivers
+L_0000021801c528d0 .array/port v0000021801c4f7f0, L_0000021801c52650;
+L_0000021801c52650 .arith/sum 32, v0000021801c4e5a0_0, L_0000021801c60160;
+L_0000021801c52fb0 .array/port v0000021801c4f7f0, L_0000021801c52e70;
+L_0000021801c52e70 .arith/sum 32, v0000021801c4e5a0_0, L_0000021801c601a8;
+L_0000021801c534b0 .array/port v0000021801c4f7f0, L_0000021801c535f0;
+L_0000021801c535f0 .arith/sum 32, v0000021801c4e5a0_0, L_0000021801c601f0;
+L_0000021801c53410 .array/port v0000021801c4f7f0, L_0000021801c51e30;
+L_0000021801c51e30 .arith/sum 32, v0000021801c4e5a0_0, L_0000021801c60238;
+L_0000021801c52ab0 .concat [ 8 8 8 8], L_0000021801c53410, L_0000021801c534b0, L_0000021801c52fb0, L_0000021801c528d0;
+L_0000021801c53370 .array/port v0000021801c4f7f0, L_0000021801c52290;
+L_0000021801c52290 .arith/sum 32, v0000021801c4d380_0, L_0000021801c60280;
+L_0000021801c53050 .array/port v0000021801c4f7f0, L_0000021801c52330;
+L_0000021801c52330 .arith/sum 32, v0000021801c4d380_0, L_0000021801c602c8;
+L_0000021801c526f0 .array/port v0000021801c4f7f0, L_0000021801c52bf0;
+L_0000021801c52bf0 .arith/sum 32, v0000021801c4d380_0, L_0000021801c60310;
+L_0000021801c53730 .array/port v0000021801c4f7f0, L_0000021801c52470;
+L_0000021801c52470 .arith/sum 32, v0000021801c4d380_0, L_0000021801c60358;
+L_0000021801c52a10 .concat [ 8 8 8 8], L_0000021801c53730, L_0000021801c526f0, L_0000021801c53050, L_0000021801c53370;
+S_0000021801bc2830 .scope module, "uart0" "UART" 3 11, 6 1 0, S_0000021801bc85c0;
.timescale 0 0;
.port_info 0 /INPUT 1 "clock";
.port_info 1 /INPUT 8 "data_in";
@@ -216,90 +218,90 @@ S_0000028ded8df9d0 .scope module, "uart0" "UART" 3 11, 6 1 0, S_0000028ded8e7f90
.port_info 3 /OUTPUT 1 "tx_busy";
.port_info 4 /OUTPUT 1 "tx";
.port_info 5 /OUTPUT 1 "LED";
-P_0000028ded8c6fd0 .param/l "FPGA_FREQ" 1 6 13, +C4<00000000000000000000000000011011>;
-P_0000028ded8c7008 .param/l "S_END" 1 6 43, +C4<00000000000000000000000000000100>;
-P_0000028ded8c7040 .param/l "S_IDLE" 1 6 39, +C4<00000000000000000000000000000000>;
-P_0000028ded8c7078 .param/l "S_P" 1 6 42, +C4<00000000000000000000000000000011>;
-P_0000028ded8c70b0 .param/l "S_SEND" 1 6 41, +C4<00000000000000000000000000000010>;
-P_0000028ded8c70e8 .param/l "S_START" 1 6 40, +C4<00000000000000000000000000000001>;
-P_0000028ded8c7120 .param/l "TX_CLOCK_COUNT_MAX" 1 6 15, +C4<00000000000000000000000000000000000000000000000000000000011101001>;
-P_0000028ded8c7158 .param/l "UART_FREQ" 1 6 14, +C4<00000000000000011100001000000000>;
-L_0000028ded902c40 .functor BUFZ 1, v0000028ded971b10_0, C4<0>, C4<0>, C4<0>;
-L_0000028ded9028c0 .functor BUFZ 1, v0000028ded974830_0, C4<0>, C4<0>, C4<0>;
-v0000028ded971a70_0 .net "LED", 0 0, L_0000028ded902c40; alias, 1 drivers
-L_0000028ded9800d0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
-v0000028ded9723d0_0 .net *"_ivl_11", 26 0, L_0000028ded9800d0; 1 drivers
-L_0000028ded980118 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
-v0000028ded9728d0_0 .net/2u *"_ivl_12", 31 0, L_0000028ded980118; 1 drivers
-L_0000028ded980088 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
-v0000028ded972970_0 .net/2u *"_ivl_2", 31 0, L_0000028ded980088; 1 drivers
-v0000028ded971570_0 .net *"_ivl_8", 31 0, L_0000028ded9750f0; 1 drivers
-v0000028ded971610_0 .net "clock", 0 0, v0000028ded973930_0; alias, 1 drivers
-v0000028ded9716b0_0 .var "clock_count", 31 0;
-v0000028ded9717f0_0 .var "data", 7 0;
-v0000028ded972a10_0 .net "data_in", 7 0, L_0000028ded9033b0; alias, 1 drivers
-v0000028ded971b10_0 .var "led_flag", 0 0;
-v0000028ded971890_0 .var "local_in", 7 0;
-v0000028ded971930_0 .var "local_start", 0 0;
-v0000028ded971c50_0 .var "send_count", 3 0;
-v0000028ded971cf0_0 .net "start", 0 0, L_0000028ded902930; alias, 1 drivers
-v0000028ded971d90_0 .var "state", 4 0;
-v0000028ded971e30_0 .net "tx", 0 0, L_0000028ded9028c0; alias, 1 drivers
-v0000028ded971ed0_0 .net "tx_busy", 0 0, L_0000028ded9739d0; alias, 1 drivers
-v0000028ded971f70_0 .net "tx_clock", 0 0, L_0000028ded973cf0; 1 drivers
-v0000028ded974830_0 .var "tx_reg", 0 0;
-L_0000028ded973cf0 .cmp/eq 32, v0000028ded9716b0_0, L_0000028ded980088;
-L_0000028ded9750f0 .concat [ 5 27 0 0], v0000028ded971d90_0, L_0000028ded9800d0;
-L_0000028ded9739d0 .cmp/ne 32, L_0000028ded9750f0, L_0000028ded980118;
- .scope S_0000028ded8df9d0;
+P_0000021801ba6fd0 .param/l "FPGA_FREQ" 1 6 13, +C4<00000000000000000000000000011011>;
+P_0000021801ba7008 .param/l "S_END" 1 6 43, +C4<00000000000000000000000000000100>;
+P_0000021801ba7040 .param/l "S_IDLE" 1 6 39, +C4<00000000000000000000000000000000>;
+P_0000021801ba7078 .param/l "S_P" 1 6 42, +C4<00000000000000000000000000000011>;
+P_0000021801ba70b0 .param/l "S_SEND" 1 6 41, +C4<00000000000000000000000000000010>;
+P_0000021801ba70e8 .param/l "S_START" 1 6 40, +C4<00000000000000000000000000000001>;
+P_0000021801ba7120 .param/l "TX_CLOCK_COUNT_MAX" 1 6 15, +C4<00000000000000000000000000000000000000000000000000000000011101001>;
+P_0000021801ba7158 .param/l "UART_FREQ" 1 6 14, +C4<00000000000000011100001000000000>;
+L_0000021801be1260 .functor BUFZ 1, v0000021801c4f890_0, C4<0>, C4<0>, C4<0>;
+L_0000021801be13b0 .functor BUFZ 1, v0000021801c52790_0, C4<0>, C4<0>, C4<0>;
+v0000021801c4f1b0_0 .net "LED", 0 0, L_0000021801be1260; alias, 1 drivers
+L_0000021801c600d0 .functor BUFT 1, C4<000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000021801c4fd90_0 .net *"_ivl_11", 26 0, L_0000021801c600d0; 1 drivers
+L_0000021801c60118 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000021801c501f0_0 .net/2u *"_ivl_12", 31 0, L_0000021801c60118; 1 drivers
+L_0000021801c60088 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
+v0000021801c50f10_0 .net/2u *"_ivl_2", 31 0, L_0000021801c60088; 1 drivers
+v0000021801c4f2f0_0 .net *"_ivl_8", 31 0, L_0000021801c52830; 1 drivers
+v0000021801c4f9d0_0 .net "clock", 0 0, v0000021801c51d90_0; alias, 1 drivers
+v0000021801c4f390_0 .var "clock_count", 31 0;
+v0000021801c4f430_0 .var "data", 7 0;
+v0000021801c4f4d0_0 .net "data_in", 7 0, L_0000021801be1420; alias, 1 drivers
+v0000021801c4f890_0 .var "led_flag", 0 0;
+v0000021801c4fa70_0 .var "local_in", 7 0;
+v0000021801c4fb10_0 .var "local_start", 0 0;
+v0000021801c4fbb0_0 .var "send_count", 3 0;
+v0000021801c50010_0 .net "start", 0 0, L_0000021801be1a40; alias, 1 drivers
+v0000021801c50290_0 .var "state", 4 0;
+v0000021801c503d0_0 .net "tx", 0 0, L_0000021801be13b0; alias, 1 drivers
+v0000021801c52510_0 .net "tx_busy", 0 0, L_0000021801c52dd0; alias, 1 drivers
+v0000021801c532d0_0 .net "tx_clock", 0 0, L_0000021801c52150; 1 drivers
+v0000021801c52790_0 .var "tx_reg", 0 0;
+L_0000021801c52150 .cmp/eq 32, v0000021801c4f390_0, L_0000021801c60088;
+L_0000021801c52830 .concat [ 5 27 0 0], v0000021801c50290_0, L_0000021801c600d0;
+L_0000021801c52dd0 .cmp/ne 32, L_0000021801c52830, L_0000021801c60118;
+ .scope S_0000021801bc2830;
T_0 ;
%pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded9716b0_0, 0, 32;
+ %store/vec4 v0000021801c4f390_0, 0, 32;
%end;
.thread T_0;
- .scope S_0000028ded8df9d0;
+ .scope S_0000021801bc2830;
T_1 ;
- %wait E_0000028ded909700;
- %load/vec4 v0000028ded9716b0_0;
+ %wait E_0000021801be73e0;
+ %load/vec4 v0000021801c4f390_0;
%pad/u 65;
%cmpi/e 233, 0, 65;
%jmp/0xz T_1.0, 4;
%pushi/vec4 0, 0, 32;
- %assign/vec4 v0000028ded9716b0_0, 0;
- %load/vec4 v0000028ded971b10_0;
+ %assign/vec4 v0000021801c4f390_0, 0;
+ %load/vec4 v0000021801c4f890_0;
%inv;
- %assign/vec4 v0000028ded971b10_0, 0;
+ %assign/vec4 v0000021801c4f890_0, 0;
%jmp T_1.1;
T_1.0 ;
- %load/vec4 v0000028ded9716b0_0;
+ %load/vec4 v0000021801c4f390_0;
%addi 1, 0, 32;
- %assign/vec4 v0000028ded9716b0_0, 0;
+ %assign/vec4 v0000021801c4f390_0, 0;
T_1.1 ;
%jmp T_1;
.thread T_1;
- .scope S_0000028ded8df9d0;
+ .scope S_0000021801bc2830;
T_2 ;
- %wait E_0000028ded909700;
- %load/vec4 v0000028ded972a10_0;
- %assign/vec4 v0000028ded971890_0, 0;
- %load/vec4 v0000028ded971cf0_0;
- %assign/vec4 v0000028ded971930_0, 0;
+ %wait E_0000021801be73e0;
+ %load/vec4 v0000021801c4f4d0_0;
+ %assign/vec4 v0000021801c4fa70_0, 0;
+ %load/vec4 v0000021801c50010_0;
+ %assign/vec4 v0000021801c4fb10_0, 0;
%jmp T_2;
.thread T_2;
- .scope S_0000028ded8df9d0;
+ .scope S_0000021801bc2830;
T_3 ;
%pushi/vec4 0, 0, 5;
- %store/vec4 v0000028ded971d90_0, 0, 5;
+ %store/vec4 v0000021801c50290_0, 0, 5;
%pushi/vec4 0, 0, 4;
- %store/vec4 v0000028ded971c50_0, 0, 4;
+ %store/vec4 v0000021801c4fbb0_0, 0, 4;
%pushi/vec4 1, 0, 1;
- %store/vec4 v0000028ded974830_0, 0, 1;
+ %store/vec4 v0000021801c52790_0, 0, 1;
%end;
.thread T_3;
- .scope S_0000028ded8df9d0;
+ .scope S_0000021801bc2830;
T_4 ;
- %wait E_0000028ded909700;
- %load/vec4 v0000028ded971d90_0;
+ %wait E_0000021801be73e0;
+ %load/vec4 v0000021801c50290_0;
%dup/vec4;
%pushi/vec4 0, 0, 5;
%cmp/u;
@@ -322,258 +324,262 @@ T_4 ;
%jmp/1 T_4.4, 6;
%jmp T_4.5;
T_4.0 ;
- %load/vec4 v0000028ded971f70_0;
+ %load/vec4 v0000021801c532d0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.6, 8;
- %load/vec4 v0000028ded971930_0;
+ %load/vec4 v0000021801c4fb10_0;
%flag_set/vec4 8;
%jmp/0xz T_4.8, 8;
%pushi/vec4 1, 0, 1;
- %assign/vec4 v0000028ded974830_0, 0;
+ %assign/vec4 v0000021801c52790_0, 0;
%pushi/vec4 1, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
%jmp T_4.9;
T_4.8 ;
%pushi/vec4 1, 0, 1;
- %assign/vec4 v0000028ded974830_0, 0;
+ %assign/vec4 v0000021801c52790_0, 0;
%pushi/vec4 0, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
T_4.9 ;
T_4.6 ;
%jmp T_4.5;
T_4.1 ;
- %load/vec4 v0000028ded971f70_0;
+ %load/vec4 v0000021801c532d0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.10, 8;
%pushi/vec4 0, 0, 1;
- %assign/vec4 v0000028ded974830_0, 0;
- %load/vec4 v0000028ded971890_0;
- %assign/vec4 v0000028ded9717f0_0, 0;
+ %assign/vec4 v0000021801c52790_0, 0;
+ %load/vec4 v0000021801c4fa70_0;
+ %assign/vec4 v0000021801c4f430_0, 0;
%pushi/vec4 0, 0, 4;
- %assign/vec4 v0000028ded971c50_0, 0;
+ %assign/vec4 v0000021801c4fbb0_0, 0;
%pushi/vec4 2, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
%jmp T_4.11;
T_4.10 ;
%pushi/vec4 0, 0, 1;
- %assign/vec4 v0000028ded974830_0, 0;
+ %assign/vec4 v0000021801c52790_0, 0;
%pushi/vec4 1, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
T_4.11 ;
%jmp T_4.5;
T_4.2 ;
- %load/vec4 v0000028ded971f70_0;
+ %load/vec4 v0000021801c532d0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.12, 8;
- %load/vec4 v0000028ded9717f0_0;
- %load/vec4 v0000028ded971c50_0;
+ %load/vec4 v0000021801c4f430_0;
+ %load/vec4 v0000021801c4fbb0_0;
%part/u 1;
- %assign/vec4 v0000028ded974830_0, 0;
- %load/vec4 v0000028ded971c50_0;
+ %assign/vec4 v0000021801c52790_0, 0;
+ %load/vec4 v0000021801c4fbb0_0;
%cmpi/e 7, 0, 4;
%jmp/0xz T_4.14, 4;
%pushi/vec4 3, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
%jmp T_4.15;
T_4.14 ;
- %load/vec4 v0000028ded971c50_0;
+ %load/vec4 v0000021801c4fbb0_0;
%addi 1, 0, 4;
- %assign/vec4 v0000028ded971c50_0, 0;
+ %assign/vec4 v0000021801c4fbb0_0, 0;
%pushi/vec4 2, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
T_4.15 ;
%jmp T_4.13;
T_4.12 ;
- %load/vec4 v0000028ded9717f0_0;
- %load/vec4 v0000028ded971c50_0;
+ %load/vec4 v0000021801c4f430_0;
+ %load/vec4 v0000021801c4fbb0_0;
%part/u 1;
- %assign/vec4 v0000028ded974830_0, 0;
+ %assign/vec4 v0000021801c52790_0, 0;
%pushi/vec4 2, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
T_4.13 ;
%jmp T_4.5;
T_4.3 ;
- %load/vec4 v0000028ded971f70_0;
+ %load/vec4 v0000021801c532d0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.16, 8;
%pushi/vec4 1, 0, 1;
- %assign/vec4 v0000028ded974830_0, 0;
+ %assign/vec4 v0000021801c52790_0, 0;
%pushi/vec4 4, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
%jmp T_4.17;
T_4.16 ;
%pushi/vec4 1, 0, 1;
- %assign/vec4 v0000028ded974830_0, 0;
+ %assign/vec4 v0000021801c52790_0, 0;
%pushi/vec4 3, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
T_4.17 ;
%jmp T_4.5;
T_4.4 ;
- %load/vec4 v0000028ded971f70_0;
+ %load/vec4 v0000021801c532d0_0;
%flag_set/vec4 8;
%jmp/0xz T_4.18, 8;
%pushi/vec4 1, 0, 1;
- %assign/vec4 v0000028ded974830_0, 0;
+ %assign/vec4 v0000021801c52790_0, 0;
%pushi/vec4 0, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
%jmp T_4.19;
T_4.18 ;
%pushi/vec4 1, 0, 1;
- %assign/vec4 v0000028ded974830_0, 0;
+ %assign/vec4 v0000021801c52790_0, 0;
%pushi/vec4 4, 0, 5;
- %assign/vec4 v0000028ded971d90_0, 0;
+ %assign/vec4 v0000021801c50290_0, 0;
T_4.19 ;
%jmp T_4.5;
T_4.5 ;
%pop/vec4 1;
%jmp T_4;
.thread T_4;
- .scope S_0000028ded8c6d00;
+ .scope S_0000021801ba6d00;
T_5 ;
%pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded972010_0, 0, 32;
+ %store/vec4 v0000021801c50790_0, 0, 32;
T_5.0 ;
- %load/vec4 v0000028ded972010_0;
+ %load/vec4 v0000021801c50790_0;
%cmpi/s 64, 0, 32;
%jmp/0xz T_5.1, 5;
%pushi/vec4 0, 0, 8;
- %ix/getv/s 3, v0000028ded972010_0;
+ %ix/getv/s 3, v0000021801c50790_0;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded9720b0, 0, 4;
- %load/vec4 v0000028ded972010_0;
+ %assign/vec4/a/d v0000021801c4f7f0, 0, 4;
+ %load/vec4 v0000021801c50790_0;
%addi 1, 0, 32;
- %store/vec4 v0000028ded972010_0, 0, 32;
+ %store/vec4 v0000021801c50790_0, 0, 32;
%jmp T_5.0;
T_5.1 ;
- %pushi/vec4 0, 0, 8;
+ %pushi/vec4 221, 0, 8;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded9720b0, 0, 4;
- %pushi/vec4 32, 0, 8;
- %ix/load 3, 1, 0;
- %flag_set/imm 4, 0;
- %ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded9720b0, 0, 4;
- %pushi/vec4 162, 0, 8;
- %ix/load 3, 2, 0;
- %flag_set/imm 4, 0;
- %ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded9720b0, 0, 4;
- %pushi/vec4 35, 0, 8;
- %ix/load 3, 3, 0;
- %flag_set/imm 4, 0;
- %ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded9720b0, 0, 4;
+ %assign/vec4/a/d v0000021801c4f7f0, 0, 4;
%pushi/vec4 0, 0, 8;
- %ix/load 3, 0, 0;
- %flag_set/imm 4, 0;
- %ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded9720b0, 0, 4;
- %pushi/vec4 32, 0, 8;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded9720b0, 0, 4;
- %pushi/vec4 162, 0, 8;
+ %assign/vec4/a/d v0000021801c4f7f0, 0, 4;
+ %pushi/vec4 2, 0, 8;
%ix/load 3, 2, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded9720b0, 0, 4;
- %pushi/vec4 35, 0, 8;
+ %assign/vec4/a/d v0000021801c4f7f0, 0, 4;
+ %pushi/vec4 55, 0, 8;
%ix/load 3, 3, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded9720b0, 0, 4;
+ %assign/vec4/a/d v0000021801c4f7f0, 0, 4;
+ %pushi/vec4 3, 0, 8;
+ %ix/load 3, 4, 0;
+ %flag_set/imm 4, 0;
+ %ix/load 4, 0, 0; Constant delay
+ %assign/vec4/a/d v0000021801c4f7f0, 0, 4;
+ %pushi/vec4 50, 0, 8;
+ %ix/load 3, 5, 0;
+ %flag_set/imm 4, 0;
+ %ix/load 4, 0, 0; Constant delay
+ %assign/vec4/a/d v0000021801c4f7f0, 0, 4;
+ %pushi/vec4 2, 0, 8;
+ %ix/load 3, 6, 0;
+ %flag_set/imm 4, 0;
+ %ix/load 4, 0, 0; Constant delay
+ %assign/vec4/a/d v0000021801c4f7f0, 0, 4;
+ %pushi/vec4 19, 0, 8;
+ %ix/load 3, 7, 0;
+ %flag_set/imm 4, 0;
+ %ix/load 4, 0, 0; Constant delay
+ %assign/vec4/a/d v0000021801c4f7f0, 0, 4;
%pushi/vec4 0, 0, 32;
- %assign/vec4 v0000028ded971250_0, 0;
+ %assign/vec4 v0000021801c50970_0, 0;
%end;
.thread T_5;
- .scope S_0000028ded8c6d00;
+ .scope S_0000021801ba6d00;
T_6 ;
- %wait E_0000028ded909700;
- %load/vec4 v0000028ded9714d0_0;
+ %wait E_0000021801be73e0;
+ %load/vec4 v0000021801c50830_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_6.0, 4;
- %load/vec4 v0000028ded971390_0;
+ %load/vec4 v0000021801c50dd0_0;
%parti/s 8, 0, 2;
- %ix/getv 4, v0000028ded9721f0_0;
- %store/vec4a v0000028ded9720b0, 4, 0;
- %load/vec4 v0000028ded971390_0;
+ %ix/getv 4, v0000021801c4fcf0_0;
+ %store/vec4a v0000021801c4f7f0, 4, 0;
+ %load/vec4 v0000021801c50dd0_0;
%parti/s 8, 8, 5;
- %load/vec4 v0000028ded9721f0_0;
+ %load/vec4 v0000021801c4fcf0_0;
%addi 1, 0, 32;
%ix/vec4 4;
- %store/vec4a v0000028ded9720b0, 4, 0;
- %load/vec4 v0000028ded971390_0;
+ %store/vec4a v0000021801c4f7f0, 4, 0;
+ %load/vec4 v0000021801c50dd0_0;
%parti/s 8, 16, 6;
- %load/vec4 v0000028ded9721f0_0;
+ %load/vec4 v0000021801c4fcf0_0;
%addi 2, 0, 32;
%ix/vec4 4;
- %store/vec4a v0000028ded9720b0, 4, 0;
- %load/vec4 v0000028ded971390_0;
+ %store/vec4a v0000021801c4f7f0, 4, 0;
+ %load/vec4 v0000021801c50dd0_0;
%parti/s 8, 24, 6;
- %load/vec4 v0000028ded9721f0_0;
+ %load/vec4 v0000021801c4fcf0_0;
%addi 3, 0, 32;
%ix/vec4 4;
- %store/vec4a v0000028ded9720b0, 4, 0;
+ %store/vec4a v0000021801c4f7f0, 4, 0;
T_6.0 ;
%jmp T_6;
.thread T_6;
- .scope S_0000028ded8e8120;
+ .scope S_0000021801bc8750;
T_7 ;
%pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded9705a0_0, 0, 32;
+ %store/vec4 v0000021801c4e8c0_0, 0, 32;
T_7.0 ;
- %load/vec4 v0000028ded9705a0_0;
+ %load/vec4 v0000021801c4e8c0_0;
%cmpi/s 32, 0, 32;
%jmp/0xz T_7.1, 5;
%pushi/vec4 0, 0, 32;
- %ix/getv/s 3, v0000028ded9705a0_0;
+ %ix/getv/s 3, v0000021801c4e8c0_0;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded970be0, 0, 4;
- %load/vec4 v0000028ded9705a0_0;
+ %assign/vec4/a/d v0000021801c4ee60, 0, 4;
+ %load/vec4 v0000021801c4e8c0_0;
%addi 1, 0, 32;
- %store/vec4 v0000028ded9705a0_0, 0, 32;
+ %store/vec4 v0000021801c4e8c0_0, 0, 32;
%jmp T_7.0;
T_7.1 ;
%pushi/vec4 0, 0, 32;
%ix/load 3, 0, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded970be0, 0, 4;
+ %assign/vec4/a/d v0000021801c4ee60, 0, 4;
%pushi/vec4 0, 0, 32;
%ix/load 3, 1, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded970be0, 0, 4;
- %pushi/vec4 65, 0, 32;
+ %assign/vec4/a/d v0000021801c4ee60, 0, 4;
+ %pushi/vec4 0, 0, 32;
%ix/load 3, 2, 0;
%flag_set/imm 4, 0;
%ix/load 4, 0, 0; Constant delay
- %assign/vec4/a/d v0000028ded970be0, 0, 4;
+ %assign/vec4/a/d v0000021801c4ee60, 0, 4;
%pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded96f7e0_0, 0, 32;
- %pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded96f880_0, 0, 32;
- %pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded970320_0, 0, 32;
- %pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded96f1a0_0, 0, 32;
- %pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded970820_0, 0, 32;
+ %store/vec4 v0000021801c4eaa0_0, 0, 32;
%pushi/vec4 0, 0, 1;
- %store/vec4 v0000028ded96fa60_0, 0, 1;
+ %store/vec4 v0000021801c4ebe0_0, 0, 1;
%pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded970a00_0, 0, 32;
+ %store/vec4 v0000021801c4d9c0_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0000021801c4db00_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0000021801c4e5a0_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0000021801c4d380_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0000021801c4de20_0, 0, 32;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0000021801c4d920_0, 0, 1;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0000021801c4e820_0, 0, 32;
%pushi/vec4 0, 0, 4;
- %store/vec4 v0000028ded970dc0_0, 0, 4;
+ %store/vec4 v0000021801c4e0a0_0, 0, 4;
%end;
.thread T_7;
- .scope S_0000028ded8e8120;
+ .scope S_0000021801bc8750;
T_8 ;
- %wait E_0000028ded909700;
- %load/vec4 v0000028ded970dc0_0;
+ %wait E_0000021801be73e0;
+ %load/vec4 v0000021801c4e0a0_0;
%dup/vec4;
%pushi/vec4 0, 0, 4;
%cmp/u;
@@ -597,150 +603,206 @@ T_8 ;
%jmp T_8.5;
T_8.0 ;
%pushi/vec4 1, 0, 1;
- %assign/vec4 v0000028ded96f2e0_0, 0;
- %load/vec4 v0000028ded970b40_0;
+ %assign/vec4 v0000021801c4df60_0, 0;
+ %load/vec4 v0000021801c4e3c0_0;
%parti/s 8, 24, 6;
- %assign/vec4 v0000028ded970640_0, 0;
- %ix/load 4, 1, 0;
+ %assign/vec4 v0000021801c4ed20_0, 0;
+ %ix/load 4, 4, 0;
%flag_set/imm 4, 0;
- %load/vec4a v0000028ded970be0, 4;
- %assign/vec4 v0000028ded900080_0, 0;
- %load/vec4 v0000028ded9701e0_0;
- %assign/vec4 v0000028ded96f880_0, 0;
- %load/vec4 v0000028ded96f7e0_0;
+ %load/vec4a v0000021801c4ee60, 4;
+ %assign/vec4 v0000021801be51d0_0, 0;
+ %load/vec4 v0000021801c4ef00_0;
+ %assign/vec4 v0000021801c4db00_0, 0;
+ %load/vec4 v0000021801c4d9c0_0;
%addi 4, 0, 32;
- %assign/vec4 v0000028ded970140_0, 0;
+ %assign/vec4 v0000021801c4d880_0, 0;
%pushi/vec4 1, 0, 4;
- %assign/vec4 v0000028ded970dc0_0, 0;
+ %assign/vec4 v0000021801c4e0a0_0, 0;
%jmp T_8.5;
T_8.1 ;
- %load/vec4 v0000028ded96f880_0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 7, 0, 2;
- %store/vec4 v0000028ded96f740_0, 0, 7;
- %load/vec4 v0000028ded96f880_0;
+ %store/vec4 v0000021801c4e460_0, 0, 7;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 5, 7, 4;
- %store/vec4 v0000028ded970280_0, 0, 5;
- %load/vec4 v0000028ded96f880_0;
+ %store/vec4 v0000021801c4d6a0_0, 0, 5;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 3, 12, 5;
- %store/vec4 v0000028ded96f560_0, 0, 3;
- %load/vec4 v0000028ded96f880_0;
+ %store/vec4 v0000021801c4e280_0, 0, 3;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 5, 15, 5;
- %assign/vec4 v0000028ded96fba0_0, 0;
- %load/vec4 v0000028ded96f880_0;
+ %assign/vec4 v0000021801c4e000_0, 0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 5, 20, 6;
- %assign/vec4 v0000028ded96fd80_0, 0;
- %load/vec4 v0000028ded96f880_0;
+ %assign/vec4 v0000021801c4d060_0, 0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 7, 25, 6;
- %store/vec4 v0000028ded96fce0_0, 0, 7;
- %load/vec4 v0000028ded96f880_0;
+ %store/vec4 v0000021801c4e320_0, 0, 7;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 12, 20, 6;
- %assign/vec4 v0000028ded9700a0_0, 0;
- %load/vec4 v0000028ded96f880_0;
+ %assign/vec4 v0000021801c4d740_0, 0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 7, 25, 6;
- %load/vec4 v0000028ded96f880_0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 5, 7, 4;
%concat/vec4; draw_concat_vec4
- %assign/vec4 v0000028ded970c80_0, 0;
- %load/vec4 v0000028ded96f880_0;
+ %assign/vec4 v0000021801c4d2e0_0, 0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 7, 25, 6;
- %load/vec4 v0000028ded96f880_0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 5, 7, 4;
%concat/vec4; draw_concat_vec4
%pad/u 13;
- %store/vec4 v0000028ded96f6a0_0, 0, 13;
- %load/vec4 v0000028ded96f880_0;
+ %store/vec4 v0000021801c4e780_0, 0, 13;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 20, 12, 5;
%ix/load 4, 12, 0;
%flag_set/imm 4, 0;
- %store/vec4 v0000028ded96f240_0, 4, 20;
- %load/vec4 v0000028ded96f880_0;
+ %store/vec4 v0000021801c4dce0_0, 4, 20;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 1, 31, 6;
%replicate 12;
- %load/vec4 v0000028ded96f880_0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 8, 12, 5;
%concat/vec4; draw_concat_vec4
- %load/vec4 v0000028ded96f880_0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 1, 20, 6;
%concat/vec4; draw_concat_vec4
- %load/vec4 v0000028ded96f880_0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 6, 25, 6;
%concat/vec4; draw_concat_vec4
- %load/vec4 v0000028ded96f880_0;
+ %load/vec4 v0000021801c4db00_0;
%parti/s 4, 21, 6;
%concat/vec4; draw_concat_vec4
%concati/vec4 0, 0, 1;
%pad/u 21;
- %store/vec4 v0000028ded970aa0_0, 0, 21;
+ %store/vec4 v0000021801c4ec80_0, 0, 21;
%pushi/vec4 2, 0, 4;
- %assign/vec4 v0000028ded970dc0_0, 0;
+ %assign/vec4 v0000021801c4e0a0_0, 0;
%jmp T_8.5;
T_8.2 ;
- %load/vec4 v0000028ded96f740_0;
- %dup/vec4;
- %pushi/vec4 35, 0, 7;
- %cmp/u;
- %jmp/1 T_8.6, 6;
- %jmp T_8.7;
-T_8.6 ;
- %load/vec4 v0000028ded96f9c0_0;
- %load/vec4 v0000028ded970d20_0;
+ %load/vec4 v0000021801c4db00_0;
+ %pushi/vec4 28799, 0, 32;
+ %and;
+ %cmpi/e 8227, 0, 32;
+ %jmp/0xz T_8.6, 4;
+ %load/vec4 v0000021801c4edc0_0;
+ %load/vec4 v0000021801c4dba0_0;
%add;
- %store/vec4 v0000028ded970a00_0, 0, 32;
- %jmp T_8.7;
-T_8.7 ;
- %pop/vec4 1;
+ %store/vec4 v0000021801c4e820_0, 0, 32;
+T_8.6 ;
+ %load/vec4 v0000021801c4db00_0;
+ %pushi/vec4 28799, 0, 32;
+ %and;
+ %cmpi/e 8195, 0, 32;
+ %jmp/0xz T_8.8, 4;
+ %load/vec4 v0000021801c4edc0_0;
+ %load/vec4 v0000021801c4ea00_0;
+ %add;
+ %store/vec4 v0000021801c4e820_0, 0, 32;
+T_8.8 ;
+ %load/vec4 v0000021801c4db00_0;
+ %pushi/vec4 127, 0, 32;
+ %and;
+ %cmpi/e 55, 0, 32;
+ %jmp/0xz T_8.10, 4;
+ %load/vec4 v0000021801c4dce0_0;
+ %parti/s 20, 12, 5;
+ %ix/load 4, 12, 0;
+ %flag_set/imm 4, 0;
+ %store/vec4 v0000021801c4eaa0_0, 4, 20;
+ %pushi/vec4 1, 0, 1;
+ %store/vec4 v0000021801c4ebe0_0, 0, 1;
+T_8.10 ;
+ %load/vec4 v0000021801c4db00_0;
+ %pushi/vec4 28799, 0, 32;
+ %and;
+ %cmpi/e 19, 0, 32;
+ %jmp/0xz T_8.12, 4;
+ %load/vec4 v0000021801c4edc0_0;
+ %load/vec4 v0000021801c4ea00_0;
+ %add;
+ %store/vec4 v0000021801c4eaa0_0, 0, 32;
+ %pushi/vec4 1, 0, 1;
+ %store/vec4 v0000021801c4ebe0_0, 0, 1;
+T_8.12 ;
%pushi/vec4 3, 0, 4;
- %assign/vec4 v0000028ded970dc0_0, 0;
+ %assign/vec4 v0000021801c4e0a0_0, 0;
%jmp T_8.5;
T_8.3 ;
- %load/vec4 v0000028ded970a00_0;
- %store/vec4 v0000028ded96f1a0_0, 0, 32;
- %load/vec4 v0000028ded96f740_0;
- %pushi/vec4 35, 0, 7;
+ %load/vec4 v0000021801c4e820_0;
+ %store/vec4 v0000021801c4d380_0, 0, 32;
+ %load/vec4 v0000021801c4e460_0;
+ %pad/u 32;
+ %pushi/vec4 8227, 0, 32;
%cmp/e;
%flag_get/vec4 4;
- %store/vec4 v0000028ded96fa60_0, 0, 1;
- %load/vec4 v0000028ded970960_0;
- %store/vec4 v0000028ded970820_0, 0, 32;
+ %store/vec4 v0000021801c4d920_0, 0, 1;
+ %load/vec4 v0000021801c4d100_0;
+ %store/vec4 v0000021801c4de20_0, 0, 32;
%pushi/vec4 4, 0, 4;
- %assign/vec4 v0000028ded970dc0_0, 0;
+ %assign/vec4 v0000021801c4e0a0_0, 0;
%jmp T_8.5;
T_8.4 ;
- %load/vec4 v0000028ded970140_0;
- %store/vec4 v0000028ded96f7e0_0, 0, 32;
- %pushi/vec4 0, 0, 32;
- %store/vec4 v0000028ded970a00_0, 0, 32;
+ %load/vec4 v0000021801c4e460_0;
+ %pad/u 32;
+ %cmpi/e 8195, 0, 32;
+ %jmp/0xz T_8.14, 4;
+ %load/vec4 v0000021801c4e3c0_0;
+ %load/vec4 v0000021801c4d6a0_0;
+ %pad/u 7;
+ %ix/vec4 3;
+ %ix/load 4, 0, 0; Constant delay
+ %assign/vec4/a/d v0000021801c4ee60, 0, 4;
+T_8.14 ;
+ %load/vec4 v0000021801c4ebe0_0;
+ %pad/u 32;
+ %cmpi/e 1, 0, 32;
+ %jmp/0xz T_8.16, 4;
+ %load/vec4 v0000021801c4eaa0_0;
+ %load/vec4 v0000021801c4d6a0_0;
+ %pad/u 7;
+ %ix/vec4 3;
+ %ix/load 4, 0, 0; Constant delay
+ %assign/vec4/a/d v0000021801c4ee60, 0, 4;
+T_8.16 ;
%pushi/vec4 0, 0, 1;
- %store/vec4 v0000028ded96fa60_0, 0, 1;
- %load/vec4 v0000028ded970140_0;
- %store/vec4 v0000028ded970320_0, 0, 32;
+ %store/vec4 v0000021801c4ebe0_0, 0, 1;
+ %load/vec4 v0000021801c4d880_0;
+ %store/vec4 v0000021801c4d9c0_0, 0, 32;
+ %pushi/vec4 0, 0, 32;
+ %store/vec4 v0000021801c4e820_0, 0, 32;
+ %pushi/vec4 0, 0, 1;
+ %store/vec4 v0000021801c4d920_0, 0, 1;
+ %load/vec4 v0000021801c4d880_0;
+ %store/vec4 v0000021801c4e5a0_0, 0, 32;
%pushi/vec4 0, 0, 4;
- %assign/vec4 v0000028ded970dc0_0, 0;
+ %assign/vec4 v0000021801c4e0a0_0, 0;
%jmp T_8.5;
T_8.5 ;
%pop/vec4 1;
%jmp T_8;
.thread T_8;
- .scope S_0000028ded9179d0;
+ .scope S_0000021801ba52c0;
T_9 ;
%pushi/vec4 0, 0, 1;
- %store/vec4 v0000028ded973930_0, 0, 1;
+ %store/vec4 v0000021801c51d90_0, 0, 1;
%end;
.thread T_9;
- .scope S_0000028ded9179d0;
+ .scope S_0000021801ba52c0;
T_10 ;
%vpi_call 2 6 "$dumpfile", "tb_memory.vcd" {0 0 0};
- %vpi_call 2 7 "$dumpvars", 32'sb00000000000000000000000000000011, S_0000028ded9179d0 {0 0 0};
+ %vpi_call 2 7 "$dumpvars", 32'sb00000000000000000000000000000011, S_0000021801ba52c0 {0 0 0};
%delay 10000, 0;
%vpi_call 2 9 "$finish" {0 0 0};
%end;
.thread T_10;
- .scope S_0000028ded9179d0;
+ .scope S_0000021801ba52c0;
T_11 ;
%delay 1, 0;
- %load/vec4 v0000028ded973930_0;
+ %load/vec4 v0000021801c51d90_0;
%nor/r;
- %store/vec4 v0000028ded973930_0, 0, 1;
+ %store/vec4 v0000021801c51d90_0, 0, 1;
%jmp T_11;
.thread T_11;
# The file index is used to find the file name in the following table.
diff --git a/src/tb_memory.vcd b/src/tb_memory.vcd
index 9c7c0f8..e1792a5 100644
--- a/src/tb_memory.vcd
+++ b/src/tb_memory.vcd
@@ -1,5 +1,5 @@
$date
- Thu May 18 13:59:51 2023
+ Thu May 18 16:48:10 2023
$end
$version
Icarus Verilog
@@ -60,64 +60,66 @@ $var reg 32 I reg_inst [31:0] $end
$var reg 32 J reg_raddr [31:0] $end
$var reg 8 K reg_tx_data [7:0] $end
$var reg 1 L reg_tx_start $end
-$var reg 32 M reg_wdata [31:0] $end
-$var reg 1 N reg_wen $end
-$var reg 5 O rs1 [4:0] $end
-$var reg 5 P rs2 [4:0] $end
-$var reg 12 Q s_imm [11:0] $end
-$var reg 4 R stage [3:0] $end
-$var reg 32 S u_imm [31:0] $end
-$var integer 32 T i [31:0] $end
+$var reg 32 M reg_wb_data [31:0] $end
+$var reg 1 N reg_wb_wen $end
+$var reg 32 O reg_wdata [31:0] $end
+$var reg 1 P reg_wen $end
+$var reg 5 Q rs1 [4:0] $end
+$var reg 5 R rs2 [4:0] $end
+$var reg 12 S s_imm [11:0] $end
+$var reg 4 T stage [3:0] $end
+$var reg 32 U u_imm [31:0] $end
+$var integer 32 V i [31:0] $end
$upscope $end
$scope module mem0 $end
$var wire 1 $ clock $end
-$var wire 32 U iaddr [31:0] $end
-$var wire 32 V raddr [31:0] $end
-$var wire 32 W wdata [31:0] $end
+$var wire 32 W iaddr [31:0] $end
+$var wire 32 X raddr [31:0] $end
+$var wire 32 Y wdata [31:0] $end
$var wire 1 % wen $end
-$var wire 32 X rdata [31:0] $end
-$var wire 32 Y inst [31:0] $end
-$var reg 32 Z reg_raddr [31:0] $end
-$var integer 32 [ i [31:0] $end
+$var wire 32 Z rdata [31:0] $end
+$var wire 32 [ inst [31:0] $end
+$var reg 32 \ reg_raddr [31:0] $end
+$var integer 32 ] i [31:0] $end
$upscope $end
$scope module uart0 $end
$var wire 1 " LED $end
$var wire 1 $ clock $end
-$var wire 8 \ data_in [7:0] $end
+$var wire 8 ^ data_in [7:0] $end
$var wire 1 ' start $end
$var wire 1 ! tx $end
-$var wire 1 ] tx_clock $end
+$var wire 1 _ tx_clock $end
$var wire 1 ) tx_busy $end
-$var parameter 32 ^ FPGA_FREQ $end
-$var parameter 32 _ S_END $end
-$var parameter 32 ` S_IDLE $end
-$var parameter 32 a S_P $end
-$var parameter 32 b S_SEND $end
-$var parameter 32 c S_START $end
-$var parameter 65 d TX_CLOCK_COUNT_MAX $end
-$var parameter 32 e UART_FREQ $end
-$var reg 32 f clock_count [31:0] $end
-$var reg 8 g data [7:0] $end
-$var reg 1 h led_flag $end
-$var reg 8 i local_in [7:0] $end
-$var reg 1 j local_start $end
-$var reg 4 k send_count [3:0] $end
-$var reg 5 l state [4:0] $end
-$var reg 1 m tx_reg $end
+$var parameter 32 ` FPGA_FREQ $end
+$var parameter 32 a S_END $end
+$var parameter 32 b S_IDLE $end
+$var parameter 32 c S_P $end
+$var parameter 32 d S_SEND $end
+$var parameter 32 e S_START $end
+$var parameter 65 f TX_CLOCK_COUNT_MAX $end
+$var parameter 32 g UART_FREQ $end
+$var reg 32 h clock_count [31:0] $end
+$var reg 8 i data [7:0] $end
+$var reg 1 j led_flag $end
+$var reg 8 k local_in [7:0] $end
+$var reg 1 l local_start $end
+$var reg 4 m send_count [3:0] $end
+$var reg 5 n state [4:0] $end
+$var reg 1 o tx_reg $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
-b11100001000000000 e
-b11101001 d
-b1 c
-b10 b
-b11 a
-b0 `
-b100 _
-b11011 ^
+b11100001000000000 g
+b11101001 f
+b1 e
+b10 d
+b11 c
+b0 b
+b100 a
+b11011 `
b100 <
b0 ;
b1 :
@@ -127,29 +129,31 @@ b1 #
$end
#0
$dumpvars
-1m
-b0 l
-b0 k
+1o
+b0 n
+b0 m
+xl
+bx k
xj
bx i
-xh
-bx g
-b0 f
-1]
-bx \
-b1000000 [
-b0 Z
-b1000001010001000100011 Y
-b1000001010001000100011 X
+b0 h
+1_
+bx ^
+b1000000 ]
+b0 \
+b11011101000000000000001000110111 [
+b11011101000000000000001000110111 Z
+b0 Y
+b0 X
b0 W
-b0 V
-b0 U
-b100000 T
+b100000 V
+bx U
+b0 T
bx S
-b0 R
+bx R
bx Q
-bx P
-bx O
+0P
+b0 O
0N
b0 M
xL
@@ -170,18 +174,18 @@ b0 >
bx =
b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 7
b0 6
-b1000001010001000100011 5
+b11011101000000000000001000110111 5
b0 4
-b1000001010001000100011 3
+b11011101000000000000001000110111 3
b0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 2
b0 1
bx 0
bx /
bx .
b0 -
-b1000001010001000100011 ,
+b11011101000000000000001000110111 ,
b0 +
-b1000001010001000100011 *
+b11011101000000000000001000110111 *
0)
bx (
x'
@@ -192,370 +196,367 @@ x"
1!
$end
#1
-0]
-b1 f
-b1 R
+0_
+b1 h
+b1 T
b100 F
-b1000001010001000100011 I
+b11011101000000000000001000110111 I
b0 =
-b0 (
-b0 0
-b0 \
-b0 K
+b11011101 (
+b11011101 0
+b11011101 ^
+b11011101 K
1'
1L
1$
#2
0$
#3
-b100 2
-b10 7
-b10 R
-b100 Q
-b10 B
-b1000001 /
-b10 P
+b1111111111111111111110111000100 2
+b1111111111111111111110111010000 7
+b10 T
+b110111000100 S
+b110111010000 B
+b0 /
+b10000 R
b0 .
-b1 O
-1j
-b0 i
-b10 f
-b1010000000000010 C
-b1000001010xxxxxxxxxxxx S
-b100 ?
-b0 A
-b10 @
+b0 Q
+1l
+b11011101 k
+b10 h
+b100000000010111010000 C
+b11011101000000000000xxxxxxxxxxxx U
+b110111000100 ?
+b1101110 A
+b0 @
b100 G
-b100011 D
+b110111 D
1$
#4
0$
#5
-b11 f
-b11 R
-b100 >
+b11 h
+b11 T
+1N
+b11011101000000000000000000000000 M
1$
#6
0$
#7
-b100 R
-b100 f
-b1000001 &
-b1000001 1
-b1000001 W
-b1000001 M
-1%
-1N
-b0 *
-b0 3
-b0 X
-b100 +
-b100 4
-b100 J
-b100 V
+b100 T
+b100 h
1$
#8
0$
#9
-b101 f
-b0 R
-b0 ,
-b0 5
-b0 Y
+b101 h
+b0 T
+b11001100100000001000010011 ,
+b11001100100000001000010011 5
+b11001100100000001000010011 [
b100 -
b100 6
b100 H
-b100 U
-0%
-0N
-b0 >
+b100 W
b100 E
+0N
1$
#10
0$
#11
-b1 R
+b1 T
b1000 F
-b0 I
-b110 f
+b11001100100000001000010011 I
+b11011101000000000000000000000000 =
+b110 h
1$
#12
0$
#13
-b0 2
-b0 7
-b111 f
-b10 R
-b0 Q
-b0 B
-b0 /
-b0 P
-b0 O
-b0 C
-b0xxxxxxxxxxxx S
-b0 ?
-b0 @
-b0 G
-b0 D
+b100100 2
+b110011 7
+b111 h
+b10 T
+b100100 S
+b110011 B
+b10011 R
+b11011101000000000000000000000000 .
+b100 Q
+b100000100000110010 C
+b11001100100000xxxxxxxxxxxx U
+b100100 ?
+b1 A
+b10011 D
1$
#14
0$
#15
-b11 R
-b1000 f
+b11 T
+b1000 h
+1N
+b11011101000000000000000000110011 M
1$
#16
0$
#17
-b1001 f
-b100 R
-b0 &
-b0 1
-b0 W
-b0 M
-b1000001010001000100011 *
-b1000001010001000100011 3
-b1000001010001000100011 X
-b0 +
-b0 4
-b0 J
-b0 V
+b1001 h
+b100 T
1$
#18
0$
#19
-b0 R
-b1010 f
+b0 T
+b11011101000000000000000000110011 .
+b1010 h
+b0 ,
+b0 5
+b0 [
b1000 -
b1000 6
b1000 H
-b1000 U
+b1000 W
b1000 E
+0N
1$
#20
0$
#21
-b1011 f
-b1 R
+b1011 h
+b1 T
b1100 F
+b0 I
+b11011101000000000000000000110011 =
1$
#22
0$
#23
-b10 R
-b1100 f
+b0 2
+b0 7
+b10 T
+b0 S
+b0 B
+b0 R
+b0 .
+b0 Q
+b1100 h
+b0 C
+b0xxxxxxxxxxxx U
+b0 ?
+b0 A
+b0 G
+b0 D
1$
#24
0$
#25
-b1101 f
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0$
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@@ -564,16 +565,16 @@ b0xxxxxxxxxxxxxxxxxxxxxxxx I
#83
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@@ -582,39759 +583,35809 @@ bx D
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1$
#1444
0$
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-b10101 f
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0$
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-b100 R
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1$
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0$
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-b10111 f
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1$
#1450
0$
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-b1 R
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1$
#1452
0$
#1453
-b11001 f
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1$
#1454
0$
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-b11 R
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0$
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-b11011 f
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1$
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0$
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-b0 R
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1$
#1460
0$
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-b11101 f
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0$
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-b10 R
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#1464
0$
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-b11111 f
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1$
#1466
0$
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-b100 R
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1$
#1468
0$
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1$
#1470
0$
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0$
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-b100011 f
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1$
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0$
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-b11 R
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0$
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-b100101 f
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0$
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1$
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0$
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-b100111 f
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0$
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0$
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-b101001 f
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0$
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0$
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1$
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0$
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1$
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0$
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-b11 R
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0$
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-b101111 f
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0$
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1$
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0$
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0$
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0$
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-b110011 f
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#1506
0$
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#1508
0$
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1$
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0$
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#1512
0$
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1$
#1514
0$
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-b11 R
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#1516
0$
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-b111001 f
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0$
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1$
#1520
0$
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-b111011 f
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0$
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#1524
0$
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-b111101 f
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#1526
0$
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#1528
0$
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1$
#1530
0$
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#1532
0$
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1$
#1534
0$
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#1536
0$
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-b1000011 f
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0$
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1$
#1540
0$
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0$
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#1544
0$
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-b1000111 f
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#1546
0$
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1$
#1548
0$
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1$
#1550
0$
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#1552
0$
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1$
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0$
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0$
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-b1001101 f
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1$
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0$
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1$
#1560
0$
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-b1001111 f
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0$
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#1564
0$
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-b1010001 f
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#1566
0$
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1$
#1568
0$
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1$
#1570
0$
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#1572
0$
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1$
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0$
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-b11 R
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0$
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-b1010111 f
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0$
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1$
#1580
0$
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-b1011001 f
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0$
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0$
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-b1011011 f
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0$
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#1588
0$
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-b1011101 f
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1$
#1590
0$
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#1592
0$
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1$
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0$
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-b11 R
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0$
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0$
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1$
#1600
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#1601
-b1100011 f
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#1602
0$
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0$
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-b1100101 f
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#1606
0$
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#1608
0$
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1$
#1610
0$
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#1612
0$
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1$
#1614
0$
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-b11 R
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#1616
0$
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-b1101011 f
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1$
#1618
0$
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1$
#1620
0$
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-b1101101 f
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#1622
0$
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-b10 R
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#1624
0$
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-b1101111 f
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1$
#1626
0$
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1$
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0$
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1$
#1630
0$
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-b1 R
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1$
#1632
0$
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1$
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0$
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-b11 R
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#1636
0$
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#1638
0$
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1$
#1640
0$
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-b1110111 f
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#1642
0$
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#1644
0$
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-b1111001 f
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1$
#1646
0$
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-b100 R
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1$
#1648
0$
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1$
#1650
0$
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-b1 R
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#1652
0$
#1653
-b1111101 f
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1$
#1654
0$
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-b11 R
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#1656
0$
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-b1111111 f
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1$
#1658
0$
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1$
#1660
0$
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-b10000001 f
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#1662
0$
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#1664
0$
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-b10000011 f
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1$
#1666
0$
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1$
#1668
0$
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1$
#1670
0$
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-b1 R
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#1672
0$
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1$
#1674
0$
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-b11 R
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#1676
0$
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1$
#1678
0$
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1$
#1680
0$
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-b10001011 f
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0$
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-b10 R
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1$
#1684
0$
#1685
-b10001101 f
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1$
#1686
0$
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-b100 R
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1$
#1688
0$
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-b10001111 f
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1$
#1690
0$
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-b1 R
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1$
#1692
0$
#1693
-b10010001 f
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1$
#1694
0$
#1695
-b11 R
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1$
#1696
0$
#1697
-b10010011 f
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-xN
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1$
#1698
0$
#1699
-b0 R
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b1010101000 E
1$
#1700
0$
#1701
-b10010101 f
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1$
#1702
0$
#1703
-b10 R
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1$
#1704
0$
#1705
-b10010111 f
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1$
#1706
0$
#1707
-b100 R
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-xN
+b100 T
+b10011000 h
1$
#1708
0$
#1709
-b10011001 f
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b1010101100 -
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-0%
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+b1010101100 W
b1010101100 E
1$
#1710
0$
#1711
-b1 R
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1$
#1712
0$
#1713
-b10011011 f
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1$
#1714
0$
#1715
-b11 R
-b10011100 f
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1$
#1716
0$
#1717
-b10011101 f
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-x%
-xN
+b10011101 h
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1$
#1718
0$
#1719
-b0 R
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-b1010110000 U
-0%
-0N
+b1010110000 W
b1010110000 E
1$
#1720
0$
#1721
-b10011111 f
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1$
#1722
0$
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1$
#1724
0$
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-b10100001 f
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1$
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0$
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1$
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0$
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1$
#1730
0$
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1$
#1732
0$
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1$
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0$
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-b11 R
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1$
#1736
0$
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1$
#1738
0$
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1$
#1740
0$
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-b10101001 f
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1$
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0$
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1$
#1744
0$
#1745
-b10101011 f
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1$
#1746
0$
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1$
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0$
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1$
#1750
0$
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-b1 R
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1$
#1752
0$
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1$
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0$
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-b11 R
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1$
#1756
0$
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-b10110001 f
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1$
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0$
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1$
#1760
0$
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1$
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0$
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1$
#1764
0$
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-b10110101 f
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1$
#1766
0$
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1$
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0$
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1$
#1770
0$
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1$
#1772
0$
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-b10111001 f
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1$
#1774
0$
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-b11 R
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1$
#1776
0$
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-b10111011 f
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1$
#1778
0$
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-b0 R
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1$
#1780
0$
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-b10111101 f
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1$
#1782
0$
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-b10 R
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1$
#1784
0$
#1785
-b10111111 f
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1$
#1786
0$
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1$
#1788
0$
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-b11000001 f
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1$
#1790
0$
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-b1 R
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1$
#1792
0$
#1793
-b11000011 f
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1$
#1794
0$
#1795
-b11 R
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1$
#1796
0$
#1797
-b11000101 f
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1$
#1798
0$
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-b0 R
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1$
#1800
0$
#1801
-b11000111 f
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1$
#1802
0$
#1803
-b10 R
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1$
#1804
0$
#1805
-b11001001 f
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1$
#1806
0$
#1807
-b100 R
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1$
#1808
0$
#1809
-b11001011 f
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-0%
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1$
#1810
0$
#1811
-b1 R
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1$
#1812
0$
#1813
-b11001101 f
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1$
#1814
0$
#1815
-b11 R
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1$
#1816
0$
#1817
-b11001111 f
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1$
#1818
0$
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-b0 R
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-0%
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1$
#1820
0$
#1821
-b11010001 f
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1$
#1822
0$
#1823
-b10 R
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1$
#1824
0$
#1825
-b11010011 f
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1$
#1826
0$
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-b100 R
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1$
#1828
0$
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-b11010101 f
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-0%
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1$
#1830
0$
#1831
-b1 R
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1$
#1832
0$
#1833
-b11010111 f
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1$
#1834
0$
#1835
-b11 R
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1$
#1836
0$
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-b11011001 f
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+b11011001 h
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1$
#1838
0$
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-b0 R
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-0%
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1$
#1840
0$
#1841
-b11011011 f
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1$
#1842
0$
#1843
-b10 R
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1$
#1844
0$
#1845
-b11011101 f
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1$
#1846
0$
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-b100 R
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1$
#1848
0$
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-b11011111 f
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b1011100100 -
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-0%
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1$
#1850
0$
#1851
-b1 R
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-b11100000 f
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1$
#1852
0$
#1853
-b11100001 f
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1$
#1854
0$
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-b11 R
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1$
#1856
0$
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-b11100011 f
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+b11100011 h
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1$
#1858
0$
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-b0 R
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1$
#1860
0$
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-b11100101 f
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1$
#1862
0$
#1863
-b10 R
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1$
#1864
0$
#1865
-b11100111 f
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1$
#1866
0$
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-b100 R
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1$
#1868
0$
#1869
-b11101001 f
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-0%
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1$
#1870
0$
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-b1 R
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1$
#1872
0$
#1873
-0]
-b1 f
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-b10 R
+0_
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1$
#1874
0$
#1875
-b11 R
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+1!
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1$
#1876
0$
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-b11 f
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1$
#1878
0$
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-b0 R
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-0%
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1$
#1880
0$
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-b101 f
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1$
#1882
0$
#1883
-b10 R
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1$
#1884
0$
#1885
-b111 f
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1$
#1886
0$
#1887
-b100 R
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-xN
+b100 T
+b1000 h
1$
#1888
0$
#1889
-b1001 f
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b1011110100 -
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-0%
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1$
#1890
0$
#1891
-b1 R
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-b1010 f
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1$
#1892
0$
#1893
-b1011 f
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+b10 T
1$
#1894
0$
#1895
-b11 R
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+b1100 h
1$
#1896
0$
#1897
-b1101 f
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-xN
+b1101 h
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1$
#1898
0$
#1899
-b0 R
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b1011111000 -
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-b1011111000 U
-0%
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+b1011111000 W
b1011111000 E
1$
#1900
0$
#1901
-b1111 f
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+b1111 h
+b1 T
b1011111100 F
1$
#1902
0$
#1903
-b10 R
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+b10000 h
1$
#1904
0$
#1905
-b10001 f
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1$
#1906
0$
#1907
-b100 R
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-xN
+b100 T
+b10010 h
1$
#1908
0$
#1909
-b10011 f
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b1011111100 -
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-b1011111100 U
-0%
-0N
+b1011111100 W
b1011111100 E
1$
#1910
0$
#1911
-b1 R
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-b10100 f
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1$
#1912
0$
#1913
-b10101 f
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+b10101 h
+b10 T
1$
#1914
0$
#1915
-b11 R
-b10110 f
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+b10110 h
1$
#1916
0$
#1917
-b10111 f
-b100 R
-x%
-xN
+b10111 h
+b100 T
1$
#1918
0$
#1919
-b0 R
-b11000 f
+b0 T
+b11000 h
b1100000000 -
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b1100000000 H
-b1100000000 U
-0%
-0N
+b1100000000 W
b1100000000 E
1$
#1920
0$
#1921
-b11001 f
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+b11001 h
+b1 T
b1100000100 F
1$
#1922
0$
#1923
-b10 R
-b11010 f
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+b11010 h
1$
#1924
0$
#1925
-b11011 f
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+b11011 h
+b11 T
1$
#1926
0$
#1927
-b100 R
-b11100 f
-x%
-xN
+b100 T
+b11100 h
1$
#1928
0$
#1929
-b11101 f
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b1100000100 -
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b1100000100 H
-b1100000100 U
-0%
-0N
+b1100000100 W
b1100000100 E
1$
#1930
0$
#1931
-b1 R
+b1 T
b1100001000 F
-b11110 f
+b11110 h
1$
#1932
0$
#1933
-b11111 f
-b10 R
+b11111 h
+b10 T
1$
#1934
0$
#1935
-b11 R
-b100000 f
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+b100000 h
1$
#1936
0$
#1937
-b100001 f
-b100 R
-x%
-xN
+b100001 h
+b100 T
1$
#1938
0$
#1939
-b0 R
-b100010 f
+b0 T
+b100010 h
b1100001000 -
b1100001000 6
b1100001000 H
-b1100001000 U
-0%
-0N
+b1100001000 W
b1100001000 E
1$
#1940
0$
#1941
-b100011 f
-b1 R
+b100011 h
+b1 T
b1100001100 F
1$
#1942
0$
#1943
-b10 R
-b100100 f
+b10 T
+b100100 h
1$
#1944
0$
#1945
-b100101 f
-b11 R
+b100101 h
+b11 T
1$
#1946
0$
#1947
-b100 R
-b100110 f
-x%
-xN
+b100 T
+b100110 h
1$
#1948
0$
#1949
-b100111 f
-b0 R
+b100111 h
+b0 T
b1100001100 -
b1100001100 6
b1100001100 H
-b1100001100 U
-0%
-0N
+b1100001100 W
b1100001100 E
1$
#1950
0$
#1951
-b1 R
+b1 T
b1100010000 F
-b101000 f
+b101000 h
1$
#1952
0$
#1953
-b101001 f
-b10 R
+b101001 h
+b10 T
1$
#1954
0$
#1955
-b11 R
-b101010 f
+b11 T
+b101010 h
1$
#1956
0$
#1957
-b101011 f
-b100 R
-x%
-xN
+b101011 h
+b100 T
1$
#1958
0$
#1959
-b0 R
-b101100 f
+b0 T
+b101100 h
b1100010000 -
b1100010000 6
b1100010000 H
-b1100010000 U
-0%
-0N
+b1100010000 W
b1100010000 E
1$
#1960
0$
#1961
-b101101 f
-b1 R
+b101101 h
+b1 T
b1100010100 F
1$
#1962
0$
#1963
-b10 R
-b101110 f
+b10 T
+b101110 h
1$
#1964
0$
#1965
-b101111 f
-b11 R
+b101111 h
+b11 T
1$
#1966
0$
#1967
-b100 R
-b110000 f
-x%
-xN
+b100 T
+b110000 h
1$
#1968
0$
#1969
-b110001 f
-b0 R
+b110001 h
+b0 T
b1100010100 -
b1100010100 6
b1100010100 H
-b1100010100 U
-0%
-0N
+b1100010100 W
b1100010100 E
1$
#1970
0$
#1971
-b1 R
+b1 T
b1100011000 F
-b110010 f
+b110010 h
1$
#1972
0$
#1973
-b110011 f
-b10 R
+b110011 h
+b10 T
1$
#1974
0$
#1975
-b11 R
-b110100 f
+b11 T
+b110100 h
1$
#1976
0$
#1977
-b110101 f
-b100 R
-x%
-xN
+b110101 h
+b100 T
1$
#1978
0$
#1979
-b0 R
-b110110 f
+b0 T
+b110110 h
b1100011000 -
b1100011000 6
b1100011000 H
-b1100011000 U
-0%
-0N
+b1100011000 W
b1100011000 E
1$
#1980
0$
#1981
-b110111 f
-b1 R
+b110111 h
+b1 T
b1100011100 F
1$
#1982
0$
#1983
-b10 R
-b111000 f
+b10 T
+b111000 h
1$
#1984
0$
#1985
-b111001 f
-b11 R
+b111001 h
+b11 T
1$
#1986
0$
#1987
-b100 R
-b111010 f
-x%
-xN
+b100 T
+b111010 h
1$
#1988
0$
#1989
-b111011 f
-b0 R
+b111011 h
+b0 T
b1100011100 -
b1100011100 6
b1100011100 H
-b1100011100 U
-0%
-0N
+b1100011100 W
b1100011100 E
1$
#1990
0$
#1991
-b1 R
+b1 T
b1100100000 F
-b111100 f
+b111100 h
1$
#1992
0$
#1993
-b111101 f
-b10 R
+b111101 h
+b10 T
1$
#1994
0$
#1995
-b11 R
-b111110 f
+b11 T
+b111110 h
1$
#1996
0$
#1997
-b111111 f
-b100 R
-x%
-xN
+b111111 h
+b100 T
1$
#1998
0$
#1999
-b0 R
-b1000000 f
+b0 T
+b1000000 h
b1100100000 -
b1100100000 6
b1100100000 H
-b1100100000 U
-0%
-0N
+b1100100000 W
b1100100000 E
1$
#2000
0$
#2001
-b1000001 f
-b1 R
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b1100100100 F
1$
#2002
0$
#2003
-b10 R
-b1000010 f
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1$
#2004
0$
#2005
-b1000011 f
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1$
#2006
0$
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-b100 R
-b1000100 f
-x%
-xN
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1$
#2008
0$
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-b1000101 f
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b1100100100 -
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-b1100100100 U
-0%
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1$
#2010
0$
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-b1 R
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-b1000110 f
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1$
#2012
0$
#2013
-b1000111 f
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1$
#2014
0$
#2015
-b11 R
-b1001000 f
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1$
#2016
0$
#2017
-b1001001 f
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-x%
-xN
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1$
#2018
0$
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-b0 R
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-0%
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1$
#2020
0$
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-b1001011 f
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1$
#2022
0$
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-b10 R
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1$
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0$
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-b1001101 f
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1$
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0$
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-b100 R
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1$
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0$
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1$
#2030
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0$
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1$
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0$
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0$
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-b1010011 f
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0$
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0$
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1$
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0$
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1$
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-b1011101 f
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0$
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1$
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0$
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0$
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0$
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1$
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0$
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0$
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1$
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0$
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0$
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-b1100101 f
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1$
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0$
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-b11 R
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0$
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-b1100111 f
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1$
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0$
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1$
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0$
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#2084
0$
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#2086
0$
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1$
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#2092
0$
#2093
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1$
#2094
0$
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-b11 R
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#2096
0$
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-b1110001 f
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1$
#2098
0$
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1$
#2100
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-b1110011 f
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1$
#2102
0$
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#2104
0$
#2105
-b1110101 f
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1$
#2106
0$
#2107
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1$
#2108
0$
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-b1110111 f
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1$
#2110
0$
#2111
-b1 R
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-b1111000 f
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1$
#2112
0$
#2113
-b1111001 f
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1$
#2114
0$
#2115
-b11 R
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#2116
0$
#2117
-b1111011 f
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-xN
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1$
#2118
0$
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1$
#2120
0$
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-b1111101 f
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#2122
0$
#2123
-b10 R
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1$
#2124
0$
#2125
-b1111111 f
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1$
#2126
0$
#2127
-b100 R
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-xN
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1$
#2128
0$
#2129
-b10000001 f
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1$
#2130
0$
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-b1 R
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1$
#2132
0$
#2133
-b10000011 f
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1$
#2134
0$
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-b11 R
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#2136
0$
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-xN
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1$
#2138
0$
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1$
#2140
0$
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-b10000111 f
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#2142
0$
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-b10 R
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#2144
0$
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-b10001001 f
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0$
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-b100 R
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#2148
0$
#2149
-b10001011 f
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1$
#2150
0$
#2151
-b1 R
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1$
#2152
0$
#2153
-b10001101 f
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1$
#2154
0$
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-b11 R
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#2156
0$
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1$
#2158
0$
#2159
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1$
#2160
0$
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-b10010001 f
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0$
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-b10 R
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1$
#2164
0$
#2165
-b10010011 f
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1$
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0$
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-b100 R
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1$
#2168
0$
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-b10010101 f
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1$
#2170
0$
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-b1 R
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1$
#2172
0$
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-b10010111 f
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1$
#2174
0$
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-b11 R
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#2176
0$
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-b10011001 f
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1$
#2178
0$
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-b0 R
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1$
#2180
0$
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-b10011011 f
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#2182
0$
#2183
-b10 R
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#2184
0$
#2185
-b10011101 f
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1$
#2186
0$
#2187
-b100 R
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1$
#2188
0$
#2189
-b10011111 f
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1$
#2190
0$
#2191
-b1 R
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-b10100000 f
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1$
#2192
0$
#2193
-b10100001 f
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1$
#2194
0$
#2195
-b11 R
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#2196
0$
#2197
-b10100011 f
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#2198
0$
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1$
#2200
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-b10100101 f
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1$
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0$
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-b10 R
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0$
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-b10100111 f
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1$
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0$
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-b100 R
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#2208
0$
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-b10101001 f
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1$
#2210
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1$
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0$
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1$
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0$
#2215
-b11 R
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#2216
0$
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-xN
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1$
#2218
0$
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1$
#2220
0$
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-b10101111 f
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#2222
0$
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-b10 R
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1$
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0$
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-b10110001 f
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1$
#2226
0$
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-b100 R
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1$
#2228
0$
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-b10110011 f
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1$
#2230
0$
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-b1 R
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1$
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0$
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1$
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-b11 R
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0$
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1$
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0$
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1$
#2240
0$
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-b10111001 f
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0$
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1$
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0$
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0$
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1$
#2250
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1$
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0$
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1$
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0$
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0$
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0$
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1$
#2260
0$
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-b11000011 f
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0$
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0$
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-b11000101 f
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1$
#2266
0$
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1$
#2268
0$
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-b11000111 f
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1$
#2270
0$
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-b1 R
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1$
#2272
0$
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-b11001001 f
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1$
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0$
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-b11 R
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1$
#2276
0$
#2277
-b11001011 f
-b100 R
-x%
-xN
+b11001011 h
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1$
#2278
0$
#2279
-b0 R
-b11001100 f
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b1110010000 -
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-b1110010000 U
-0%
-0N
+b1110010000 W
b1110010000 E
1$
#2280
0$
#2281
-b11001101 f
-b1 R
+b11001101 h
+b1 T
b1110010100 F
1$
#2282
0$
#2283
-b10 R
-b11001110 f
+b10 T
+b11001110 h
1$
#2284
0$
#2285
-b11001111 f
-b11 R
+b11001111 h
+b11 T
1$
#2286
0$
#2287
-b100 R
-b11010000 f
-x%
-xN
+b100 T
+b11010000 h
1$
#2288
0$
#2289
-b11010001 f
-b0 R
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b1110010100 -
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b1110010100 H
-b1110010100 U
-0%
-0N
+b1110010100 W
b1110010100 E
1$
#2290
0$
#2291
-b1 R
+b1 T
b1110011000 F
-b11010010 f
+b11010010 h
1$
#2292
0$
#2293
-b11010011 f
-b10 R
+b11010011 h
+b10 T
1$
#2294
0$
#2295
-b11 R
-b11010100 f
+b11 T
+b11010100 h
1$
#2296
0$
#2297
-b11010101 f
-b100 R
-x%
-xN
+b11010101 h
+b100 T
1$
#2298
0$
#2299
-b0 R
-b11010110 f
+b0 T
+b11010110 h
b1110011000 -
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-b1110011000 U
-0%
-0N
+b1110011000 W
b1110011000 E
1$
#2300
0$
#2301
-b11010111 f
-b1 R
+b11010111 h
+b1 T
b1110011100 F
1$
#2302
0$
#2303
-b10 R
-b11011000 f
+b10 T
+b11011000 h
1$
#2304
0$
#2305
-b11011001 f
-b11 R
+b11011001 h
+b11 T
1$
#2306
0$
#2307
-b100 R
-b11011010 f
-x%
-xN
+b100 T
+b11011010 h
1$
#2308
0$
#2309
-b11011011 f
-b0 R
+b11011011 h
+b0 T
b1110011100 -
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b1110011100 H
-b1110011100 U
-0%
-0N
+b1110011100 W
b1110011100 E
1$
#2310
0$
#2311
-b1 R
+b1 T
b1110100000 F
-b11011100 f
+b11011100 h
1$
#2312
0$
#2313
-b11011101 f
-b10 R
+b11011101 h
+b10 T
1$
#2314
0$
#2315
-b11 R
-b11011110 f
+b11 T
+b11011110 h
1$
#2316
0$
#2317
-b11011111 f
-b100 R
-x%
-xN
+b11011111 h
+b100 T
1$
#2318
0$
#2319
-b0 R
-b11100000 f
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+b11100000 h
b1110100000 -
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b1110100000 H
-b1110100000 U
-0%
-0N
+b1110100000 W
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1$
#2320
0$
#2321
-b11100001 f
-b1 R
+b11100001 h
+b1 T
b1110100100 F
1$
#2322
0$
#2323
-b10 R
-b11100010 f
+b10 T
+b11100010 h
1$
#2324
0$
#2325
-b11100011 f
-b11 R
+b11100011 h
+b11 T
1$
#2326
0$
#2327
-b100 R
-b11100100 f
-x%
-xN
+b100 T
+b11100100 h
1$
#2328
0$
#2329
-b11100101 f
-b0 R
+b11100101 h
+b0 T
b1110100100 -
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-b1110100100 U
-0%
-0N
+b1110100100 W
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1$
#2330
0$
#2331
-b1 R
+b1 T
b1110101000 F
-b11100110 f
+b11100110 h
1$
#2332
0$
#2333
-b11100111 f
-b10 R
+b11100111 h
+b10 T
1$
#2334
0$
#2335
-b11 R
-b11101000 f
+b11 T
+b11101000 h
1$
#2336
0$
#2337
-b11101001 f
-b100 R
-x%
-xN
+b11101001 h
+b100 T
1$
#2338
0$
#2339
-b0 R
-1]
-b0 f
+b0 T
+1_
+b0 h
b1110101000 -
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b1110101000 H
-b1110101000 U
-0%
-0N
+b1110101000 W
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1$
#2340
0$
#2341
-0]
-b1 f
-b11 k
-b1 R
+0_
+b1 h
+b11 m
+b1 T
b1110101100 F
1$
#2342
0$
#2343
-b10 R
-b10 f
+b10 T
+b10 h
1$
#2344
0$
#2345
-b11 f
-b11 R
+b11 h
+b11 T
1$
#2346
0$
#2347
-b100 R
-b100 f
-x%
-xN
+b100 T
+b100 h
1$
#2348
0$
#2349
-b101 f
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+b101 h
+b0 T
b1110101100 -
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-b1110101100 U
-0%
-0N
+b1110101100 W
b1110101100 E
1$
#2350
0$
#2351
-b1 R
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b1110110000 F
-b110 f
+b110 h
1$
#2352
0$
#2353
-b111 f
-b10 R
+b111 h
+b10 T
1$
#2354
0$
#2355
-b11 R
-b1000 f
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+b1000 h
1$
#2356
0$
#2357
-b1001 f
-b100 R
-x%
-xN
+b1001 h
+b100 T
1$
#2358
0$
#2359
-b0 R
-b1010 f
+b0 T
+b1010 h
b1110110000 -
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-b1110110000 U
-0%
-0N
+b1110110000 W
b1110110000 E
1$
#2360
0$
#2361
-b1011 f
-b1 R
+b1011 h
+b1 T
b1110110100 F
1$
#2362
0$
#2363
-b10 R
-b1100 f
+b10 T
+b1100 h
1$
#2364
0$
#2365
-b1101 f
-b11 R
+b1101 h
+b11 T
1$
#2366
0$
#2367
-b100 R
-b1110 f
-x%
-xN
+b100 T
+b1110 h
1$
#2368
0$
#2369
-b1111 f
-b0 R
+b1111 h
+b0 T
b1110110100 -
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b1110110100 H
-b1110110100 U
-0%
-0N
+b1110110100 W
b1110110100 E
1$
#2370
0$
#2371
-b1 R
+b1 T
b1110111000 F
-b10000 f
+b10000 h
1$
#2372
0$
#2373
-b10001 f
-b10 R
+b10001 h
+b10 T
1$
#2374
0$
#2375
-b11 R
-b10010 f
+b11 T
+b10010 h
1$
#2376
0$
#2377
-b10011 f
-b100 R
-x%
-xN
+b10011 h
+b100 T
1$
#2378
0$
#2379
-b0 R
-b10100 f
+b0 T
+b10100 h
b1110111000 -
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b1110111000 H
-b1110111000 U
-0%
-0N
+b1110111000 W
b1110111000 E
1$
#2380
0$
#2381
-b10101 f
-b1 R
+b10101 h
+b1 T
b1110111100 F
1$
#2382
0$
#2383
-b10 R
-b10110 f
+b10 T
+b10110 h
1$
#2384
0$
#2385
-b10111 f
-b11 R
+b10111 h
+b11 T
1$
#2386
0$
#2387
-b100 R
-b11000 f
-x%
-xN
+b100 T
+b11000 h
1$
#2388
0$
#2389
-b11001 f
-b0 R
+b11001 h
+b0 T
b1110111100 -
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b1110111100 H
-b1110111100 U
-0%
-0N
+b1110111100 W
b1110111100 E
1$
#2390
0$
#2391
-b1 R
+b1 T
b1111000000 F
-b11010 f
+b11010 h
1$
#2392
0$
#2393
-b11011 f
-b10 R
+b11011 h
+b10 T
1$
#2394
0$
#2395
-b11 R
-b11100 f
+b11 T
+b11100 h
1$
#2396
0$
#2397
-b11101 f
-b100 R
-x%
-xN
+b11101 h
+b100 T
1$
#2398
0$
#2399
-b0 R
-b11110 f
+b0 T
+b11110 h
b1111000000 -
b1111000000 6
b1111000000 H
-b1111000000 U
-0%
-0N
+b1111000000 W
b1111000000 E
1$
#2400
0$
#2401
-b11111 f
-b1 R
+b11111 h
+b1 T
b1111000100 F
1$
#2402
0$
#2403
-b10 R
-b100000 f
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+b100000 h
1$
#2404
0$
#2405
-b100001 f
-b11 R
+b100001 h
+b11 T
1$
#2406
0$
#2407
-b100 R
-b100010 f
-x%
-xN
+b100 T
+b100010 h
1$
#2408
0$
#2409
-b100011 f
-b0 R
+b100011 h
+b0 T
b1111000100 -
b1111000100 6
b1111000100 H
-b1111000100 U
-0%
-0N
+b1111000100 W
b1111000100 E
1$
#2410
0$
#2411
-b1 R
+b1 T
b1111001000 F
-b100100 f
+b100100 h
1$
#2412
0$
#2413
-b100101 f
-b10 R
+b100101 h
+b10 T
1$
#2414
0$
#2415
-b11 R
-b100110 f
+b11 T
+b100110 h
1$
#2416
0$
#2417
-b100111 f
-b100 R
-x%
-xN
+b100111 h
+b100 T
1$
#2418
0$
#2419
-b0 R
-b101000 f
+b0 T
+b101000 h
b1111001000 -
b1111001000 6
b1111001000 H
-b1111001000 U
-0%
-0N
+b1111001000 W
b1111001000 E
1$
#2420
0$
#2421
-b101001 f
-b1 R
+b101001 h
+b1 T
b1111001100 F
1$
#2422
0$
#2423
-b10 R
-b101010 f
+b10 T
+b101010 h
1$
#2424
0$
#2425
-b101011 f
-b11 R
+b101011 h
+b11 T
1$
#2426
0$
#2427
-b100 R
-b101100 f
-x%
-xN
+b100 T
+b101100 h
1$
#2428
0$
#2429
-b101101 f
-b0 R
+b101101 h
+b0 T
b1111001100 -
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b1111001100 H
-b1111001100 U
-0%
-0N
+b1111001100 W
b1111001100 E
1$
#2430
0$
#2431
-b1 R
+b1 T
b1111010000 F
-b101110 f
+b101110 h
1$
#2432
0$
#2433
-b101111 f
-b10 R
+b101111 h
+b10 T
1$
#2434
0$
#2435
-b11 R
-b110000 f
+b11 T
+b110000 h
1$
#2436
0$
#2437
-b110001 f
-b100 R
-x%
-xN
+b110001 h
+b100 T
1$
#2438
0$
#2439
-b0 R
-b110010 f
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+b110010 h
b1111010000 -
b1111010000 6
b1111010000 H
-b1111010000 U
-0%
-0N
+b1111010000 W
b1111010000 E
1$
#2440
0$
#2441
-b110011 f
-b1 R
+b110011 h
+b1 T
b1111010100 F
1$
#2442
0$
#2443
-b10 R
-b110100 f
+b10 T
+b110100 h
1$
#2444
0$
#2445
-b110101 f
-b11 R
+b110101 h
+b11 T
1$
#2446
0$
#2447
-b100 R
-b110110 f
-x%
-xN
+b100 T
+b110110 h
1$
#2448
0$
#2449
-b110111 f
-b0 R
+b110111 h
+b0 T
b1111010100 -
b1111010100 6
b1111010100 H
-b1111010100 U
-0%
-0N
+b1111010100 W
b1111010100 E
1$
#2450
0$
#2451
-b1 R
+b1 T
b1111011000 F
-b111000 f
+b111000 h
1$
#2452
0$
#2453
-b111001 f
-b10 R
+b111001 h
+b10 T
1$
#2454
0$
#2455
-b11 R
-b111010 f
+b11 T
+b111010 h
1$
#2456
0$
#2457
-b111011 f
-b100 R
-x%
-xN
+b111011 h
+b100 T
1$
#2458
0$
#2459
-b0 R
-b111100 f
+b0 T
+b111100 h
b1111011000 -
b1111011000 6
b1111011000 H
-b1111011000 U
-0%
-0N
+b1111011000 W
b1111011000 E
1$
#2460
0$
#2461
-b111101 f
-b1 R
+b111101 h
+b1 T
b1111011100 F
1$
#2462
0$
#2463
-b10 R
-b111110 f
+b10 T
+b111110 h
1$
#2464
0$
#2465
-b111111 f
-b11 R
+b111111 h
+b11 T
1$
#2466
0$
#2467
-b100 R
-b1000000 f
-x%
-xN
+b100 T
+b1000000 h
1$
#2468
0$
#2469
-b1000001 f
-b0 R
+b1000001 h
+b0 T
b1111011100 -
b1111011100 6
b1111011100 H
-b1111011100 U
-0%
-0N
+b1111011100 W
b1111011100 E
1$
#2470
0$
#2471
-b1 R
+b1 T
b1111100000 F
-b1000010 f
+b1000010 h
1$
#2472
0$
#2473
-b1000011 f
-b10 R
+b1000011 h
+b10 T
1$
#2474
0$
#2475
-b11 R
-b1000100 f
+b11 T
+b1000100 h
1$
#2476
0$
#2477
-b1000101 f
-b100 R
-x%
-xN
+b1000101 h
+b100 T
1$
#2478
0$
#2479
-b0 R
-b1000110 f
+b0 T
+b1000110 h
b1111100000 -
b1111100000 6
b1111100000 H
-b1111100000 U
-0%
-0N
+b1111100000 W
b1111100000 E
1$
#2480
0$
#2481
-b1000111 f
-b1 R
+b1000111 h
+b1 T
b1111100100 F
1$
#2482
0$
#2483
-b10 R
-b1001000 f
+b10 T
+b1001000 h
1$
#2484
0$
#2485
-b1001001 f
-b11 R
+b1001001 h
+b11 T
1$
#2486
0$
#2487
-b100 R
-b1001010 f
-x%
-xN
+b100 T
+b1001010 h
1$
#2488
0$
#2489
-b1001011 f
-b0 R
+b1001011 h
+b0 T
b1111100100 -
b1111100100 6
b1111100100 H
-b1111100100 U
-0%
-0N
+b1111100100 W
b1111100100 E
1$
#2490
0$
#2491
-b1 R
+b1 T
b1111101000 F
-b1001100 f
+b1001100 h
1$
#2492
0$
#2493
-b1001101 f
-b10 R
+b1001101 h
+b10 T
1$
#2494
0$
#2495
-b11 R
-b1001110 f
+b11 T
+b1001110 h
1$
#2496
0$
#2497
-b1001111 f
-b100 R
-x%
-xN
+b1001111 h
+b100 T
1$
#2498
0$
#2499
-b0 R
-b1010000 f
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+b1010000 h
b1111101000 -
b1111101000 6
b1111101000 H
-b1111101000 U
-0%
-0N
+b1111101000 W
b1111101000 E
1$
#2500
0$
#2501
-b1010001 f
-b1 R
+b1010001 h
+b1 T
b1111101100 F
1$
#2502
0$
#2503
-b10 R
-b1010010 f
+b10 T
+b1010010 h
1$
#2504
0$
#2505
-b1010011 f
-b11 R
+b1010011 h
+b11 T
1$
#2506
0$
#2507
-b100 R
-b1010100 f
-x%
-xN
+b100 T
+b1010100 h
1$
#2508
0$
#2509
-b1010101 f
-b0 R
+b1010101 h
+b0 T
b1111101100 -
b1111101100 6
b1111101100 H
-b1111101100 U
-0%
-0N
+b1111101100 W
b1111101100 E
1$
#2510
0$
#2511
-b1 R
+b1 T
b1111110000 F
-b1010110 f
+b1010110 h
1$
#2512
0$
#2513
-b1010111 f
-b10 R
+b1010111 h
+b10 T
1$
#2514
0$
#2515
-b11 R
-b1011000 f
+b11 T
+b1011000 h
1$
#2516
0$
#2517
-b1011001 f
-b100 R
-x%
-xN
+b1011001 h
+b100 T
1$
#2518
0$
#2519
-b0 R
-b1011010 f
+b0 T
+b1011010 h
b1111110000 -
b1111110000 6
b1111110000 H
-b1111110000 U
-0%
-0N
+b1111110000 W
b1111110000 E
1$
#2520
0$
#2521
-b1011011 f
-b1 R
+b1011011 h
+b1 T
b1111110100 F
1$
#2522
0$
#2523
-b10 R
-b1011100 f
+b10 T
+b1011100 h
1$
#2524
0$
#2525
-b1011101 f
-b11 R
+b1011101 h
+b11 T
1$
#2526
0$
#2527
-b100 R
-b1011110 f
-x%
-xN
+b100 T
+b1011110 h
1$
#2528
0$
#2529
-b1011111 f
-b0 R
+b1011111 h
+b0 T
b1111110100 -
b1111110100 6
b1111110100 H
-b1111110100 U
-0%
-0N
+b1111110100 W
b1111110100 E
1$
#2530
0$
#2531
-b1 R
+b1 T
b1111111000 F
-b1100000 f
+b1100000 h
1$
#2532
0$
#2533
-b1100001 f
-b10 R
+b1100001 h
+b10 T
1$
#2534
0$
#2535
-b11 R
-b1100010 f
+b11 T
+b1100010 h
1$
#2536
0$
#2537
-b1100011 f
-b100 R
-x%
-xN
+b1100011 h
+b100 T
1$
#2538
0$
#2539
-b0 R
-b1100100 f
+b0 T
+b1100100 h
b1111111000 -
b1111111000 6
b1111111000 H
-b1111111000 U
-0%
-0N
+b1111111000 W
b1111111000 E
1$
#2540
0$
#2541
-b1100101 f
-b1 R
+b1100101 h
+b1 T
b1111111100 F
1$
#2542
0$
#2543
-b10 R
-b1100110 f
+b10 T
+b1100110 h
1$
#2544
0$
#2545
-b1100111 f
-b11 R
+b1100111 h
+b11 T
1$
#2546
0$
#2547
-b100 R
-b1101000 f
-x%
-xN
+b100 T
+b1101000 h
1$
#2548
0$
#2549
-b1101001 f
-b0 R
+b1101001 h
+b0 T
b1111111100 -
b1111111100 6
b1111111100 H
-b1111111100 U
-0%
-0N
+b1111111100 W
b1111111100 E
1$
#2550
0$
#2551
-b1 R
+b1 T
b10000000000 F
-b1101010 f
+b1101010 h
1$
#2552
0$
#2553
-b1101011 f
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1$
#2554
0$
#2555
-b11 R
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1$
#2556
0$
#2557
-b1101101 f
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1$
#2558
0$
#2559
-b0 R
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b10000000000 -
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-b10000000000 U
-0%
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+b10000000000 W
b10000000000 E
1$
#2560
0$
#2561
-b1101111 f
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1$
#2562
0$
#2563
-b10 R
-b1110000 f
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1$
#2564
0$
#2565
-b1110001 f
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1$
#2566
0$
#2567
-b100 R
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+b100 T
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1$
#2568
0$
#2569
-b1110011 f
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b10000000100 -
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-b10000000100 U
-0%
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1$
#2570
0$
#2571
-b1 R
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-b1110100 f
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1$
#2572
0$
#2573
-b1110101 f
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1$
#2574
0$
#2575
-b11 R
-b1110110 f
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1$
#2576
0$
#2577
-b1110111 f
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-x%
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+b1110111 h
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1$
#2578
0$
#2579
-b0 R
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-0%
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1$
#2580
0$
#2581
-b1111001 f
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1$
#2582
0$
#2583
-b10 R
-b1111010 f
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1$
#2584
0$
#2585
-b1111011 f
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1$
#2586
0$
#2587
-b100 R
-b1111100 f
-x%
-xN
+b100 T
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1$
#2588
0$
#2589
-b1111101 f
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b10000001100 -
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-0%
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1$
#2590
0$
#2591
-b1 R
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-b1111110 f
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1$
#2592
0$
#2593
-b1111111 f
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1$
#2594
0$
#2595
-b11 R
-b10000000 f
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+b10000000 h
1$
#2596
0$
#2597
-b10000001 f
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+b10000001 h
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1$
#2598
0$
#2599
-b0 R
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-0%
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1$
#2600
0$
#2601
-b10000011 f
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1$
#2602
0$
#2603
-b10 R
-b10000100 f
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+b10000100 h
1$
#2604
0$
#2605
-b10000101 f
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1$
#2606
0$
#2607
-b100 R
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+b100 T
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1$
#2608
0$
#2609
-b10000111 f
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b10000010100 -
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-0%
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1$
#2610
0$
#2611
-b1 R
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-b10001000 f
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1$
#2612
0$
#2613
-b10001001 f
-b10 R
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1$
#2614
0$
#2615
-b11 R
-b10001010 f
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1$
#2616
0$
#2617
-b10001011 f
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+b10001011 h
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1$
#2618
0$
#2619
-b0 R
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-b10000011000 U
-0%
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1$
#2620
0$
#2621
-b10001101 f
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1$
#2622
0$
#2623
-b10 R
-b10001110 f
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1$
#2624
0$
#2625
-b10001111 f
-b11 R
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1$
#2626
0$
#2627
-b100 R
-b10010000 f
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-xN
+b100 T
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1$
#2628
0$
#2629
-b10010001 f
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-0%
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1$
#2630
0$
#2631
-b1 R
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-b10010010 f
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1$
#2632
0$
#2633
-b10010011 f
-b10 R
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+b10 T
1$
#2634
0$
#2635
-b11 R
-b10010100 f
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1$
#2636
0$
#2637
-b10010101 f
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-x%
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+b10010101 h
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1$
#2638
0$
#2639
-b0 R
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-b10000100000 U
-0%
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1$
#2640
0$
#2641
-b10010111 f
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b10000100100 F
1$
#2642
0$
#2643
-b10 R
-b10011000 f
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+b10011000 h
1$
#2644
0$
#2645
-b10011001 f
-b11 R
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+b11 T
1$
#2646
0$
#2647
-b100 R
-b10011010 f
-x%
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+b100 T
+b10011010 h
1$
#2648
0$
#2649
-b10011011 f
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b10000100100 -
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-b10000100100 U
-0%
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1$
#2650
0$
#2651
-b1 R
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-b10011100 f
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1$
#2652
0$
#2653
-b10011101 f
-b10 R
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+b10 T
1$
#2654
0$
#2655
-b11 R
-b10011110 f
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+b10011110 h
1$
#2656
0$
#2657
-b10011111 f
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-x%
-xN
+b10011111 h
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1$
#2658
0$
#2659
-b0 R
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b10000101000 -
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-b10000101000 U
-0%
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1$
#2660
0$
#2661
-b10100001 f
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b10000101100 F
1$
#2662
0$
#2663
-b10 R
-b10100010 f
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+b10100010 h
1$
#2664
0$
#2665
-b10100011 f
-b11 R
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1$
#2666
0$
#2667
-b100 R
-b10100100 f
-x%
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+b100 T
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1$
#2668
0$
#2669
-b10100101 f
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b10000101100 -
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-b10000101100 U
-0%
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1$
#2670
0$
#2671
-b1 R
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-b10100110 f
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1$
#2672
0$
#2673
-b10100111 f
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1$
#2674
0$
#2675
-b11 R
-b10101000 f
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+b10101000 h
1$
#2676
0$
#2677
-b10101001 f
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-x%
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+b10101001 h
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1$
#2678
0$
#2679
-b0 R
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-b10000110000 U
-0%
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+b10000110000 W
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1$
#2680
0$
#2681
-b10101011 f
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1$
#2682
0$
#2683
-b10 R
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1$
#2684
0$
#2685
-b10101101 f
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1$
#2686
0$
#2687
-b100 R
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-x%
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+b100 T
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1$
#2688
0$
#2689
-b10101111 f
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-0%
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1$
#2690
0$
#2691
-b1 R
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-b10110000 f
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1$
#2692
0$
#2693
-b10110001 f
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1$
#2694
0$
#2695
-b11 R
-b10110010 f
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1$
#2696
0$
#2697
-b10110011 f
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-x%
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+b10110011 h
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1$
#2698
0$
#2699
-b0 R
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-0%
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1$
#2700
0$
#2701
-b10110101 f
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1$
#2702
0$
#2703
-b10 R
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1$
#2704
0$
#2705
-b10110111 f
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1$
#2706
0$
#2707
-b100 R
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-x%
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+b100 T
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1$
#2708
0$
#2709
-b10111001 f
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b10000111100 -
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-b10000111100 U
-0%
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+b10000111100 W
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1$
#2710
0$
#2711
-b1 R
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-b10111010 f
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1$
#2712
0$
#2713
-b10111011 f
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1$
#2714
0$
#2715
-b11 R
-b10111100 f
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1$
#2716
0$
#2717
-b10111101 f
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-x%
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+b10111101 h
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1$
#2718
0$
#2719
-b0 R
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-0%
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1$
#2720
0$
#2721
-b10111111 f
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1$
#2722
0$
#2723
-b10 R
-b11000000 f
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1$
#2724
0$
#2725
-b11000001 f
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1$
#2726
0$
#2727
-b100 R
-b11000010 f
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+b100 T
+b11000010 h
1$
#2728
0$
#2729
-b11000011 f
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b10001000100 -
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-b10001000100 U
-0%
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+b10001000100 W
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1$
#2730
0$
#2731
-b1 R
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-b11000100 f
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1$
#2732
0$
#2733
-b11000101 f
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+b10 T
1$
#2734
0$
#2735
-b11 R
-b11000110 f
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+b11000110 h
1$
#2736
0$
#2737
-b11000111 f
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-x%
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+b11000111 h
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1$
#2738
0$
#2739
-b0 R
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b10001001000 -
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-0%
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1$
#2740
0$
#2741
-b11001001 f
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1$
#2742
0$
#2743
-b10 R
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1$
#2744
0$
#2745
-b11001011 f
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1$
#2746
0$
#2747
-b100 R
-b11001100 f
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+b100 T
+b11001100 h
1$
#2748
0$
#2749
-b11001101 f
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b10001001100 -
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-b10001001100 U
-0%
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+b10001001100 W
b10001001100 E
1$
#2750
0$
#2751
-b1 R
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-b11001110 f
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1$
#2752
0$
#2753
-b11001111 f
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1$
#2754
0$
#2755
-b11 R
-b11010000 f
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+b11010000 h
1$
#2756
0$
#2757
-b11010001 f
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-xN
+b11010001 h
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1$
#2758
0$
#2759
-b0 R
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b10001010000 -
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-0%
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+b10001010000 W
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1$
#2760
0$
#2761
-b11010011 f
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1$
#2762
0$
#2763
-b10 R
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1$
#2764
0$
#2765
-b11010101 f
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1$
#2766
0$
#2767
-b100 R
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-x%
-xN
+b100 T
+b11010110 h
1$
#2768
0$
#2769
-b11010111 f
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b10001010100 -
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-0%
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+b10001010100 W
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1$
#2770
0$
#2771
-b1 R
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1$
#2772
0$
#2773
-b11011001 f
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1$
#2774
0$
#2775
-b11 R
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+b11011010 h
1$
#2776
0$
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-b11011011 f
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+b11011011 h
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1$
#2778
0$
#2779
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1$
#2780
0$
#2781
-b11011101 f
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1$
#2782
0$
#2783
-b10 R
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1$
#2784
0$
#2785
-b11011111 f
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1$
#2786
0$
#2787
-b100 R
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-xN
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1$
#2788
0$
#2789
-b11100001 f
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b10001011100 -
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-0%
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1$
#2790
0$
#2791
-b1 R
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1$
#2792
0$
#2793
-b11100011 f
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1$
#2794
0$
#2795
-b11 R
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1$
#2796
0$
#2797
-b11100101 f
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+b11100101 h
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1$
#2798
0$
#2799
-b0 R
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-b10001100000 U
-0%
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+b10001100000 W
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1$
#2800
0$
#2801
-b11100111 f
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1$
#2802
0$
#2803
-b10 R
-b11101000 f
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1$
#2804
0$
#2805
-b11101001 f
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1$
#2806
0$
#2807
-b100 R
-1]
-b0 f
-x%
-xN
+b100 T
+1_
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1$
#2808
0$
#2809
-0]
-b1 f
-b100 k
-b0 R
+0_
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b10001100100 -
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-b10001100100 U
-0%
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+b10001100100 W
b10001100100 E
1$
#2810
0$
#2811
-b1 R
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b10001101000 F
-b10 f
+b10 h
1$
#2812
0$
#2813
-b11 f
-b10 R
+b11 h
+b10 T
1$
#2814
0$
#2815
-b11 R
-b100 f
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+b100 h
1$
#2816
0$
#2817
-b101 f
-b100 R
-x%
-xN
+b101 h
+b100 T
1$
#2818
0$
#2819
-b0 R
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b10001101000 -
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b10001101000 H
-b10001101000 U
-0%
-0N
+b10001101000 W
b10001101000 E
1$
#2820
0$
#2821
-b111 f
-b1 R
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b10001101100 F
1$
#2822
0$
#2823
-b10 R
-b1000 f
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+b1000 h
1$
#2824
0$
#2825
-b1001 f
-b11 R
+b1001 h
+b11 T
1$
#2826
0$
#2827
-b100 R
-b1010 f
-x%
-xN
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1$
#2828
0$
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-b1011 f
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b10001101100 -
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1$
#2830
0$
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-b1 R
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1$
#2832
0$
#2833
-b1101 f
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1$
#2834
0$
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-b11 R
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1$
#2836
0$
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-b1111 f
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1$
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0$
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1$
#2840
0$
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-b10001 f
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1$
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0$
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-b10 R
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1$
#2844
0$
#2845
-b10011 f
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1$
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0$
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-b100 R
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1$
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0$
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1$
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0$
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-b1 R
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1$
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0$
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-b10111 f
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1$
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0$
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-b11 R
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#2856
0$
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-b11001 f
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1$
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0$
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1$
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0$
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-b11011 f
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0$
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-b10 R
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1$
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0$
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-b11101 f
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1$
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0$
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-b100 R
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1$
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0$
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b10001111100 -
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1$
#2870
0$
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-b1 R
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0$
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-b100001 f
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1$
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0$
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-b11 R
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0$
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-b100011 f
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0$
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1$
#2880
0$
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-b100101 f
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0$
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-b10 R
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0$
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-b100111 f
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1$
#2886
0$
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-b100 R
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0$
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-b101001 f
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1$
#2890
0$
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-b1 R
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1$
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0$
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-b101011 f
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1$
#2894
0$
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-b11 R
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1$
#2896
0$
#2897
-b101101 f
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1$
#2898
0$
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-b0 R
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-0%
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1$
#2900
0$
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-b101111 f
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#2902
0$
#2903
-b10 R
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1$
#2904
0$
#2905
-b110001 f
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1$
#2906
0$
#2907
-b100 R
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1$
#2908
0$
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-b110011 f
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b10010001100 -
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-0%
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1$
#2910
0$
#2911
-b1 R
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1$
#2912
0$
#2913
-b110101 f
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1$
#2914
0$
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-b11 R
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1$
#2916
0$
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-b110111 f
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1$
#2918
0$
#2919
-b0 R
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1$
#2920
0$
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-b111001 f
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1$
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0$
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-b10 R
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1$
#2924
0$
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-b111011 f
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1$
#2926
0$
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-b100 R
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1$
#2928
0$
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-b111101 f
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1$
#2930
0$
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-b1 R
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1$
#2932
0$
#2933
-b111111 f
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1$
#2934
0$
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-b11 R
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1$
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0$
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-b1000001 f
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1$
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0$
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-b0 R
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1$
#2940
0$
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-b1000011 f
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0$
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-b10 R
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1$
#2944
0$
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-b1000101 f
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1$
#2946
0$
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-b100 R
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1$
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0$
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-b1000111 f
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1$
#2950
0$
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-b1 R
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1$
#2952
0$
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-b1001001 f
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1$
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0$
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-b11 R
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0$
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-b1001011 f
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0$
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-b0 R
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1$
#2960
0$
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-b1001101 f
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0$
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-b10 R
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0$
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-b1001111 f
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0$
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-b100 R
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0$
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-b1010001 f
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1$
#2970
0$
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-b1 R
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1$
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0$
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-b1010011 f
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1$
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0$
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-b11 R
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0$
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-b1010101 f
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1$
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0$
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-b0 R
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1$
#2980
0$
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-b1010111 f
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0$
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-b10 R
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1$
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0$
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-b1011001 f
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1$
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0$
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-b100 R
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0$
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-b1011011 f
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1$
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0$
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-b1 R
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1$
#2992
0$
#2993
-b1011101 f
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1$
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0$
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-b11 R
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0$
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-b1011111 f
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1$
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0$
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1$
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0$
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-b1100001 f
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#3002
0$
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0$
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-b1100011 f
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0$
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0$
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-b1100101 f
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1$
#3010
0$
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-b1 R
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1$
#3012
0$
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-b1100111 f
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1$
#3014
0$
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-b11 R
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#3016
0$
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-b1101001 f
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0$
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1$
#3020
0$
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-b1101011 f
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0$
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-b10 R
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0$
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-b1101101 f
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1$
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0$
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-xN
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1$
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0$
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1$
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0$
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-b1 R
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1$
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0$
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-b1110001 f
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1$
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0$
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-b11 R
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0$
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-b1110011 f
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0$
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0$
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-b1110101 f
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0$
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-b10 R
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0$
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-b1110111 f
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0$
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-b100 R
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0$
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-b1111001 f
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1$
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0$
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-b1 R
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1$
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0$
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-b1111011 f
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1$
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0$
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-b11 R
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0$
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-b1111101 f
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-xN
+b1111101 h
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1$
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0$
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-b0 R
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1$
#3060
0$
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-b1111111 f
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0$
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-b10 R
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0$
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-b10000001 f
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0$
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-b100 R
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1$
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0$
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-b10000011 f
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b10011001100 -
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1$
#3070
0$
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-b1 R
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1$
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0$
#3073
-b10000101 f
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1$
#3074
0$
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-b11 R
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1$
#3076
0$
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-b10000111 f
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-xN
+b10000111 h
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1$
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0$
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-b0 R
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+b10011010000 W
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1$
#3080
0$
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-b10001001 f
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1$
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0$
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-b10 R
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1$
#3084
0$
#3085
-b10001011 f
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1$
#3086
0$
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-b100 R
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-xN
+b100 T
+b10001100 h
1$
#3088
0$
#3089
-b10001101 f
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-0%
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+b10011010100 W
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1$
#3090
0$
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-b1 R
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1$
#3092
0$
#3093
-b10001111 f
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1$
#3094
0$
#3095
-b11 R
-b10010000 f
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+b10010000 h
1$
#3096
0$
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-b10010001 f
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+b10010001 h
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1$
#3098
0$
#3099
-b0 R
-b10010010 f
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-b10011011000 U
-0%
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+b10011011000 W
b10011011000 E
1$
#3100
0$
#3101
-b10010011 f
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b10011011100 F
1$
#3102
0$
#3103
-b10 R
-b10010100 f
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+b10010100 h
1$
#3104
0$
#3105
-b10010101 f
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1$
#3106
0$
#3107
-b100 R
-b10010110 f
-x%
-xN
+b100 T
+b10010110 h
1$
#3108
0$
#3109
-b10010111 f
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+b0 T
b10011011100 -
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b10011011100 H
-b10011011100 U
-0%
-0N
+b10011011100 W
b10011011100 E
1$
#3110
0$
#3111
-b1 R
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b10011100000 F
-b10011000 f
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1$
#3112
0$
#3113
-b10011001 f
-b10 R
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1$
#3114
0$
#3115
-b11 R
-b10011010 f
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+b10011010 h
1$
#3116
0$
#3117
-b10011011 f
-b100 R
-x%
-xN
+b10011011 h
+b100 T
1$
#3118
0$
#3119
-b0 R
-b10011100 f
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b10011100000 -
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-b10011100000 U
-0%
-0N
+b10011100000 W
b10011100000 E
1$
#3120
0$
#3121
-b10011101 f
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b10011100100 F
1$
#3122
0$
#3123
-b10 R
-b10011110 f
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+b10011110 h
1$
#3124
0$
#3125
-b10011111 f
-b11 R
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1$
#3126
0$
#3127
-b100 R
-b10100000 f
-x%
-xN
+b100 T
+b10100000 h
1$
#3128
0$
#3129
-b10100001 f
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b10011100100 -
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b10011100100 H
-b10011100100 U
-0%
-0N
+b10011100100 W
b10011100100 E
1$
#3130
0$
#3131
-b1 R
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b10011101000 F
-b10100010 f
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1$
#3132
0$
#3133
-b10100011 f
-b10 R
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+b10 T
1$
#3134
0$
#3135
-b11 R
-b10100100 f
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+b10100100 h
1$
#3136
0$
#3137
-b10100101 f
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-x%
-xN
+b10100101 h
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1$
#3138
0$
#3139
-b0 R
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b10011101000 -
b10011101000 6
b10011101000 H
-b10011101000 U
-0%
-0N
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b10011101000 E
1$
#3140
0$
#3141
-b10100111 f
-b1 R
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b10011101100 F
1$
#3142
0$
#3143
-b10 R
-b10101000 f
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+b10101000 h
1$
#3144
0$
#3145
-b10101001 f
-b11 R
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+b11 T
1$
#3146
0$
#3147
-b100 R
-b10101010 f
-x%
-xN
+b100 T
+b10101010 h
1$
#3148
0$
#3149
-b10101011 f
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b10011101100 -
b10011101100 6
b10011101100 H
-b10011101100 U
-0%
-0N
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b10011101100 E
1$
#3150
0$
#3151
-b1 R
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b10011110000 F
-b10101100 f
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1$
#3152
0$
#3153
-b10101101 f
-b10 R
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+b10 T
1$
#3154
0$
#3155
-b11 R
-b10101110 f
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+b10101110 h
1$
#3156
0$
#3157
-b10101111 f
-b100 R
-x%
-xN
+b10101111 h
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1$
#3158
0$
#3159
-b0 R
-b10110000 f
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+b10110000 h
b10011110000 -
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b10011110000 H
-b10011110000 U
-0%
-0N
+b10011110000 W
b10011110000 E
1$
#3160
0$
#3161
-b10110001 f
-b1 R
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b10011110100 F
1$
#3162
0$
#3163
-b10 R
-b10110010 f
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+b10110010 h
1$
#3164
0$
#3165
-b10110011 f
-b11 R
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1$
#3166
0$
#3167
-b100 R
-b10110100 f
-x%
-xN
+b100 T
+b10110100 h
1$
#3168
0$
#3169
-b10110101 f
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b10011110100 -
b10011110100 6
b10011110100 H
-b10011110100 U
-0%
-0N
+b10011110100 W
b10011110100 E
1$
#3170
0$
#3171
-b1 R
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b10011111000 F
-b10110110 f
+b10110110 h
1$
#3172
0$
#3173
-b10110111 f
-b10 R
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+b10 T
1$
#3174
0$
#3175
-b11 R
-b10111000 f
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+b10111000 h
1$
#3176
0$
#3177
-b10111001 f
-b100 R
-x%
-xN
+b10111001 h
+b100 T
1$
#3178
0$
#3179
-b0 R
-b10111010 f
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+b10111010 h
b10011111000 -
b10011111000 6
b10011111000 H
-b10011111000 U
-0%
-0N
+b10011111000 W
b10011111000 E
1$
#3180
0$
#3181
-b10111011 f
-b1 R
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+b1 T
b10011111100 F
1$
#3182
0$
#3183
-b10 R
-b10111100 f
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+b10111100 h
1$
#3184
0$
#3185
-b10111101 f
-b11 R
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+b11 T
1$
#3186
0$
#3187
-b100 R
-b10111110 f
-x%
-xN
+b100 T
+b10111110 h
1$
#3188
0$
#3189
-b10111111 f
-b0 R
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b10011111100 -
b10011111100 6
b10011111100 H
-b10011111100 U
-0%
-0N
+b10011111100 W
b10011111100 E
1$
#3190
0$
#3191
-b1 R
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b10100000000 F
-b11000000 f
+b11000000 h
1$
#3192
0$
#3193
-b11000001 f
-b10 R
+b11000001 h
+b10 T
1$
#3194
0$
#3195
-b11 R
-b11000010 f
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+b11000010 h
1$
#3196
0$
#3197
-b11000011 f
-b100 R
-x%
-xN
+b11000011 h
+b100 T
1$
#3198
0$
#3199
-b0 R
-b11000100 f
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+b11000100 h
b10100000000 -
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b10100000000 H
-b10100000000 U
-0%
-0N
+b10100000000 W
b10100000000 E
1$
#3200
0$
#3201
-b11000101 f
-b1 R
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b10100000100 F
1$
#3202
0$
#3203
-b10 R
-b11000110 f
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+b11000110 h
1$
#3204
0$
#3205
-b11000111 f
-b11 R
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+b11 T
1$
#3206
0$
#3207
-b100 R
-b11001000 f
-x%
-xN
+b100 T
+b11001000 h
1$
#3208
0$
#3209
-b11001001 f
-b0 R
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b10100000100 -
b10100000100 6
b10100000100 H
-b10100000100 U
-0%
-0N
+b10100000100 W
b10100000100 E
1$
#3210
0$
#3211
-b1 R
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b10100001000 F
-b11001010 f
+b11001010 h
1$
#3212
0$
#3213
-b11001011 f
-b10 R
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+b10 T
1$
#3214
0$
#3215
-b11 R
-b11001100 f
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+b11001100 h
1$
#3216
0$
#3217
-b11001101 f
-b100 R
-x%
-xN
+b11001101 h
+b100 T
1$
#3218
0$
#3219
-b0 R
-b11001110 f
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b10100001000 -
b10100001000 6
b10100001000 H
-b10100001000 U
-0%
-0N
+b10100001000 W
b10100001000 E
1$
#3220
0$
#3221
-b11001111 f
-b1 R
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b10100001100 F
1$
#3222
0$
#3223
-b10 R
-b11010000 f
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+b11010000 h
1$
#3224
0$
#3225
-b11010001 f
-b11 R
+b11010001 h
+b11 T
1$
#3226
0$
#3227
-b100 R
-b11010010 f
-x%
-xN
+b100 T
+b11010010 h
1$
#3228
0$
#3229
-b11010011 f
-b0 R
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+b0 T
b10100001100 -
b10100001100 6
b10100001100 H
-b10100001100 U
-0%
-0N
+b10100001100 W
b10100001100 E
1$
#3230
0$
#3231
-b1 R
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b10100010000 F
-b11010100 f
+b11010100 h
1$
#3232
0$
#3233
-b11010101 f
-b10 R
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+b10 T
1$
#3234
0$
#3235
-b11 R
-b11010110 f
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+b11010110 h
1$
#3236
0$
#3237
-b11010111 f
-b100 R
-x%
-xN
+b11010111 h
+b100 T
1$
#3238
0$
#3239
-b0 R
-b11011000 f
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+b11011000 h
b10100010000 -
b10100010000 6
b10100010000 H
-b10100010000 U
-0%
-0N
+b10100010000 W
b10100010000 E
1$
#3240
0$
#3241
-b11011001 f
-b1 R
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+b1 T
b10100010100 F
1$
#3242
0$
#3243
-b10 R
-b11011010 f
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+b11011010 h
1$
#3244
0$
#3245
-b11011011 f
-b11 R
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+b11 T
1$
#3246
0$
#3247
-b100 R
-b11011100 f
-x%
-xN
+b100 T
+b11011100 h
1$
#3248
0$
#3249
-b11011101 f
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b10100010100 -
b10100010100 6
b10100010100 H
-b10100010100 U
-0%
-0N
+b10100010100 W
b10100010100 E
1$
#3250
0$
#3251
-b1 R
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b10100011000 F
-b11011110 f
+b11011110 h
1$
#3252
0$
#3253
-b11011111 f
-b10 R
+b11011111 h
+b10 T
1$
#3254
0$
#3255
-b11 R
-b11100000 f
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+b11100000 h
1$
#3256
0$
#3257
-b11100001 f
-b100 R
-x%
-xN
+b11100001 h
+b100 T
1$
#3258
0$
#3259
-b0 R
-b11100010 f
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+b11100010 h
b10100011000 -
b10100011000 6
b10100011000 H
-b10100011000 U
-0%
-0N
+b10100011000 W
b10100011000 E
1$
#3260
0$
#3261
-b11100011 f
-b1 R
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b10100011100 F
1$
#3262
0$
#3263
-b10 R
-b11100100 f
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+b11100100 h
1$
#3264
0$
#3265
-b11100101 f
-b11 R
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+b11 T
1$
#3266
0$
#3267
-b100 R
-b11100110 f
-x%
-xN
+b100 T
+b11100110 h
1$
#3268
0$
#3269
-b11100111 f
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b10100011100 -
b10100011100 6
b10100011100 H
-b10100011100 U
-0%
-0N
+b10100011100 W
b10100011100 E
1$
#3270
0$
#3271
-b1 R
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b10100100000 F
-b11101000 f
+b11101000 h
1$
#3272
0$
#3273
-b11101001 f
-b10 R
+b11101001 h
+b10 T
1$
#3274
0$
#3275
-b11 R
-1]
-b0 f
+b11 T
+1_
+b0 h
1$
#3276
0$
#3277
-0]
-b1 f
-b101 k
-b100 R
-x%
-xN
+0_
+b1 h
+b101 m
+b100 T
1$
#3278
0$
#3279
-b0 R
-b10 f
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+0!
+0o
+b10 h
b10100100000 -
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b10100100000 H
-b10100100000 U
-0%
-0N
+b10100100000 W
b10100100000 E
1$
#3280
0$
#3281
-b11 f
-b1 R
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+b1 T
b10100100100 F
1$
#3282
0$
#3283
-b10 R
-b100 f
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+b100 h
1$
#3284
0$
#3285
-b101 f
-b11 R
+b101 h
+b11 T
1$
#3286
0$
#3287
-b100 R
-b110 f
-x%
-xN
+b100 T
+b110 h
1$
#3288
0$
#3289
-b111 f
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b10100100100 -
b10100100100 6
b10100100100 H
-b10100100100 U
-0%
-0N
+b10100100100 W
b10100100100 E
1$
#3290
0$
#3291
-b1 R
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b10100101000 F
-b1000 f
+b1000 h
1$
#3292
0$
#3293
-b1001 f
-b10 R
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+b10 T
1$
#3294
0$
#3295
-b11 R
-b1010 f
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+b1010 h
1$
#3296
0$
#3297
-b1011 f
-b100 R
-x%
-xN
+b1011 h
+b100 T
1$
#3298
0$
#3299
-b0 R
-b1100 f
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+b1100 h
b10100101000 -
b10100101000 6
b10100101000 H
-b10100101000 U
-0%
-0N
+b10100101000 W
b10100101000 E
1$
#3300
0$
#3301
-b1101 f
-b1 R
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+b1 T
b10100101100 F
1$
#3302
0$
#3303
-b10 R
-b1110 f
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+b1110 h
1$
#3304
0$
#3305
-b1111 f
-b11 R
+b1111 h
+b11 T
1$
#3306
0$
#3307
-b100 R
-b10000 f
-x%
-xN
+b100 T
+b10000 h
1$
#3308
0$
#3309
-b10001 f
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b10100101100 -
b10100101100 6
b10100101100 H
-b10100101100 U
-0%
-0N
+b10100101100 W
b10100101100 E
1$
#3310
0$
#3311
-b1 R
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b10100110000 F
-b10010 f
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1$
#3312
0$
#3313
-b10011 f
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+b10 T
1$
#3314
0$
#3315
-b11 R
-b10100 f
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+b10100 h
1$
#3316
0$
#3317
-b10101 f
-b100 R
-x%
-xN
+b10101 h
+b100 T
1$
#3318
0$
#3319
-b0 R
-b10110 f
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+b10110 h
b10100110000 -
b10100110000 6
b10100110000 H
-b10100110000 U
-0%
-0N
+b10100110000 W
b10100110000 E
1$
#3320
0$
#3321
-b10111 f
-b1 R
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b10100110100 F
1$
#3322
0$
#3323
-b10 R
-b11000 f
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+b11000 h
1$
#3324
0$
#3325
-b11001 f
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+b11 T
1$
#3326
0$
#3327
-b100 R
-b11010 f
-x%
-xN
+b100 T
+b11010 h
1$
#3328
0$
#3329
-b11011 f
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b10100110100 -
b10100110100 6
b10100110100 H
-b10100110100 U
-0%
-0N
+b10100110100 W
b10100110100 E
1$
#3330
0$
#3331
-b1 R
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b10100111000 F
-b11100 f
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1$
#3332
0$
#3333
-b11101 f
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+b10 T
1$
#3334
0$
#3335
-b11 R
-b11110 f
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+b11110 h
1$
#3336
0$
#3337
-b11111 f
-b100 R
-x%
-xN
+b11111 h
+b100 T
1$
#3338
0$
#3339
-b0 R
-b100000 f
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+b100000 h
b10100111000 -
b10100111000 6
b10100111000 H
-b10100111000 U
-0%
-0N
+b10100111000 W
b10100111000 E
1$
#3340
0$
#3341
-b100001 f
-b1 R
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+b1 T
b10100111100 F
1$
#3342
0$
#3343
-b10 R
-b100010 f
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+b100010 h
1$
#3344
0$
#3345
-b100011 f
-b11 R
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+b11 T
1$
#3346
0$
#3347
-b100 R
-b100100 f
-x%
-xN
+b100 T
+b100100 h
1$
#3348
0$
#3349
-b100101 f
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+b0 T
b10100111100 -
b10100111100 6
b10100111100 H
-b10100111100 U
-0%
-0N
+b10100111100 W
b10100111100 E
1$
#3350
0$
#3351
-b1 R
+b1 T
b10101000000 F
-b100110 f
+b100110 h
1$
#3352
0$
#3353
-b100111 f
-b10 R
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+b10 T
1$
#3354
0$
#3355
-b11 R
-b101000 f
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+b101000 h
1$
#3356
0$
#3357
-b101001 f
-b100 R
-x%
-xN
+b101001 h
+b100 T
1$
#3358
0$
#3359
-b0 R
-b101010 f
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+b101010 h
b10101000000 -
b10101000000 6
b10101000000 H
-b10101000000 U
-0%
-0N
+b10101000000 W
b10101000000 E
1$
#3360
0$
#3361
-b101011 f
-b1 R
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b10101000100 F
1$
#3362
0$
#3363
-b10 R
-b101100 f
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+b101100 h
1$
#3364
0$
#3365
-b101101 f
-b11 R
+b101101 h
+b11 T
1$
#3366
0$
#3367
-b100 R
-b101110 f
-x%
-xN
+b100 T
+b101110 h
1$
#3368
0$
#3369
-b101111 f
-b0 R
+b101111 h
+b0 T
b10101000100 -
b10101000100 6
b10101000100 H
-b10101000100 U
-0%
-0N
+b10101000100 W
b10101000100 E
1$
#3370
0$
#3371
-b1 R
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b10101001000 F
-b110000 f
+b110000 h
1$
#3372
0$
#3373
-b110001 f
-b10 R
+b110001 h
+b10 T
1$
#3374
0$
#3375
-b11 R
-b110010 f
+b11 T
+b110010 h
1$
#3376
0$
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0$
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1$
#3380
0$
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-b110101 f
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0$
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#3384
0$
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-b110111 f
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#3386
0$
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1$
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0$
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1$
#3390
0$
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1$
#3392
0$
#3393
-b111011 f
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1$
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0$
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-b11 R
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#3396
0$
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-b111101 f
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0$
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1$
#3400
0$
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-b111111 f
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#3402
0$
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#3404
0$
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-b1000001 f
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0$
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#3408
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1$
#3410
0$
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0$
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1$
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0$
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0$
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0$
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1$
#3420
0$
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1$
#3422
0$
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#3424
0$
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#3426
0$
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#3428
0$
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1$
#3430
0$
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#3432
0$
#3433
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1$
#3434
0$
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#3436
0$
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0$
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1$
#3440
0$
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0$
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#3444
0$
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-b1010101 f
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1$
#3446
0$
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#3448
0$
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1$
#3450
0$
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1$
#3452
0$
#3453
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1$
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0$
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0$
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0$
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1$
#3460
0$
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1$
#3462
0$
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#3464
0$
#3465
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1$
#3466
0$
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0$
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1$
#3470
0$
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1$
#3472
0$
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1$
#3474
0$
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#3476
0$
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0$
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1$
#3480
0$
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#3482
0$
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#3484
0$
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#3486
0$
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0$
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1$
#3490
0$
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#3492
0$
#3493
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1$
#3494
0$
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#3496
0$
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#3498
0$
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1$
#3500
0$
#3501
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0$
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0$
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0$
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0$
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1$
#3510
0$
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#3512
0$
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1$
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0$
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#3516
0$
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0$
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1$
#3520
0$
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0$
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0$
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-b1111101 f
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0$
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0$
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1$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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1$
#3550
0$
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0$
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1$
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0$
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0$
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0$
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#3560
0$
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0$
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0$
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0$
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0$
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1$
#3570
0$
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0$
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1$
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0$
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0$
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0$
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1$
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0$
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0$
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0$
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0$
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0$
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1$
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0$
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0$
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0$
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0$
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0$
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#3600
0$
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0$
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0$
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0$
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0$
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1$
#3610
0$
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1$
#3612
0$
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1$
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0$
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0$
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1$
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0$
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1$
#3620
0$
#3621
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#3622
0$
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#3624
0$
#3625
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1$
#3626
0$
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1$
#3628
0$
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1$
#3630
0$
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1$
#3632
0$
#3633
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1$
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0$
#3635
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1$
#3636
0$
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1$
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0$
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1$
#3640
0$
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0$
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1$
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0$
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1$
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0$
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-xN
+b100 T
+b10111010 h
1$
#3648
0$
#3649
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-0%
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1$
#3650
0$
#3651
-b1 R
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1$
#3652
0$
#3653
-b10111101 f
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1$
#3654
0$
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-b11 R
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1$
#3656
0$
#3657
-b10111111 f
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1$
#3658
0$
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1$
#3660
0$
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-b11000001 f
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1$
#3662
0$
#3663
-b10 R
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1$
#3664
0$
#3665
-b11000011 f
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1$
#3666
0$
#3667
-b100 R
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1$
#3668
0$
#3669
-b11000101 f
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1$
#3670
0$
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-b1 R
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1$
#3672
0$
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-b11000111 f
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1$
#3674
0$
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-b11 R
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#3676
0$
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1$
#3678
0$
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1$
#3680
0$
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-b11001011 f
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0$
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1$
#3684
0$
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-b11001101 f
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1$
#3686
0$
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1$
#3688
0$
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1$
#3690
0$
#3691
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1$
#3692
0$
#3693
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1$
#3694
0$
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-b11 R
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1$
#3696
0$
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-b11010011 f
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1$
#3698
0$
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1$
#3700
0$
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-b11010101 f
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1$
#3702
0$
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1$
#3704
0$
#3705
-b11010111 f
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1$
#3706
0$
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1$
#3708
0$
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-0%
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1$
#3710
0$
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1$
#3712
0$
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-b11011011 f
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1$
#3714
0$
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-b11 R
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1$
#3716
0$
#3717
-b11011101 f
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1$
#3718
0$
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-b0 R
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1$
#3720
0$
#3721
-b11011111 f
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1$
#3722
0$
#3723
-b10 R
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1$
#3724
0$
#3725
-b11100001 f
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1$
#3726
0$
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-b100 R
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1$
#3728
0$
#3729
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-0%
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1$
#3730
0$
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-b1 R
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1$
#3732
0$
#3733
-b11100101 f
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1$
#3734
0$
#3735
-b11 R
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1$
#3736
0$
#3737
-b11100111 f
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1$
#3738
0$
#3739
-b0 R
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1$
#3740
0$
#3741
-b11101001 f
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1$
#3742
0$
#3743
-b10 R
-1]
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1$
#3744
0$
#3745
-0]
-b1 f
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1$
#3746
0$
#3747
-b100 R
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1$
#3748
0$
#3749
-b11 f
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-0%
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1$
#3750
0$
#3751
-b1 R
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1$
#3752
0$
#3753
-b101 f
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1$
#3754
0$
#3755
-b11 R
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1$
#3756
0$
#3757
-b111 f
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1$
#3758
0$
#3759
-b0 R
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b10111100000 -
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-0%
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1$
#3760
0$
#3761
-b1001 f
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1$
#3762
0$
#3763
-b10 R
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1$
#3764
0$
#3765
-b1011 f
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1$
#3766
0$
#3767
-b100 R
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1$
#3768
0$
#3769
-b1101 f
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b10111100100 -
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-0%
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1$
#3770
0$
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-b1 R
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1$
#3772
0$
#3773
-b1111 f
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1$
#3774
0$
#3775
-b11 R
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1$
#3776
0$
#3777
-b10001 f
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1$
#3778
0$
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-b0 R
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b10111101000 -
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1$
#3780
0$
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-b10011 f
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1$
#3782
0$
#3783
-b10 R
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1$
#3784
0$
#3785
-b10101 f
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1$
#3786
0$
#3787
-b100 R
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1$
#3788
0$
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-b10111 f
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b10111101100 -
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-0%
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1$
#3790
0$
#3791
-b1 R
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1$
#3792
0$
#3793
-b11001 f
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1$
#3794
0$
#3795
-b11 R
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1$
#3796
0$
#3797
-b11011 f
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1$
#3798
0$
#3799
-b0 R
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b10111110000 -
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-0%
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1$
#3800
0$
#3801
-b11101 f
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1$
#3802
0$
#3803
-b10 R
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1$
#3804
0$
#3805
-b11111 f
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1$
#3806
0$
#3807
-b100 R
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1$
#3808
0$
#3809
-b100001 f
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-0%
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1$
#3810
0$
#3811
-b1 R
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1$
#3812
0$
#3813
-b100011 f
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1$
#3814
0$
#3815
-b11 R
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1$
#3816
0$
#3817
-b100101 f
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-xN
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1$
#3818
0$
#3819
-b0 R
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b10111111000 -
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-0%
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b10111111000 E
1$
#3820
0$
#3821
-b100111 f
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1$
#3822
0$
#3823
-b10 R
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1$
#3824
0$
#3825
-b101001 f
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1$
#3826
0$
#3827
-b100 R
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1$
#3828
0$
#3829
-b101011 f
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1$
#3830
0$
#3831
-b1 R
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1$
#3832
0$
#3833
-b101101 f
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1$
#3834
0$
#3835
-b11 R
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1$
#3836
0$
#3837
-b101111 f
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-xN
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1$
#3838
0$
#3839
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b11000000000 -
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1$
#3840
0$
#3841
-b110001 f
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1$
#3842
0$
#3843
-b10 R
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1$
#3844
0$
#3845
-b110011 f
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1$
#3846
0$
#3847
-b100 R
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1$
#3848
0$
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b11000000100 -
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1$
#3850
0$
#3851
-b1 R
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1$
#3852
0$
#3853
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1$
#3854
0$
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1$
#3856
0$
#3857
-b111001 f
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1$
#3858
0$
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1$
#3860
0$
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-b111011 f
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1$
#3862
0$
#3863
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1$
#3864
0$
#3865
-b111101 f
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1$
#3866
0$
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-b100 R
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1$
#3868
0$
#3869
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b11000001100 -
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1$
#3870
0$
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-b1 R
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1$
#3872
0$
#3873
-b1000001 f
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1$
#3874
0$
#3875
-b11 R
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1$
#3876
0$
#3877
-b1000011 f
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-xN
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1$
#3878
0$
#3879
-b0 R
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b11000010000 -
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b11000010000 E
1$
#3880
0$
#3881
-b1000101 f
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b11000010100 F
1$
#3882
0$
#3883
-b10 R
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1$
#3884
0$
#3885
-b1000111 f
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1$
#3886
0$
#3887
-b100 R
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1$
#3888
0$
#3889
-b1001001 f
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b11000010100 -
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-0%
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b11000010100 E
1$
#3890
0$
#3891
-b1 R
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1$
#3892
0$
#3893
-b1001011 f
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1$
#3894
0$
#3895
-b11 R
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1$
#3896
0$
#3897
-b1001101 f
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-x%
-xN
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1$
#3898
0$
#3899
-b0 R
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b11000011000 -
b11000011000 6
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-0%
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b11000011000 E
1$
#3900
0$
#3901
-b1001111 f
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b11000011100 F
1$
#3902
0$
#3903
-b10 R
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1$
#3904
0$
#3905
-b1010001 f
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1$
#3906
0$
#3907
-b100 R
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-xN
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1$
#3908
0$
#3909
-b1010011 f
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b11000011100 -
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b11000011100 H
-b11000011100 U
-0%
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+b11000011100 W
b11000011100 E
1$
#3910
0$
#3911
-b1 R
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b11000100000 F
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1$
#3912
0$
#3913
-b1010101 f
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1$
#3914
0$
#3915
-b11 R
-b1010110 f
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+b1010110 h
1$
#3916
0$
#3917
-b1010111 f
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-x%
-xN
+b1010111 h
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1$
#3918
0$
#3919
-b0 R
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b11000100000 -
b11000100000 6
b11000100000 H
-b11000100000 U
-0%
-0N
+b11000100000 W
b11000100000 E
1$
#3920
0$
#3921
-b1011001 f
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0$
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0$
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0$
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0$
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1$
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#4100
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0$
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#4106
0$
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#4108
0$
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1$
#4110
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1$
#4112
0$
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1$
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0$
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0$
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1$
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0$
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1$
#4120
0$
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#4122
0$
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0$
#4125
-b10111111 f
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1$
#4126
0$
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1$
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0$
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1$
#4130
0$
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#4132
0$
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1$
#4134
0$
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#4136
0$
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#4138
0$
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1$
#4140
0$
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-b11000111 f
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#4142
0$
#4143
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#4144
0$
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-b11001001 f
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1$
#4146
0$
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1$
#4148
0$
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1$
#4150
0$
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1$
#4152
0$
#4153
-b11001101 f
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1$
#4154
0$
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-b11 R
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#4156
0$
#4157
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1$
#4158
0$
#4159
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1$
#4160
0$
#4161
-b11010001 f
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#4162
0$
#4163
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1$
#4164
0$
#4165
-b11010011 f
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1$
#4166
0$
#4167
-b100 R
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1$
#4168
0$
#4169
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1$
#4170
0$
#4171
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1$
#4172
0$
#4173
-b11010111 f
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1$
#4174
0$
#4175
-b11 R
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1$
#4176
0$
#4177
-b11011001 f
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1$
#4178
0$
#4179
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1$
#4180
0$
#4181
-b11011011 f
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1$
#4182
0$
#4183
-b10 R
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1$
#4184
0$
#4185
-b11011101 f
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1$
#4186
0$
#4187
-b100 R
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1$
#4188
0$
#4189
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1$
#4190
0$
#4191
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1$
#4192
0$
#4193
-b11100001 f
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1$
#4194
0$
#4195
-b11 R
-b11100010 f
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+b11100010 h
1$
#4196
0$
#4197
-b11100011 f
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-x%
-xN
+b11100011 h
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1$
#4198
0$
#4199
-b0 R
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b11010010000 -
b11010010000 6
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-b11010010000 U
-0%
-0N
+b11010010000 W
b11010010000 E
1$
#4200
0$
#4201
-b11100101 f
-b1 R
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b11010010100 F
1$
#4202
0$
#4203
-b10 R
-b11100110 f
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1$
#4204
0$
#4205
-b11100111 f
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1$
#4206
0$
#4207
-b100 R
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-x%
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+b100 T
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1$
#4208
0$
#4209
-b11101001 f
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b11010010100 -
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-b11010010100 U
-0%
-0N
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b11010010100 E
1$
#4210
0$
#4211
-b1 R
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b11010011000 F
-1]
-b0 f
+1_
+b0 h
1$
#4212
0$
#4213
-0]
-b1 f
-b111 k
-b10 R
+0_
+b1 h
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+b10 T
1$
#4214
0$
#4215
-b11 R
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1$
#4216
0$
#4217
-b11 f
-b100 R
-x%
-xN
+b11 h
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1$
#4218
0$
#4219
-b0 R
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b11010011000 -
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-0%
-0N
+b11010011000 W
b11010011000 E
1$
#4220
0$
#4221
-b101 f
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b11010011100 F
1$
#4222
0$
#4223
-b10 R
-b110 f
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1$
#4224
0$
#4225
-b111 f
-b11 R
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1$
#4226
0$
#4227
-b100 R
-b1000 f
-x%
-xN
+b100 T
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1$
#4228
0$
#4229
-b1001 f
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b11010011100 -
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-b11010011100 U
-0%
-0N
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b11010011100 E
1$
#4230
0$
#4231
-b1 R
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b11010100000 F
-b1010 f
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1$
#4232
0$
#4233
-b1011 f
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1$
#4234
0$
#4235
-b11 R
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1$
#4236
0$
#4237
-b1101 f
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-x%
-xN
+b1101 h
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1$
#4238
0$
#4239
-b0 R
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b11010100000 -
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-b11010100000 U
-0%
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1$
#4240
0$
#4241
-b1111 f
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b11010100100 F
1$
#4242
0$
#4243
-b10 R
-b10000 f
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1$
#4244
0$
#4245
-b10001 f
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1$
#4246
0$
#4247
-b100 R
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-x%
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+b100 T
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1$
#4248
0$
#4249
-b10011 f
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b11010100100 -
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-0%
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1$
#4250
0$
#4251
-b1 R
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b11010101000 F
-b10100 f
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1$
#4252
0$
#4253
-b10101 f
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1$
#4254
0$
#4255
-b11 R
-b10110 f
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1$
#4256
0$
#4257
-b10111 f
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-xN
+b10111 h
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1$
#4258
0$
#4259
-b0 R
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b11010101000 -
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-0%
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1$
#4260
0$
#4261
-b11001 f
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b11010101100 F
1$
#4262
0$
#4263
-b10 R
-b11010 f
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1$
#4264
0$
#4265
-b11011 f
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1$
#4266
0$
#4267
-b100 R
-b11100 f
-x%
-xN
+b100 T
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1$
#4268
0$
#4269
-b11101 f
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b11010101100 -
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-b11010101100 U
-0%
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b11010101100 E
1$
#4270
0$
#4271
-b1 R
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b11010110000 F
-b11110 f
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1$
#4272
0$
#4273
-b11111 f
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1$
#4274
0$
#4275
-b11 R
-b100000 f
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+b100000 h
1$
#4276
0$
#4277
-b100001 f
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-xN
+b100001 h
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1$
#4278
0$
#4279
-b0 R
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b11010110000 -
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-0%
-0N
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b11010110000 E
1$
#4280
0$
#4281
-b100011 f
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b11010110100 F
1$
#4282
0$
#4283
-b10 R
-b100100 f
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1$
#4284
0$
#4285
-b100101 f
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1$
#4286
0$
#4287
-b100 R
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-xN
+b100 T
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1$
#4288
0$
#4289
-b100111 f
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b11010110100 -
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-0%
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b11010110100 E
1$
#4290
0$
#4291
-b1 R
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b11010111000 F
-b101000 f
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1$
#4292
0$
#4293
-b101001 f
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1$
#4294
0$
#4295
-b11 R
-b101010 f
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+b101010 h
1$
#4296
0$
#4297
-b101011 f
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-x%
-xN
+b101011 h
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1$
#4298
0$
#4299
-b0 R
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b11010111000 -
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-0%
-0N
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b11010111000 E
1$
#4300
0$
#4301
-b101101 f
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b11010111100 F
1$
#4302
0$
#4303
-b10 R
-b101110 f
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1$
#4304
0$
#4305
-b101111 f
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1$
#4306
0$
#4307
-b100 R
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-xN
+b100 T
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1$
#4308
0$
#4309
-b110001 f
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b11010111100 -
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-0%
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b11010111100 E
1$
#4310
0$
#4311
-b1 R
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b11011000000 F
-b110010 f
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1$
#4312
0$
#4313
-b110011 f
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1$
#4314
0$
#4315
-b11 R
-b110100 f
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1$
#4316
0$
#4317
-b110101 f
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-xN
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1$
#4318
0$
#4319
-b0 R
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b11011000000 -
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-0%
-0N
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b11011000000 E
1$
#4320
0$
#4321
-b110111 f
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b11011000100 F
1$
#4322
0$
#4323
-b10 R
-b111000 f
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1$
#4324
0$
#4325
-b111001 f
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1$
#4326
0$
#4327
-b100 R
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+b100 T
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1$
#4328
0$
#4329
-b111011 f
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b11011000100 -
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-0%
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b11011000100 E
1$
#4330
0$
#4331
-b1 R
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b11011001000 F
-b111100 f
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1$
#4332
0$
#4333
-b111101 f
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1$
#4334
0$
#4335
-b11 R
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1$
#4336
0$
#4337
-b111111 f
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-xN
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1$
#4338
0$
#4339
-b0 R
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b11011001000 -
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-0%
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b11011001000 E
1$
#4340
0$
#4341
-b1000001 f
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b11011001100 F
1$
#4342
0$
#4343
-b10 R
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1$
#4344
0$
#4345
-b1000011 f
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1$
#4346
0$
#4347
-b100 R
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-xN
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1$
#4348
0$
#4349
-b1000101 f
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b11011001100 -
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-0%
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b11011001100 E
1$
#4350
0$
#4351
-b1 R
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b11011010000 F
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1$
#4352
0$
#4353
-b1000111 f
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1$
#4354
0$
#4355
-b11 R
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1$
#4356
0$
#4357
-b1001001 f
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1$
#4358
0$
#4359
-b0 R
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b11011010000 -
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1$
#4360
0$
#4361
-b1001011 f
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1$
#4362
0$
#4363
-b10 R
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1$
#4364
0$
#4365
-b1001101 f
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1$
#4366
0$
#4367
-b100 R
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1$
#4368
0$
#4369
-b1001111 f
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b11011010100 -
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-0%
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b11011010100 E
1$
#4370
0$
#4371
-b1 R
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b11011011000 F
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1$
#4372
0$
#4373
-b1010001 f
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1$
#4374
0$
#4375
-b11 R
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1$
#4376
0$
#4377
-b1010011 f
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1$
#4378
0$
#4379
-b0 R
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b11011011000 -
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-0%
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b11011011000 E
1$
#4380
0$
#4381
-b1010101 f
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b11011011100 F
1$
#4382
0$
#4383
-b10 R
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1$
#4384
0$
#4385
-b1010111 f
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1$
#4386
0$
#4387
-b100 R
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1$
#4388
0$
#4389
-b1011001 f
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b11011011100 -
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-0%
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b11011011100 E
1$
#4390
0$
#4391
-b1 R
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b11011100000 F
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1$
#4392
0$
#4393
-b1011011 f
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1$
#4394
0$
#4395
-b11 R
-b1011100 f
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1$
#4396
0$
#4397
-b1011101 f
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-xN
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1$
#4398
0$
#4399
-b0 R
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b11011100000 -
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-0%
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b11011100000 E
1$
#4400
0$
#4401
-b1011111 f
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b11011100100 F
1$
#4402
0$
#4403
-b10 R
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1$
#4404
0$
#4405
-b1100001 f
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1$
#4406
0$
#4407
-b100 R
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1$
#4408
0$
#4409
-b1100011 f
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b11011100100 -
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-0%
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b11011100100 E
1$
#4410
0$
#4411
-b1 R
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b11011101000 F
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1$
#4412
0$
#4413
-b1100101 f
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1$
#4414
0$
#4415
-b11 R
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1$
#4416
0$
#4417
-b1100111 f
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-xN
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1$
#4418
0$
#4419
-b0 R
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b11011101000 -
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b11011101000 H
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-0%
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b11011101000 E
1$
#4420
0$
#4421
-b1101001 f
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b11011101100 F
1$
#4422
0$
#4423
-b10 R
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1$
#4424
0$
#4425
-b1101011 f
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1$
#4426
0$
#4427
-b100 R
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-x%
-xN
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1$
#4428
0$
#4429
-b1101101 f
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b11011101100 -
b11011101100 6
b11011101100 H
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-0%
-0N
+b11011101100 W
b11011101100 E
1$
#4430
0$
#4431
-b1 R
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b11011110000 F
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1$
#4432
0$
#4433
-b1101111 f
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1$
#4434
0$
#4435
-b11 R
-b1110000 f
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1$
#4436
0$
#4437
-b1110001 f
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-xN
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1$
#4438
0$
#4439
-b0 R
-b1110010 f
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b11011110000 -
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-b11011110000 U
-0%
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+b11011110000 W
b11011110000 E
1$
#4440
0$
#4441
-b1110011 f
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b11011110100 F
1$
#4442
0$
#4443
-b10 R
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1$
#4444
0$
#4445
-b1110101 f
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1$
#4446
0$
#4447
-b100 R
-b1110110 f
-x%
-xN
+b100 T
+b1110110 h
1$
#4448
0$
#4449
-b1110111 f
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b11011110100 -
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b11011110100 H
-b11011110100 U
-0%
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+b11011110100 W
b11011110100 E
1$
#4450
0$
#4451
-b1 R
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b11011111000 F
-b1111000 f
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1$
#4452
0$
#4453
-b1111001 f
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1$
#4454
0$
#4455
-b11 R
-b1111010 f
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1$
#4456
0$
#4457
-b1111011 f
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-x%
-xN
+b1111011 h
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1$
#4458
0$
#4459
-b0 R
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b11011111000 -
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b11011111000 H
-b11011111000 U
-0%
-0N
+b11011111000 W
b11011111000 E
1$
#4460
0$
#4461
-b1111101 f
-b1 R
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b11011111100 F
1$
#4462
0$
#4463
-b10 R
-b1111110 f
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+b1111110 h
1$
#4464
0$
#4465
-b1111111 f
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1$
#4466
0$
#4467
-b100 R
-b10000000 f
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-xN
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+b10000000 h
1$
#4468
0$
#4469
-b10000001 f
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b11011111100 -
b11011111100 6
b11011111100 H
-b11011111100 U
-0%
-0N
+b11011111100 W
b11011111100 E
1$
#4470
0$
#4471
-b1 R
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1$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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#4646
0$
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1$
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0$
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1$
#4660
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0$
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1$
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1$
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1$
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1$
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0$
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0$
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1$
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0$
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1$
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1$
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1$
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1$
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0$
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1$
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0$
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1$
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0$
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0$
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1$
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0$
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0$
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0$
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0$
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1$
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0$
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0$
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1$
#4730
0$
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0$
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1$
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0$
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0$
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1$
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0$
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1$
#4740
0$
#4741
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b11101101100 F
1$
#4742
0$
#4743
-b10 R
-b100000 f
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1$
#4744
0$
#4745
-b100001 f
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1$
#4746
0$
#4747
-b100 R
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+b100 T
+b100010 h
1$
#4748
0$
#4749
-b100011 f
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b11101101100 -
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-b11101101100 U
-0%
-0N
+b11101101100 W
b11101101100 E
1$
#4750
0$
#4751
-b1 R
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b11101110000 F
-b100100 f
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1$
#4752
0$
#4753
-b100101 f
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1$
#4754
0$
#4755
-b11 R
-b100110 f
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+b100110 h
1$
#4756
0$
#4757
-b100111 f
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-xN
+b100111 h
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1$
#4758
0$
#4759
-b0 R
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b11101110000 -
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-b11101110000 U
-0%
-0N
+b11101110000 W
b11101110000 E
1$
#4760
0$
#4761
-b101001 f
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b11101110100 F
1$
#4762
0$
#4763
-b10 R
-b101010 f
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1$
#4764
0$
#4765
-b101011 f
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1$
#4766
0$
#4767
-b100 R
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-x%
-xN
+b100 T
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1$
#4768
0$
#4769
-b101101 f
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b11101110100 -
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-b11101110100 U
-0%
-0N
+b11101110100 W
b11101110100 E
1$
#4770
0$
#4771
-b1 R
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b11101111000 F
-b101110 f
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1$
#4772
0$
#4773
-b101111 f
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+b10 T
1$
#4774
0$
#4775
-b11 R
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1$
#4776
0$
#4777
-b110001 f
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-xN
+b110001 h
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1$
#4778
0$
#4779
-b0 R
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b11101111000 -
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-b11101111000 U
-0%
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b11101111000 E
1$
#4780
0$
#4781
-b110011 f
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b11101111100 F
1$
#4782
0$
#4783
-b10 R
-b110100 f
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1$
#4784
0$
#4785
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+b11 T
1$
#4786
0$
#4787
-b100 R
-b110110 f
-x%
-xN
+b100 T
+b110110 h
1$
#4788
0$
#4789
-b110111 f
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b11101111100 -
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-b11101111100 U
-0%
-0N
+b11101111100 W
b11101111100 E
1$
#4790
0$
#4791
-b1 R
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b11110000000 F
-b111000 f
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1$
#4792
0$
#4793
-b111001 f
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+b10 T
1$
#4794
0$
#4795
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-b111010 f
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+b111010 h
1$
#4796
0$
#4797
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-x%
-xN
+b111011 h
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1$
#4798
0$
#4799
-b0 R
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+b111100 h
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-b11110000000 U
-0%
-0N
+b11110000000 W
b11110000000 E
1$
#4800
0$
#4801
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-b1 R
+b111101 h
+b1 T
b11110000100 F
1$
#4802
0$
#4803
-b10 R
-b111110 f
+b10 T
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1$
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0$
#4805
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-b11 R
+b111111 h
+b11 T
1$
#4806
0$
#4807
-b100 R
-b1000000 f
-x%
-xN
+b100 T
+b1000000 h
1$
#4808
0$
#4809
-b1000001 f
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+b0 T
b11110000100 -
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-b11110000100 U
-0%
-0N
+b11110000100 W
b11110000100 E
1$
#4810
0$
#4811
-b1 R
+b1 T
b11110001000 F
-b1000010 f
+b1000010 h
1$
#4812
0$
#4813
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-b10 R
+b1000011 h
+b10 T
1$
#4814
0$
#4815
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-b1000100 f
+b11 T
+b1000100 h
1$
#4816
0$
#4817
-b1000101 f
-b100 R
-x%
-xN
+b1000101 h
+b100 T
1$
#4818
0$
#4819
-b0 R
-b1000110 f
+b0 T
+b1000110 h
b11110001000 -
b11110001000 6
b11110001000 H
-b11110001000 U
-0%
-0N
+b11110001000 W
b11110001000 E
1$
#4820
0$
#4821
-b1000111 f
-b1 R
+b1000111 h
+b1 T
b11110001100 F
1$
#4822
0$
#4823
-b10 R
-b1001000 f
+b10 T
+b1001000 h
1$
#4824
0$
#4825
-b1001001 f
-b11 R
+b1001001 h
+b11 T
1$
#4826
0$
#4827
-b100 R
-b1001010 f
-x%
-xN
+b100 T
+b1001010 h
1$
#4828
0$
#4829
-b1001011 f
-b0 R
+b1001011 h
+b0 T
b11110001100 -
b11110001100 6
b11110001100 H
-b11110001100 U
-0%
-0N
+b11110001100 W
b11110001100 E
1$
#4830
0$
#4831
-b1 R
+b1 T
b11110010000 F
-b1001100 f
+b1001100 h
1$
#4832
0$
#4833
-b1001101 f
-b10 R
+b1001101 h
+b10 T
1$
#4834
0$
#4835
-b11 R
-b1001110 f
+b11 T
+b1001110 h
1$
#4836
0$
#4837
-b1001111 f
-b100 R
-x%
-xN
+b1001111 h
+b100 T
1$
#4838
0$
#4839
-b0 R
-b1010000 f
+b0 T
+b1010000 h
b11110010000 -
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b11110010000 H
-b11110010000 U
-0%
-0N
+b11110010000 W
b11110010000 E
1$
#4840
0$
#4841
-b1010001 f
-b1 R
+b1010001 h
+b1 T
b11110010100 F
1$
#4842
0$
#4843
-b10 R
-b1010010 f
+b10 T
+b1010010 h
1$
#4844
0$
#4845
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-b11 R
+b1010011 h
+b11 T
1$
#4846
0$
#4847
-b100 R
-b1010100 f
-x%
-xN
+b100 T
+b1010100 h
1$
#4848
0$
#4849
-b1010101 f
-b0 R
+b1010101 h
+b0 T
b11110010100 -
b11110010100 6
b11110010100 H
-b11110010100 U
-0%
-0N
+b11110010100 W
b11110010100 E
1$
#4850
0$
#4851
-b1 R
+b1 T
b11110011000 F
-b1010110 f
+b1010110 h
1$
#4852
0$
#4853
-b1010111 f
-b10 R
+b1010111 h
+b10 T
1$
#4854
0$
#4855
-b11 R
-b1011000 f
+b11 T
+b1011000 h
1$
#4856
0$
#4857
-b1011001 f
-b100 R
-x%
-xN
+b1011001 h
+b100 T
1$
#4858
0$
#4859
-b0 R
-b1011010 f
+b0 T
+b1011010 h
b11110011000 -
b11110011000 6
b11110011000 H
-b11110011000 U
-0%
-0N
+b11110011000 W
b11110011000 E
1$
#4860
0$
#4861
-b1011011 f
-b1 R
+b1011011 h
+b1 T
b11110011100 F
1$
#4862
0$
#4863
-b10 R
-b1011100 f
+b10 T
+b1011100 h
1$
#4864
0$
#4865
-b1011101 f
-b11 R
+b1011101 h
+b11 T
1$
#4866
0$
#4867
-b100 R
-b1011110 f
-x%
-xN
+b100 T
+b1011110 h
1$
#4868
0$
#4869
-b1011111 f
-b0 R
+b1011111 h
+b0 T
b11110011100 -
b11110011100 6
b11110011100 H
-b11110011100 U
-0%
-0N
+b11110011100 W
b11110011100 E
1$
#4870
0$
#4871
-b1 R
+b1 T
b11110100000 F
-b1100000 f
+b1100000 h
1$
#4872
0$
#4873
-b1100001 f
-b10 R
+b1100001 h
+b10 T
1$
#4874
0$
#4875
-b11 R
-b1100010 f
+b11 T
+b1100010 h
1$
#4876
0$
#4877
-b1100011 f
-b100 R
-x%
-xN
+b1100011 h
+b100 T
1$
#4878
0$
#4879
-b0 R
-b1100100 f
+b0 T
+b1100100 h
b11110100000 -
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b11110100000 H
-b11110100000 U
-0%
-0N
+b11110100000 W
b11110100000 E
1$
#4880
0$
#4881
-b1100101 f
-b1 R
+b1100101 h
+b1 T
b11110100100 F
1$
#4882
0$
#4883
-b10 R
-b1100110 f
+b10 T
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1$
#4884
0$
#4885
-b1100111 f
-b11 R
+b1100111 h
+b11 T
1$
#4886
0$
#4887
-b100 R
-b1101000 f
-x%
-xN
+b100 T
+b1101000 h
1$
#4888
0$
#4889
-b1101001 f
-b0 R
+b1101001 h
+b0 T
b11110100100 -
b11110100100 6
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-b11110100100 U
-0%
-0N
+b11110100100 W
b11110100100 E
1$
#4890
0$
#4891
-b1 R
+b1 T
b11110101000 F
-b1101010 f
+b1101010 h
1$
#4892
0$
#4893
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-b10 R
+b1101011 h
+b10 T
1$
#4894
0$
#4895
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+b11 T
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1$
#4896
0$
#4897
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-b100 R
-x%
-xN
+b1101101 h
+b100 T
1$
#4898
0$
#4899
-b0 R
-b1101110 f
+b0 T
+b1101110 h
b11110101000 -
b11110101000 6
b11110101000 H
-b11110101000 U
-0%
-0N
+b11110101000 W
b11110101000 E
1$
#4900
0$
#4901
-b1101111 f
-b1 R
+b1101111 h
+b1 T
b11110101100 F
1$
#4902
0$
#4903
-b10 R
-b1110000 f
+b10 T
+b1110000 h
1$
#4904
0$
#4905
-b1110001 f
-b11 R
+b1110001 h
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1$
#4906
0$
#4907
-b100 R
-b1110010 f
-x%
-xN
+b100 T
+b1110010 h
1$
#4908
0$
#4909
-b1110011 f
-b0 R
+b1110011 h
+b0 T
b11110101100 -
b11110101100 6
b11110101100 H
-b11110101100 U
-0%
-0N
+b11110101100 W
b11110101100 E
1$
#4910
0$
#4911
-b1 R
+b1 T
b11110110000 F
-b1110100 f
+b1110100 h
1$
#4912
0$
#4913
-b1110101 f
-b10 R
+b1110101 h
+b10 T
1$
#4914
0$
#4915
-b11 R
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+b11 T
+b1110110 h
1$
#4916
0$
#4917
-b1110111 f
-b100 R
-x%
-xN
+b1110111 h
+b100 T
1$
#4918
0$
#4919
-b0 R
-b1111000 f
+b0 T
+b1111000 h
b11110110000 -
b11110110000 6
b11110110000 H
-b11110110000 U
-0%
-0N
+b11110110000 W
b11110110000 E
1$
#4920
0$
#4921
-b1111001 f
-b1 R
+b1111001 h
+b1 T
b11110110100 F
1$
#4922
0$
#4923
-b10 R
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+b10 T
+b1111010 h
1$
#4924
0$
#4925
-b1111011 f
-b11 R
+b1111011 h
+b11 T
1$
#4926
0$
#4927
-b100 R
-b1111100 f
-x%
-xN
+b100 T
+b1111100 h
1$
#4928
0$
#4929
-b1111101 f
-b0 R
+b1111101 h
+b0 T
b11110110100 -
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b11110110100 H
-b11110110100 U
-0%
-0N
+b11110110100 W
b11110110100 E
1$
#4930
0$
#4931
-b1 R
+b1 T
b11110111000 F
-b1111110 f
+b1111110 h
1$
#4932
0$
#4933
-b1111111 f
-b10 R
+b1111111 h
+b10 T
1$
#4934
0$
#4935
-b11 R
-b10000000 f
+b11 T
+b10000000 h
1$
#4936
0$
#4937
-b10000001 f
-b100 R
-x%
-xN
+b10000001 h
+b100 T
1$
#4938
0$
#4939
-b0 R
-b10000010 f
+b0 T
+b10000010 h
b11110111000 -
b11110111000 6
b11110111000 H
-b11110111000 U
-0%
-0N
+b11110111000 W
b11110111000 E
1$
#4940
0$
#4941
-b10000011 f
-b1 R
+b10000011 h
+b1 T
b11110111100 F
1$
#4942
0$
#4943
-b10 R
-b10000100 f
+b10 T
+b10000100 h
1$
#4944
0$
#4945
-b10000101 f
-b11 R
+b10000101 h
+b11 T
1$
#4946
0$
#4947
-b100 R
-b10000110 f
-x%
-xN
+b100 T
+b10000110 h
1$
#4948
0$
#4949
-b10000111 f
-b0 R
+b10000111 h
+b0 T
b11110111100 -
b11110111100 6
b11110111100 H
-b11110111100 U
-0%
-0N
+b11110111100 W
b11110111100 E
1$
#4950
0$
#4951
-b1 R
+b1 T
b11111000000 F
-b10001000 f
+b10001000 h
1$
#4952
0$
#4953
-b10001001 f
-b10 R
+b10001001 h
+b10 T
1$
#4954
0$
#4955
-b11 R
-b10001010 f
+b11 T
+b10001010 h
1$
#4956
0$
#4957
-b10001011 f
-b100 R
-x%
-xN
+b10001011 h
+b100 T
1$
#4958
0$
#4959
-b0 R
-b10001100 f
+b0 T
+b10001100 h
b11111000000 -
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b11111000000 H
-b11111000000 U
-0%
-0N
+b11111000000 W
b11111000000 E
1$
#4960
0$
#4961
-b10001101 f
-b1 R
+b10001101 h
+b1 T
b11111000100 F
1$
#4962
0$
#4963
-b10 R
-b10001110 f
+b10 T
+b10001110 h
1$
#4964
0$
#4965
-b10001111 f
-b11 R
+b10001111 h
+b11 T
1$
#4966
0$
#4967
-b100 R
-b10010000 f
-x%
-xN
+b100 T
+b10010000 h
1$
#4968
0$
#4969
-b10010001 f
-b0 R
+b10010001 h
+b0 T
b11111000100 -
b11111000100 6
b11111000100 H
-b11111000100 U
-0%
-0N
+b11111000100 W
b11111000100 E
1$
#4970
0$
#4971
-b1 R
+b1 T
b11111001000 F
-b10010010 f
+b10010010 h
1$
#4972
0$
#4973
-b10010011 f
-b10 R
+b10010011 h
+b10 T
1$
#4974
0$
#4975
-b11 R
-b10010100 f
+b11 T
+b10010100 h
1$
#4976
0$
#4977
-b10010101 f
-b100 R
-x%
-xN
+b10010101 h
+b100 T
1$
#4978
0$
#4979
-b0 R
-b10010110 f
+b0 T
+b10010110 h
b11111001000 -
b11111001000 6
b11111001000 H
-b11111001000 U
-0%
-0N
+b11111001000 W
b11111001000 E
1$
#4980
0$
#4981
-b10010111 f
-b1 R
+b10010111 h
+b1 T
b11111001100 F
1$
#4982
0$
#4983
-b10 R
-b10011000 f
+b10 T
+b10011000 h
1$
#4984
0$
#4985
-b10011001 f
-b11 R
+b10011001 h
+b11 T
1$
#4986
0$
#4987
-b100 R
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-x%
-xN
+b100 T
+b10011010 h
1$
#4988
0$
#4989
-b10011011 f
-b0 R
+b10011011 h
+b0 T
b11111001100 -
b11111001100 6
b11111001100 H
-b11111001100 U
-0%
-0N
+b11111001100 W
b11111001100 E
1$
#4990
0$
#4991
-b1 R
+b1 T
b11111010000 F
-b10011100 f
+b10011100 h
1$
#4992
0$
#4993
-b10011101 f
-b10 R
+b10011101 h
+b10 T
1$
#4994
0$
#4995
-b11 R
-b10011110 f
+b11 T
+b10011110 h
1$
#4996
0$
#4997
-b10011111 f
-b100 R
-x%
-xN
+b10011111 h
+b100 T
1$
#4998
0$
#4999
-b0 R
-b10100000 f
+b0 T
+b10100000 h
b11111010000 -
b11111010000 6
b11111010000 H
-b11111010000 U
-0%
-0N
+b11111010000 W
b11111010000 E
1$
#5000
0$
#5001
-b10100001 f
-b1 R
+b10100001 h
+b1 T
b11111010100 F
1$
#5002
0$
#5003
-b10 R
-b10100010 f
+b10 T
+b10100010 h
1$
#5004
0$
#5005
-b10100011 f
-b11 R
+b10100011 h
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1$
#5006
0$
#5007
-b100 R
-b10100100 f
-x%
-xN
+b100 T
+b10100100 h
1$
#5008
0$
#5009
-b10100101 f
-b0 R
+b10100101 h
+b0 T
b11111010100 -
b11111010100 6
b11111010100 H
-b11111010100 U
-0%
-0N
+b11111010100 W
b11111010100 E
1$
#5010
0$
#5011
-b1 R
+b1 T
b11111011000 F
-b10100110 f
+b10100110 h
1$
#5012
0$
#5013
-b10100111 f
-b10 R
+b10100111 h
+b10 T
1$
#5014
0$
#5015
-b11 R
-b10101000 f
+b11 T
+b10101000 h
1$
#5016
0$
#5017
-b10101001 f
-b100 R
-x%
-xN
+b10101001 h
+b100 T
1$
#5018
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0$
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1$
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1$
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1$
#5110
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0$
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1$
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1$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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1$
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0$
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0$
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1$
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0$
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0$
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0$
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0$
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0$
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1$
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0$
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1$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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#5292
0$
#5293
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1$
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0$
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0$
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1$
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1$
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0$
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0$
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1$
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0$
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0$
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1$
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0$
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0$
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1$
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0$
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1$
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0$
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1$
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0$
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0$
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0$
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1$
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0$
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1$
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1$
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0$
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0$
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0$
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1$
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0$
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1$
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0$
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0$
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0$
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0$
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1$
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0$
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0$
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1$
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0$
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0$
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0$
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0$
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1$
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0$
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0$
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1$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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1$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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1$
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0$
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1$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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0$
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1$
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0$
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0$
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1$
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0$
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1$
#6380
0$
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1$
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1$
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0$
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1$
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1$
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0$
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1$
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0$
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0$
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0$
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1$
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0$
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1$
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0$
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0$
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0$
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0$
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0$
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#7186
0$
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0$
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1$
#7190
0$
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0$
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1$
#7194
0$
#7195
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1$
#7196
0$
#7197
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1$
#7198
0$
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1$
#7200
0$
#7201
-b1011011 f
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1$
#7202
0$
#7203
-b10 R
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1$
#7204
0$
#7205
-b1011101 f
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1$
#7206
0$
#7207
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1$
#7208
0$
#7209
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b101101000100 -
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1$
#7210
0$
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1$
#7212
0$
#7213
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1$
#7214
0$
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1$
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0$
#7217
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1$
#7218
0$
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1$
#7220
0$
#7221
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1$
#7222
0$
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1$
#7224
0$
#7225
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1$
#7226
0$
#7227
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1$
#7228
0$
#7229
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b101101001100 -
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1$
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0$
#7231
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1$
#7232
0$
#7233
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1$
#7234
0$
#7235
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1$
#7236
0$
#7237
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1$
#7238
0$
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1$
#7240
0$
#7241
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1$
#7242
0$
#7243
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1$
#7244
0$
#7245
-b1110001 f
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1$
#7246
0$
#7247
-b100 R
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1$
#7248
0$
#7249
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1$
#7250
0$
#7251
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1$
#7252
0$
#7253
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1$
#7254
0$
#7255
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1$
#7256
0$
#7257
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1$
#7258
0$
#7259
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1$
#7260
0$
#7261
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1$
#7262
0$
#7263
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1$
#7264
0$
#7265
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1$
#7266
0$
#7267
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1$
#7268
0$
#7269
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b101101011100 -
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-0%
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1$
#7270
0$
#7271
-b1 R
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1$
#7272
0$
#7273
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1$
#7274
0$
#7275
-b11 R
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1$
#7276
0$
#7277
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1$
#7278
0$
#7279
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1$
#7280
0$
#7281
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1$
#7282
0$
#7283
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1$
#7284
0$
#7285
-b10000101 f
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1$
#7286
0$
#7287
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1$
#7288
0$
#7289
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1$
#7290
0$
#7291
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1$
#7292
0$
#7293
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1$
#7294
0$
#7295
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1$
#7296
0$
#7297
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1$
#7298
0$
#7299
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1$
#7300
0$
#7301
-b10001101 f
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1$
#7302
0$
#7303
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1$
#7304
0$
#7305
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1$
#7306
0$
#7307
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1$
#7308
0$
#7309
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1$
#7310
0$
#7311
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1$
#7312
0$
#7313
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1$
#7314
0$
#7315
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1$
#7316
0$
#7317
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1$
#7318
0$
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b101101110000 -
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1$
#7320
0$
#7321
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1$
#7322
0$
#7323
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1$
#7324
0$
#7325
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1$
#7326
0$
#7327
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1$
#7328
0$
#7329
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1$
#7330
0$
#7331
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1$
#7332
0$
#7333
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1$
#7334
0$
#7335
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1$
#7336
0$
#7337
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1$
#7338
0$
#7339
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1$
#7340
0$
#7341
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1$
#7342
0$
#7343
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1$
#7344
0$
#7345
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1$
#7346
0$
#7347
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1$
#7348
0$
#7349
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1$
#7350
0$
#7351
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1$
#7352
0$
#7353
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1$
#7354
0$
#7355
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1$
#7356
0$
#7357
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1$
#7358
0$
#7359
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1$
#7360
0$
#7361
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1$
#7362
0$
#7363
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1$
#7364
0$
#7365
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1$
#7366
0$
#7367
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1$
#7368
0$
#7369
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1$
#7370
0$
#7371
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1$
#7372
0$
#7373
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1$
#7374
0$
#7375
-b11 R
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1$
#7376
0$
#7377
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1$
#7378
0$
#7379
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1$
#7380
0$
#7381
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1$
#7382
0$
#7383
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1$
#7384
0$
#7385
-b10110111 f
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1$
#7386
0$
#7387
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1$
#7388
0$
#7389
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1$
#7390
0$
#7391
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1$
#7392
0$
#7393
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1$
#7394
0$
#7395
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1$
#7396
0$
#7397
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1$
#7398
0$
#7399
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1$
#7400
0$
#7401
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1$
#7402
0$
#7403
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1$
#7404
0$
#7405
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1$
#7406
0$
#7407
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1$
#7408
0$
#7409
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1$
#7410
0$
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1$
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0$
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1$
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0$
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1$
#7416
0$
#7417
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1$
#7418
0$
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1$
#7420
0$
#7421
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1$
#7422
0$
#7423
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1$
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0$
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1$
#7426
0$
#7427
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1$
#7428
0$
#7429
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1$
#7430
0$
#7431
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1$
#7432
0$
#7433
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1$
#7434
0$
#7435
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1$
#7436
0$
#7437
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1$
#7438
0$
#7439
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1$
#7440
0$
#7441
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1$
#7442
0$
#7443
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1$
#7444
0$
#7445
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1$
#7446
0$
#7447
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1$
#7448
0$
#7449
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1$
#7450
0$
#7451
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1$
#7452
0$
#7453
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1$
#7454
0$
#7455
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1$
#7456
0$
#7457
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1$
#7458
0$
#7459
-b0 R
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b101110101000 -
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1$
#7460
0$
#7461
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1$
#7462
0$
#7463
-b10 R
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1$
#7464
0$
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0$
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0$
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0$
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0$
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1$
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1$
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0$
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1$
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0$
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0$
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0$
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1$
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