mirror of
https://github.com/mii443/tangprimer-riscv.git
synced 2025-08-22 16:25:39 +00:00
35 lines
1.8 KiB
Plaintext
35 lines
1.8 KiB
Plaintext
GowinSynthesis start
|
|
Running parser ...
|
|
Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\memory.v'
|
|
Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\top.v'
|
|
Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\uart.v'
|
|
Analyzing Verilog file 'C:\Users\kuroc\Downloads\cpu\src\core.v'
|
|
Compiling module 'TOP'("C:\Users\kuroc\Downloads\cpu\src\top.v":1)
|
|
Compiling module 'UART'("C:\Users\kuroc\Downloads\cpu\src\uart.v":1)
|
|
WARN (EX3791) : Expression size 5 truncated to fit in target size 4("C:\Users\kuroc\Downloads\cpu\src\uart.v":98)
|
|
Compiling module 'MEMORY'("C:\Users\kuroc\Downloads\cpu\src\memory.v":1)
|
|
Extracting RAM for identifier 'mem'("C:\Users\kuroc\Downloads\cpu\src\memory.v":13)
|
|
Compiling module 'CORE'("C:\Users\kuroc\Downloads\cpu\src\core.v":1)
|
|
Extracting RAM for identifier 'register'("C:\Users\kuroc\Downloads\cpu\src\core.v":17)
|
|
WARN (EX3791) : Expression size 32 truncated to fit in target size 21("C:\Users\kuroc\Downloads\cpu\src\core.v":102)
|
|
NOTE (EX0101) : Current top module is "TOP"
|
|
[5%] Running netlist conversion ...
|
|
Running device independent optimization ...
|
|
[10%] Optimizing Phase 0 completed
|
|
[15%] Optimizing Phase 1 completed
|
|
[25%] Optimizing Phase 2 completed
|
|
Running inference ...
|
|
[30%] Inferring Phase 0 completed
|
|
[40%] Inferring Phase 1 completed
|
|
[50%] Inferring Phase 2 completed
|
|
[55%] Inferring Phase 3 completed
|
|
Running technical mapping ...
|
|
[60%] Tech-Mapping Phase 0 completed
|
|
[65%] Tech-Mapping Phase 1 completed
|
|
[75%] Tech-Mapping Phase 2 completed
|
|
[80%] Tech-Mapping Phase 3 completed
|
|
[90%] Tech-Mapping Phase 4 completed
|
|
[95%] Generate netlist file "C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg" completed
|
|
[100%] Generate report file "C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu_syn.rpt.html" completed
|
|
GowinSynthesis finish
|