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* Basic changes for RISC-V support * RISC-V in compiler LLVM * RISC-V support in dylib engine * RISC-V support in universal engine * Various small fixes * [RISCV] LLVM-riscv working, with some ignored tests to be worked on later * Update rustc to 4.65 (1.64 has some issue with riscv64 target) * Fixed some (new) Linting issues * Updated Cargo.toml and remove split-debuginfo for Windows build * Removed profile.dev from Cargo.toml as it cannot be per platform (breaks Windows). split-debug info is now the default value * Enable Cranelift compiler for RISCV * Update crates and fixed all the new clippy errors * Taken review remarks into account * Removed change from deny.toml, it's not needed anymore * Added some more comment about llvm abi hack * Added doc about current state of RISCV support * Fixed (newer) linter --------- Co-authored-by: Toru Nayuki <tnayuki@icloud.com>
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12 lines
757 B
Markdown
Executable File
# Current state of the RISCV support
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Only Cranelift and LLVM compiler are supported.
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Singlepass can be done, but no ressources are allocated on this task for now.
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Both LLVM and Cranelift support are quite new, and so it is expected to have a few things not working well.
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LLVM code needs a hack to force the ABI to "lp64d", and some tested with funciton & float/double values are still not working correctly and have be disable for now.
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On Cranelift, SIMD is not supported as the CPU doesn't have official SIMD/Vector extension for now, and no Workaround is in place.
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Test have be conducted on actual hardware, with a Vision Fixe 2 board running Debian. Some previous tests have also be done on a Vison Five 1 running Fedora (with LLVM only). |