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e03c902cb617414dae49d77a810f6957ff7affac
Under certain circumstances the emulation for the pseries "XICS" interrupt controller was clearing a pending interrupt from the XISR register, without also clearing the corresponding priority variable. This will cause problems later when can trigger sanity checks in the under-development in-kernel XICS implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
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