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When a TLB miss occurs while pre-decrement store instruction such as "mov.l Rm, @-Rn" is executed, re-execution of such instruction cause status confusion. Because pre Rn decrement is executed before TLB miss, re-execution decrements Rn again. In other words, in a translated instruction array, register status should not modified before memory access instruction. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5069 c046a42c-6fe2-441c-8c8c-71466251a162
Read the documentation in qemu-doc.html. Fabrice Bellard.
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