Currently, treat it exactly as a 53C895A.
53C895A is a 53C810 with more capabilities, so this should work.
However, this lets us test different code paths on Linux, which
don't use lastest features if it detect a 810, or on some OSes
which only support 810 and not 895A (like very old Windows NT
versions).
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
LSI emulation has been tested with Linux on PPC platform.
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
53C895A datasheet says that this register is read/write, and that the value
returned on read access is dependant of DMA FIFO state. However, nothing is
said for written value.
53C810A datasheet gives more insight about this register:
"This was a general purpose read/write register in previous SYM53C8XX
family chips. Although it is still a read/write register, Symbios reserves
the right to use these bits for future 53C8XX family enhancements."
This prevents going to the default case, which prints an error message.
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This prevents some (invalid) error messages on console.
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The existing driver just dropped unsupported requests. This adds error
responses to those unhandled requests.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This implements capabilities exchange between vscsi host and client. As
at the moment no capability is supported, put zero flags everywhere and
return.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Nikunj A. Dadhania <nikunj@linux.vnet.ibm.com>
Replace .bdrv_aio_discard with .bdrv_co_discard so that discard
requests can be split in multiple parts, each for a small amount
of sectors.
This is useful because we expose a generic API with no limit
on the amount of sectors that can be unmapped in one request.
Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
this patch adds a coroutine for .bdrv_co_block_status as well as
a generic framework that can be used to build coroutines in block/iscsi.
Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Use deposit32() rather than handcoded shifts/masks to update the
scratch registers. This is cleaner and incidentally avoids a clang
sanitizer complaint ("runtime error: left shift of 255 by 24 places
cannot be represented in type 'int'").
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Use sextract32() for doing sign-extension rather than rolling
our own implementation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
scsi_bus_legacy_add_drive() creates either a scsi-disk or a
scsi-generic device. It sets property "serial" to argument serial
unless null. Crashes with scsi-generic, because it doesn't have such
the property.
Only usb_msd_initfn_storage() passes non-null serial. Reproducer:
$ qemu-system-x86_64 -nodefaults -display none -S -usb \
-drive if=none,file=/dev/sg1,id=usb-drv0 \
-device usb-storage,id=usb-msd0,drive=usb-drv0,serial=123
qemu-system-x86_64: -device usb-storage,id=usb-msd0,drive=usb-drv0,serial=123: Property '.serial' not found
Aborted (core dumped)
Fix by handling exactly like "removable": set the property only when
it exists.
Cc: qemu-stable@nongnu.org
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
It's the abstract base of virtio-scsi-device and vhost-scsi.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
At the moment the guest kernel issues two types of task management
requests to the hypervisor - task about and lun reset. This adds
handling for these tasks. As spapr-vscsi starts calling scsi_req_cancel(),
free_request callback was implemented.
As virtio-vscsi, spapr-vscsi does not handle CLEAR_ACA either as CDB
control byte does not seem to be used at all so NACA bit is not
set to the guest so the guest has no good reason to call CLEAR_ACA task.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
[Fix choice of UCSOLCNT vs. SCSOLCNT. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The UUID is unique even across multiple hosts, thus it is
better than a VM name even if it is less user-friendly.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
ARM queue:
* aarch64 preparation patchset (excluding the defconfigs, so this
doesn't actually enable the new targets yet)
* minor bugfixes and cleanups
* disable "-cpu any" in system emulation mode
* fix ARMv7M stack alignment on reset
# gpg: Signature made Tue 10 Sep 2013 01:46:11 PM CDT using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found
# By Alexander Graf (13) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-20130910: (28 commits)
configure: Add handling code for AArch64 targets
linux-user: Add AArch64 support
linux-user: Allow targets to specify a minimum uname release
linux-user: Add AArch64 termbits.h definitions
linux-user: Implement cpu_set_tls() and cpu_clone_regs() for AArch64
linux-user: Make sure NWFPE code is 32 bit ARM only
linux-user: Add signal handling for AArch64
linux-user: Fix up AArch64 syscall handlers
linux-user: Add syscall number definitions for AArch64
linux-user: Add cpu loop for AArch64
linux-user: Don't treat AArch64 cpu names specially
target-arm: Add AArch64 gdbstub support
target-arm: Add AArch64 translation stub
target-arm: Prepare translation for AArch64 code
target-arm: Disable 32 bit CPUs in 64 bit linux-user builds
target-arm: Add new AArch64CPUInfo base class and subclasses
target-arm: Pass DisasContext* to gen_set_pc_im()
target-arm: Fix target_ulong/uint32_t confusions
target-arm: Export cpu_env
target-arm: Extract the disas struct to a header file
...
Message-id: 1378839142-7726-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
# By Gerd Hoffmann (2) and Christophe Fergeau (1)
# Via Gerd Hoffmann
* spice/spice.v73:
qxl: fix local renderer
qxl: trace io port name
spice-core: Use g_strdup_printf instead of snprintf
Message-id: 1378807572-27902-1-git-send-email-kraxel@redhat.com
Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
# By Gerd Hoffmann (2) and Miroslav Rezanina (2)
# Via Gerd Hoffmann
* kraxel/usb.89:
ehci: save device pointer in EHCIState
Remove dev-bluetooth.c dependency from vl.c
Preparation for usb-bt-dongle conditional build
usb: sanity check setup_index+setup_len in post_load
Message-id: 1378806073-25197-1-git-send-email-kraxel@redhat.com
Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
# By Tomoki Sekiyama (10) and Paul Burton (1)
# Via Michael Roth
* mdroth/qga-pull-2013-9-9:
QMP/qemu-ga-client: Make timeout longer for guest-fsfreeze-freeze command
qemu-ga: Install Windows VSS provider on `qemu-ga -s install'
qemu-ga: Call Windows VSS requester in fsfreeze command handler
qemu-ga: Add Windows VSS provider and requester as DLL
error: Add error_set_win32 and error_setg_win32
qemu-ga: Add configure options to specify path to Windows/VSS SDK
Add a script to extract VSS SDK headers on POSIX system
checkpatch.pl: Check .cpp files
Add c++ keywords to QAPI helper script
configure: Support configuring C++ compiler
mips_malta: support up to 2GiB RAM
Message-id: 1378755701-2051-1-git-send-email-mdroth@linux.vnet.ibm.com
Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
# By Paolo Bonzini (21) and others
# Via Stefan Hajnoczi
* stefanha/block: (42 commits)
qemu-iotests: Fixed test case 026
qemu-iotests: Whitespace cleanup
dataplane: Fix startup race.
block: look for zero blocks in bs->file
block: add default get_block_status implementation for protocols
raw-posix: report unwritten extents as zero
raw-posix: return get_block_status data and flags
docs, qapi: document qemu-img map
qemu-img: add a "map" subcommand
block: return BDRV_BLOCK_ZERO past end of backing file
block: use bdrv_has_zero_init to return BDRV_BLOCK_ZERO
block: return get_block_status data and flags for formats
block: define get_block_status return value
block: introduce bdrv_get_block_status API
block: make bdrv_has_zero_init return false for copy-on-write-images
qemu-img: always probe the input image for allocated sectors
block: expect errors from bdrv_co_is_allocated
block: remove bdrv_is_allocated_above/bdrv_co_is_allocated_above distinction
block: do not use ->total_sectors in bdrv_co_is_allocated
block: make bdrv_co_is_allocated static
...
Message-id: 1378481953-23099-1-git-send-email-stefanha@redhat.com
Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
# By Brad Smith (2) and others
# Via Stefan Hajnoczi
* stefanha/net:
ne2000: mark I/O as LITTLE_ENDIAN
vmxnet3: Eliminate __packed redefined warning
e1000: add interrupt mitigation support
net: Rename send_queue to incoming_queue
tap: Use numbered tap/tun devices on all *BSD OS's
Message-id: 1378481624-20964-1-git-send-email-stefanha@redhat.com
Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
For newer target architectures, glibc can be picky about the kernel
version: for example, it will not run on an aarch64 system unless
the kernel reports itself as at least 3.8.0. Accommodate this by
enhancing the existing support for faking the kernel version so
that each target can optionally specify a minimum version: if
the user doesn't force a specific fake version then we will override
with the minimum required version only if the real host kernel
version is insufficient.
Use this facility to let aarch64 report a minimum of 3.8.0.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-21-git-send-email-peter.maydell@linaro.org
On ARM, linux-user emulation includes NWFPE support for emulating the
ancient FPA floating point coprocessor. This has long since been
superseded by VFP and is only required for legacy binaries. The
AArch64 linux-user target doesn't compile in NWFPE support, so make
sure the relevant code is protected by suitable ifdefs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-18-git-send-email-peter.maydell@linaro.org
Add the main linux-user cpu loop for AArch64. Since AArch64
has a different system call interface, doesn't need to worry
about FPA emulation and may in the future keep the prefetch/data
abort information in different system registers, it's simplest
just to use a completely separate loop from the 32 bit ARM
target, rather than peppering it with ifdefs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-14-git-send-email-peter.maydell@linaro.org
We should translate AArch64 mode separately from AArch32 mode. In AArch64 mode,
registers look vastly different, instruction encoding is completely different,
basically the system turns into a different machine.
So let's do a simple if() in translate.c to decide whether we can handle the
current code in the legacy AArch32 code or in the new AArch64 code.
So far, the translation always complains about unallocated instructions. There
is no emulator functionality in this patch!
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-11-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-5-git-send-email-john.rigby@linaro.org
[PMM:
* provide no-op versions of a64 functions ifndef TARGET_AARCH64;
this lets us avoid #ifdefs in translate.c
* insert the missing call to disas_a64_insn()
* stash the insn in the DisasContext rather than reloading it in
real_unallocated_encoding()
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This patch adds all the prerequisites for AArch64 support that didn't
fit into split up patches. It extends important bits in the core cpu
headers to also take AArch64 mode into account.
Add new ARM_TBFLAG_AARCH64_STATE translation buffer flag
indicate an ARMv8 cpu running in aarch64 mode vs aarch32 mode.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: John Rigby <john.rigby@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-10-git-send-email-peter.maydell@linaro.org
Message-id: 1368505980-17151-4-git-send-email-john.rigby@linaro.org
[PMM:
* rearranged tbflags so AArch64? is bit 31 and if it is set then
30..0 are freely available for whatever makes most sense for that mode
* added version bump since we change VFP migration state
* added a comment about how VFP/Neon register state works
* physical address space is 48 bits, not 64
* added ARM_FEATURE_AARCH64 flag to identify 64-bit capable CPUs
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
AArch32 code (ie traditional 32 bit world) expects to be
able to pass a vaddr in a TCGv_i32. However when QEMU is
compiled with TARGET_LONG_BITS=32 the TCG load/store
functions take a TCGv_i64. Abstract out load/store with
a 32 bit vaddr so we have a place to put the zero extension
of the vaddr and the extension/truncation of the data value.
Apart from the function definitions most of this patch is
a simple s/tcg_gen_qemu_/gen_aa32_/.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1378235544-22290-3-git-send-email-peter.maydell@linaro.org
The ARM EABI specifies that 64 bit integers should be
8 aligned; remove our incorrect setting of 4 alignment.
This has no actual effect since it only set the alignment
for the 'abi_ullong' and 'abi_llong' types, which are used
only inside code which is MIPS-specific, but it will
avoid problems later if we use the types elsewhere.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Clarify a comment about the ID register value presented by
the PL110 variant present on the VersatilePB board (based
on testing what the actual hardware does), to indicate that
this is not an error in our emulation, and to remove an #if-0.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
When the initial SP is loaded from the vector table on ARMv7M systems the two
least significant bits are ignored as the stack is always aligned at a four byte
boundary (see ARM DDI 0403C, B1.4.1 and B1.5.5). So far QEMU did not ignore
these bits leading to a stack alignment inconsitent with real hardware for
binaries that rely on this behaviour. This patch fixes this issue by masking the
two least significant bits when loading the SP.
Signed-off-by: Sebastian Ottlik <ottlik@fzi.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1378286595-27072-1-git-send-email-ottlik@fzi.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Avoid the undefined behaviour of "1 << 31" by using 1U to make
the shift be of an unsigned value rather than shifting into the
sign bit of a signed integer. For consistency, we make all the
CPSR_* constants unsigned, though the only one which triggers
undefined behaviour is CPSR_N.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1378391908-22137-3-git-send-email-peter.maydell@linaro.org
