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target/microblaze: Use insn_start from DisasContextBase
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -62,9 +62,6 @@ typedef struct DisasContext {
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DisasContextBase base;
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const MicroBlazeCPUConfig *cfg;
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/* TCG op of the current insn_start. */
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TCGOp *insn_start;
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TCGv_i32 r0;
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bool r0_set;
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@ -699,14 +696,14 @@ static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb)
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static void record_unaligned_ess(DisasContext *dc, int rd,
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MemOp size, bool store)
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{
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uint32_t iflags = tcg_get_insn_start_param(dc->insn_start, 1);
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uint32_t iflags = tcg_get_insn_start_param(dc->base.insn_start, 1);
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iflags |= ESR_ESS_FLAG;
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iflags |= rd << 5;
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iflags |= store * ESR_S;
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iflags |= (size == MO_32) * ESR_W;
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tcg_set_insn_start_param(dc->insn_start, 1, iflags);
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tcg_set_insn_start_param(dc->base.insn_start, 1, iflags);
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}
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#endif
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@ -1624,7 +1621,6 @@ static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs)
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DisasContext *dc = container_of(dcb, DisasContext, base);
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tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK);
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dc->insn_start = tcg_last_op();
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}
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static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
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