fix warn
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@@ -47,7 +47,7 @@ pub fn unsubscribe(callback: SubscriberCallback) -> Result<(), &'static str> {
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for slot in subscribers.iter_mut() {
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for slot in subscribers.iter_mut() {
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if let Some(subscriber) = slot {
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if let Some(subscriber) = slot {
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if subscriber.callback == callback {
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if core::ptr::fn_addr_eq(subscriber.callback, callback) {
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*slot = None;
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*slot = None;
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return Ok(());
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return Ok(());
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}
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}
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@@ -10,11 +10,11 @@ use crate::vmm::x86_64::{
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};
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};
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pub fn handle_cr_access(vcpu: &mut IntelVCpu, qual: &QualCr) -> Result<(), &'static str> {
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pub fn handle_cr_access(vcpu: &mut IntelVCpu, qual: &QualCr) -> Result<(), &'static str> {
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match AccessType::try_from(qual.access_type()).unwrap() {
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match qual.access_type() {
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AccessType::MovTo => match qual.index() {
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AccessType::MovTo => match qual.index() {
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0 | 4 => {
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0 | 4 => {
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passthrough_write(vcpu, qual);
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passthrough_write(vcpu, qual)?;
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update_ia32e(vcpu);
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update_ia32e(vcpu)?;
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}
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}
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_ => panic!("Unsupported CR index: {}", qual.index()),
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_ => panic!("Unsupported CR index: {}", qual.index()),
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},
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},
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@@ -33,7 +33,7 @@ fn passthrough_read(vcpu: &mut IntelVCpu, qual: &QualCr) -> Result<(), &'static
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_ => panic!("Unsupported CR index: {}", qual.index()),
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_ => panic!("Unsupported CR index: {}", qual.index()),
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};
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};
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set_value(vcpu, qual, value);
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set_value(vcpu, qual, value)?;
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Ok(())
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Ok(())
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}
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}
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@@ -66,7 +66,7 @@ pub fn update_ia32e(vcpu: &mut IntelVCpu) -> Result<(), &'static str> {
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let mut entry_ctrl = super::vmcs::controls::EntryControls::read()?;
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let mut entry_ctrl = super::vmcs::controls::EntryControls::read()?;
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entry_ctrl.set_ia32e_mode_guest(ia32e_enabled);
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entry_ctrl.set_ia32e_mode_guest(ia32e_enabled);
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entry_ctrl.write();
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entry_ctrl.write()?;
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let mut efer = vmread(x86::vmx::vmcs::guest::IA32_EFER_FULL)?;
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let mut efer = vmread(x86::vmx::vmcs::guest::IA32_EFER_FULL)?;
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@@ -7,14 +7,7 @@ use crate::{
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vmm::x86_64::intel::{register::GuestRegisters, vmwrite},
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vmm::x86_64::intel::{register::GuestRegisters, vmwrite},
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};
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};
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#[derive(Default)]
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pub struct Serial {
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pub ier: u8,
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pub mcr: u8,
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub enum InitPhase {
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pub enum InitPhase {
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Uninitialized,
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Uninitialized,
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Phase1,
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Phase1,
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@@ -23,7 +16,7 @@ pub enum InitPhase {
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Initialized,
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Initialized,
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}
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}
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enum ReadSel {
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pub enum ReadSel {
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IRR,
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IRR,
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ISR,
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ISR,
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}
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}
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@@ -92,7 +92,7 @@ pub fn register_msrs(vcpu: &mut IntelVCpu) -> Result<(), MsrError> {
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Ok(())
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Ok(())
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}
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}
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pub fn update_msrs(vcpu: &mut IntelVCpu) -> Result<(), MsrError> {
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pub fn _update_msrs(vcpu: &mut IntelVCpu) -> Result<(), MsrError> {
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info!("updating MSRs");
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info!("updating MSRs");
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let indices_to_update: alloc::vec::Vec<u32> = vcpu
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let indices_to_update: alloc::vec::Vec<u32> = vcpu
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.host_msr
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.host_msr
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