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This commit is contained in:
Masato Imai
2025-08-11 07:48:34 +00:00
parent 52fe955b04
commit db6c38b6de
2 changed files with 3 additions and 8 deletions
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7
nel_os_kernel/src/vmm/x86_64/intel/msr.rs
View File

@ -65,9 +65,6 @@ pub fn register_msrs(vcpu: &mut IntelVCpu) -> Result<(), MsrError> {
read_msr(x86::msr::IA32_KERNEL_GSBASE), read_msr(x86::msr::IA32_KERNEL_GSBASE),
) )
.unwrap(); .unwrap();
vcpu.host_msr
.set(x86::msr::MSR_C5_PMON_BOX_CTRL, 0)
.unwrap();
vcpu.guest_msr.set(x86::msr::IA32_TSC_AUX, 0).unwrap(); vcpu.guest_msr.set(x86::msr::IA32_TSC_AUX, 0).unwrap();
vcpu.guest_msr.set(x86::msr::IA32_STAR, 0).unwrap(); vcpu.guest_msr.set(x86::msr::IA32_STAR, 0).unwrap();
@ -75,9 +72,6 @@ pub fn register_msrs(vcpu: &mut IntelVCpu) -> Result<(), MsrError> {
vcpu.guest_msr.set(x86::msr::IA32_CSTAR, 0).unwrap(); vcpu.guest_msr.set(x86::msr::IA32_CSTAR, 0).unwrap();
vcpu.guest_msr.set(x86::msr::IA32_FMASK, 0).unwrap(); vcpu.guest_msr.set(x86::msr::IA32_FMASK, 0).unwrap();
vcpu.guest_msr.set(x86::msr::IA32_KERNEL_GSBASE, 0).unwrap(); vcpu.guest_msr.set(x86::msr::IA32_KERNEL_GSBASE, 0).unwrap();
vcpu.guest_msr
.set(x86::msr::MSR_C5_PMON_BOX_CTRL, 0)
.unwrap();
/*vcpu.guest_msr.set(0x1b, 0).unwrap(); /*vcpu.guest_msr.set(0x1b, 0).unwrap();
vcpu.guest_msr.set(0xc0010007, 0).unwrap(); vcpu.guest_msr.set(0xc0010007, 0).unwrap();
vcpu.guest_msr.set(0xc0010117, 0).unwrap();*/ vcpu.guest_msr.set(0xc0010117, 0).unwrap();*/
@ -115,6 +109,7 @@ pub fn update_msrs(vcpu: &mut IntelVCpu) -> Result<(), MsrError> {
for index in indices_to_update { for index in indices_to_update {
info!("{}", index); info!("{}", index);
let value = read_msr(index); let value = read_msr(index);
info!("Setting MSR {:#x} to {:#x}", index, value);
vcpu.host_msr.set_by_index(index, value).unwrap(); vcpu.host_msr.set_by_index(index, value).unwrap();
} }

4
nel_os_kernel/src/vmm/x86_64/intel/vcpu.rs
View File

@ -121,7 +121,7 @@ impl IntelVCpu {
} }
fn vmentry(&mut self) -> Result<(), InstructionError> { fn vmentry(&mut self) -> Result<(), InstructionError> {
//msr::update_msrs(self).unwrap(); msr::update_msrs(self).unwrap();
let success = { let success = {
let result: u16; let result: u16;
@ -245,7 +245,7 @@ impl IntelVCpu {
vmwrite(vmcs::guest::CR3, unsafe { cr3() })?; vmwrite(vmcs::guest::CR3, unsafe { cr3() })?;
vmwrite( vmwrite(
vmcs::guest::CR4, vmcs::guest::CR4,
vmread(vmcs::guest::CR4)? | !Cr4Flags::VIRTUAL_MACHINE_EXTENSIONS.bits(), vmread(vmcs::guest::CR4)? & !Cr4Flags::VIRTUAL_MACHINE_EXTENSIONS.bits(),
)?; )?;
vmwrite(vmcs::guest::CS_BASE, 0)?; vmwrite(vmcs::guest::CS_BASE, 0)?;