From db6c38b6de1738adb2af8c0617ac7b94a40cd6a1 Mon Sep 17 00:00:00 2001
From: Masato Imai <mii@sfc.wide.ad.jp>
Date: Mon, 11 Aug 2025 07:48:34 +0000
Subject: [PATCH] wip

---
 nel_os_kernel/src/vmm/x86_64/intel/msr.rs  | 7 +------
 nel_os_kernel/src/vmm/x86_64/intel/vcpu.rs | 4 ++--
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/nel_os_kernel/src/vmm/x86_64/intel/msr.rs b/nel_os_kernel/src/vmm/x86_64/intel/msr.rs
index 96edf3d..ac021a6 100644
--- a/nel_os_kernel/src/vmm/x86_64/intel/msr.rs
+++ b/nel_os_kernel/src/vmm/x86_64/intel/msr.rs
@@ -65,9 +65,6 @@ pub fn register_msrs(vcpu: &mut IntelVCpu) -> Result<(), MsrError> {
             read_msr(x86::msr::IA32_KERNEL_GSBASE),
         )
         .unwrap();
-    vcpu.host_msr
-        .set(x86::msr::MSR_C5_PMON_BOX_CTRL, 0)
-        .unwrap();
 
     vcpu.guest_msr.set(x86::msr::IA32_TSC_AUX, 0).unwrap();
     vcpu.guest_msr.set(x86::msr::IA32_STAR, 0).unwrap();
@@ -75,9 +72,6 @@ pub fn register_msrs(vcpu: &mut IntelVCpu) -> Result<(), MsrError> {
     vcpu.guest_msr.set(x86::msr::IA32_CSTAR, 0).unwrap();
     vcpu.guest_msr.set(x86::msr::IA32_FMASK, 0).unwrap();
     vcpu.guest_msr.set(x86::msr::IA32_KERNEL_GSBASE, 0).unwrap();
-    vcpu.guest_msr
-        .set(x86::msr::MSR_C5_PMON_BOX_CTRL, 0)
-        .unwrap();
     /*vcpu.guest_msr.set(0x1b, 0).unwrap();
     vcpu.guest_msr.set(0xc0010007, 0).unwrap();
     vcpu.guest_msr.set(0xc0010117, 0).unwrap();*/
@@ -115,6 +109,7 @@ pub fn update_msrs(vcpu: &mut IntelVCpu) -> Result<(), MsrError> {
     for index in indices_to_update {
         info!("{}", index);
         let value = read_msr(index);
+        info!("Setting MSR {:#x} to {:#x}", index, value);
         vcpu.host_msr.set_by_index(index, value).unwrap();
     }
 
diff --git a/nel_os_kernel/src/vmm/x86_64/intel/vcpu.rs b/nel_os_kernel/src/vmm/x86_64/intel/vcpu.rs
index fca1b94..4fed84e 100644
--- a/nel_os_kernel/src/vmm/x86_64/intel/vcpu.rs
+++ b/nel_os_kernel/src/vmm/x86_64/intel/vcpu.rs
@@ -121,7 +121,7 @@ impl IntelVCpu {
     }
 
     fn vmentry(&mut self) -> Result<(), InstructionError> {
-        //msr::update_msrs(self).unwrap();
+        msr::update_msrs(self).unwrap();
 
         let success = {
             let result: u16;
@@ -245,7 +245,7 @@ impl IntelVCpu {
         vmwrite(vmcs::guest::CR3, unsafe { cr3() })?;
         vmwrite(
             vmcs::guest::CR4,
-            vmread(vmcs::guest::CR4)? | !Cr4Flags::VIRTUAL_MACHINE_EXTENSIONS.bits(),
+            vmread(vmcs::guest::CR4)? & !Cr4Flags::VIRTUAL_MACHINE_EXTENSIONS.bits(),
         )?;
 
         vmwrite(vmcs::guest::CS_BASE, 0)?;