mirror of
https://github.com/mii443/nel_os.git
synced 2025-08-22 16:15:38 +00:00
fix kernel panic
This commit is contained in:
Masato Imai
@ -30,6 +30,11 @@ macro_rules! info {
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($($arg:tt)*) => ($crate::print!("[info] {}\n", format_args!($($arg)*)));
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}
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#[macro_export]
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macro_rules! error {
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($($arg:tt)*) => ($crate::print!("[error] {}\n", format_args!($($arg)*)));
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}
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#[doc(hidden)]
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pub fn _print(args: fmt::Arguments) {
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use core::fmt::Write;
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@ -1,17 +1,48 @@
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use crate::info;
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use raw_cpuid::cpuid;
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use super::{vcpu::VCpu, vmcs::VmxLeaf};
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pub fn handle_cpuid_exit(vcpu: &mut VCpu) {
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let regs = &mut vcpu.guest_registers;
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//let vendor: &[u8; 12] = b"miHypervisor";
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let vendor: &[u8; 12] = b"KVMKVMKVMKVM";
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let vendor: &[u8; 12] = b"miHypervisor";
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let vendor = unsafe { core::mem::transmute::<&[u8; 12], &[u32; 3]>(vendor) };
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match VmxLeaf::from(regs.rax) {
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VmxLeaf::EXTENDED_ENUMERATION => {
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info!("CPUID: {:#x}.{:#x}", regs.rax, regs.rcx);
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match regs.rcx {
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0 => {
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// EAX: supported XSAVE features (x87=bit0, SSE=bit1)
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regs.rax = 0b11; // Only x87 and SSE supported
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regs.rbx = 576; // Size required for enabled features
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regs.rcx = 576; // Size required for all features
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regs.rdx = 0x00000000;
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}
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1 => {
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// EAX: XSAVEOPT and extended features
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regs.rax = 0x00000001; // XSAVEOPT supported
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regs.rbx = 0; // Size of enabled features in compacted format
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regs.rcx = 0; // Lower 32 bits of XCR0 | IA32_XSS
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regs.rdx = 0; // Upper 32 bits of XCR0 | IA32_XSS
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}
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2 => {
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// x87 state component
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regs.rax = 512; // Size of x87 state
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regs.rbx = 0; // Offset in save area
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regs.rcx = 0; // Not used for legacy components
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regs.rdx = 0; // Not used for legacy components
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}
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_ => {
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invalid(vcpu);
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}
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}
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}
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VmxLeaf::EXTENDED_FEATURE => match regs.rcx {
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0 => {
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let mut ebx = ExtFeatureEbx0::default();
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ebx.fsgsbase = false;
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ebx.smep = true;
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ebx.invpcid = false;
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ebx.smap = true;
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@ -70,15 +101,15 @@ pub fn handle_cpuid_exit(vcpu: &mut VCpu) {
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_reserved_0: false,
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pcid: true,
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dca: false,
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sse4_1: false,
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sse4_2: false,
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sse4_1: true,
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sse4_2: true,
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x2apic: false,
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movbe: false,
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popcnt: false,
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tsc_deadline: false,
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aesni: false,
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xsave: false,
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osxsave: false,
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xsave: true,
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osxsave: true,
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avx: false,
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f16c: false,
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rdrand: false,
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@ -94,7 +125,7 @@ pub fn handle_cpuid_exit(vcpu: &mut VCpu) {
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pae: true,
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mce: false,
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cx8: true,
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apic: false,
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apic: true,
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_reserved_0: false,
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sep: true,
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mtrr: false,
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@ -118,9 +149,14 @@ pub fn handle_cpuid_exit(vcpu: &mut VCpu) {
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_reserved_2: false,
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pbe: false,
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};
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let cpuid = cpuid!(0x1, 0);
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regs.rax = cpuid.eax as u64;
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regs.rbx = cpuid.ebx as u64;
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let mut version_and_feature_info = cpuid!(0x1, 0);
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let feature = cpuid!(0x0, 0);
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if !((feature.ecx & (1 << 17)) == 1) {
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version_and_feature_info.ecx &= !(1 << 17);
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}
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regs.rax = version_and_feature_info.eax as u64;
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regs.rbx = version_and_feature_info.ebx as u64;
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regs.rcx = ecx.to_u32() as u64;
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regs.rdx = edx.to_u32() as u64;
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}
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@ -132,6 +168,7 @@ pub fn handle_cpuid_exit(vcpu: &mut VCpu) {
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fn invalid(vcpu: &mut VCpu) {
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let regs = &mut vcpu.guest_registers;
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//info!("Invalid CPUID: {:#x}.{:#x}", regs.rax, regs.rcx);
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regs.rax = 0;
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regs.rbx = 0;
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@ -6,8 +6,6 @@ use x86::{
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vmx::vmcs,
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};
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use crate::info;
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use super::{
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qual::{AccessType, QualCr, Register},
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vcpu::VCpu,
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75
src/vmm/fpu.rs
Normal file
75
src/vmm/fpu.rs
Normal file
@ -0,0 +1,75 @@
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use bitfield::bitfield;
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use crate::{error, info};
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use super::vcpu::VCpu;
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bitfield! {
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pub struct XCR0(u64);
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pub x87, set_x87: 0, 1;
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pub sse, set_sse: 1, 1;
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pub avx, set_avx: 2, 1;
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pub bndreg, set_bndreg: 3, 1;
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pub bndcsr, set_bndcsr: 4, 1;
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pub opmask, set_opmask: 5, 1;
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pub zmm_hi256, set_zmm_hi256: 6, 1;
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pub hi16_zmm, set_hi16_zmm: 7, 1;
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pub pt, set_pt: 8, 1;
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pub pkru, set_pkru: 9, 1;
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pub pasid, set_pasid: 10, 1;
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pub cet_u, set_cet_u: 11, 1;
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pub cet_s, set_cet_s: 12, 1;
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pub hdc, set_hdc: 13, 1;
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pub intr, set_intr: 14, 1;
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pub lbr, set_lbr: 15, 1;
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pub hwp, set_hwp: 16, 1;
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pub xtilecfg, set_xtilecfg: 17, 1;
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pub xtiledata, set_xtiledata: 18, 1;
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pub apx, set_apx: 19, 1;
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pub reserved, set_reserved: 20, 44;
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}
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pub fn set_xcr(vcpu: &mut VCpu, index: u32, xcr: u64) -> Result<(), ()> {
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info!("Setting XCR0: index={}, xcr={:x}", index, xcr);
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if index != 0 {
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error!("Invalid XCR index: {}", index);
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return Err(());
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}
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if !(xcr & 0b1 != 0) {
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error!("X87 is not enabled");
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return Err(());
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}
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if (xcr & 0b100 != 0) && !(xcr & 0b10 != 0) {
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error!("SSE is not enabled");
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return Err(());
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}
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if !(xcr & 0b1000) != (!(xcr & 0b10000)) {
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error!("BNDREGS and BNDCSR are not both enabled");
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return Err(());
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}
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if xcr & 0b11100000 != 0 {
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if !(xcr & 0b100 != 0) {
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error!("YMM bits are not enabled");
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return Err(());
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}
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if (xcr & 0b11100000) != 0b11100000 {
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error!("Invalid bits set in XCR0");
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return Err(());
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}
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}
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if (xcr & 0b1000000000000 != 0) && (xcr & 0b1000000000000 != 0b1000000000000) {
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error!("xtile bits are not both enabled");
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return Err(());
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}
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vcpu.xcr0 = XCR0(xcr);
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Ok(())
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}
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@ -3,6 +3,7 @@ pub mod cpuid;
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pub mod cr;
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pub mod ept;
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pub mod error;
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pub mod fpu;
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pub mod linux;
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pub mod msr;
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pub mod qual;
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@ -128,7 +128,7 @@ impl ShadowMsr {
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}
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x86::msr::IA32_KERNEL_GSBASE => Self::shadow_read(vcpu, msr_kind),
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_ => {
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panic!("Unhandled RDMSR: {}", msr_kind);
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panic!("Unhandled RDMSR: {:#x}", msr_kind);
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}
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}
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}
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@ -145,6 +145,7 @@ impl ShadowMsr {
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x86::msr::IA32_TSC_AUX => Self::shadow_write(vcpu, msr_kind),
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x86::msr::IA32_FMASK => Self::shadow_write(vcpu, msr_kind),
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x86::msr::IA32_KERNEL_GSBASE => Self::shadow_write(vcpu, msr_kind),
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x86::msr::MSR_C5_PMON_BOX_CTRL => Self::shadow_write(vcpu, msr_kind),
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x86::msr::SYSENTER_CS_MSR => unsafe {
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vmwrite(vmcs::guest::IA32_SYSENTER_CS, value).unwrap()
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},
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@ -157,8 +158,9 @@ impl ShadowMsr {
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x86::msr::IA32_EFER => unsafe { vmwrite(vmcs::guest::IA32_EFER_FULL, value).unwrap() },
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x86::msr::IA32_FS_BASE => unsafe { vmwrite(vmcs::guest::FS_BASE, value).unwrap() },
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x86::msr::IA32_GS_BASE => unsafe { vmwrite(vmcs::guest::GS_BASE, value).unwrap() },
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_ => {
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panic!("Unhandled WRMSR: {}", msr_kind);
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panic!("Unhandled WRMSR: {:#x}", msr_kind);
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}
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}
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}
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@ -125,3 +125,16 @@ impl QualCr {
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self.set_register_raw(val as u8);
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}
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}
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bitfield! {
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#[derive(Clone, Copy)]
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pub struct QualIo(u64);
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impl Debug;
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u8, size, set_size: 3, 0;
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u8, direction, set_direction: 4, 4;
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u8, string, set_string: 5, 5;
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u8, rep, set_rep: 6, 6;
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u8, operand_encoding, set_operand_encoding: 7, 7;
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u16, port, set_port: 31, 16;
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}
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100
src/vmm/vcpu.rs
100
src/vmm/vcpu.rs
@ -1,4 +1,7 @@
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use core::u64;
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use core::{
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arch::x86_64::{_xgetbv, _xsetbv},
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u64,
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};
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use x86::{
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bits64::vmx::{vmread, vmwrite},
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@ -13,7 +16,7 @@ use crate::{
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info,
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memory::BootInfoFrameAllocator,
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vmm::{
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cpuid, cr, msr,
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cpuid, cr, fpu, msr,
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qual::QualCr,
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vmcs::{
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DescriptorType, EntryControls, Granularity, PrimaryExitControls,
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@ -25,6 +28,7 @@ use crate::{
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use super::{
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ept::{EPT, EPTP},
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fpu::XCR0,
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linux::{self, BootParams, E820Type},
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msr::ShadowMsr,
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register::GuestRegisters,
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@ -44,6 +48,8 @@ pub struct VCpu {
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pub host_msr: ShadowMsr,
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pub guest_msr: ShadowMsr,
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pub ia32e_enabled: bool,
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pub xcr0: XCR0,
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pub host_xcr0: u64,
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}
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const TEMP_STACK_SIZE: usize = 4096;
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@ -68,6 +74,8 @@ impl VCpu {
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host_msr: ShadowMsr::new(),
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guest_msr: ShadowMsr::new(),
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ia32e_enabled: false,
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xcr0: XCR0(3),
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host_xcr0: 0,
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}
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}
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@ -200,6 +208,9 @@ impl VCpu {
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rdmsr(x86::msr::IA32_KERNEL_GSBASE) as u64,
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)
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.unwrap();
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self.host_msr
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.set(x86::msr::MSR_C5_PMON_BOX_CTRL, 0)
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.unwrap();
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self.guest_msr.set(x86::msr::IA32_TSC_AUX, 0).unwrap();
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self.guest_msr.set(x86::msr::IA32_STAR, 0).unwrap();
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@ -207,6 +218,9 @@ impl VCpu {
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self.guest_msr.set(x86::msr::IA32_CSTAR, 0).unwrap();
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self.guest_msr.set(x86::msr::IA32_FMASK, 0).unwrap();
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self.guest_msr.set(x86::msr::IA32_KERNEL_GSBASE, 0).unwrap();
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self.guest_msr
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.set(x86::msr::MSR_C5_PMON_BOX_CTRL, 0)
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.unwrap();
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vmwrite(
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vmcs::control::VMEXIT_MSR_LOAD_ADDR_FULL,
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@ -286,10 +300,11 @@ impl VCpu {
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primary_exec_ctrl.0 |= (reserved_bits & 0xFFFFFFFF) as u32;
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primary_exec_ctrl.0 &= (reserved_bits >> 32) as u32;
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primary_exec_ctrl.set_hlt(true);
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primary_exec_ctrl.set_hlt(false);
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primary_exec_ctrl.set_activate_secondary_controls(true);
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primary_exec_ctrl.set_use_tpr_shadow(true);
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primary_exec_ctrl.set_use_msr_bitmap(false);
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primary_exec_ctrl.set_unconditional_io(true);
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primary_exec_ctrl.write();
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@ -365,6 +380,14 @@ impl VCpu {
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exit_ctrl.write();
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unsafe {
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vmwrite(
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vmcs::control::EXCEPTION_BITMAP,
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0, /*(1u64 << irq::INVALID_OPCODE_VECTOR)*/
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)
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.unwrap();
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};
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Ok(())
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}
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@ -373,7 +396,10 @@ impl VCpu {
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unsafe {
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vmwrite(vmcs::host::CR0, cr0().bits() as u64)?;
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vmwrite(vmcs::host::CR3, cr3())?;
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vmwrite(vmcs::host::CR4, cr4().bits() as u64)?;
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vmwrite(
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vmcs::host::CR4,
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cr4().bits() as u64 | Cr4Flags::OSXSAVE.bits(),
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)?;
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vmwrite(vmcs::host::RIP, crate::vmm::asm::asm_vmexit_handler as u64)?;
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vmwrite(
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@ -433,10 +459,7 @@ impl VCpu {
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vmwrite(vmcs::guest::CR3, cr3())?;
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vmwrite(
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vmcs::guest::CR4,
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vmread(vmcs::guest::CR4)?
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| 1 << 5
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| 1 << 7
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| Cr4Flags::VIRTUAL_MACHINE_EXTENSIONS.bits(),
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vmread(vmcs::guest::CR4)? | Cr4Flags::VIRTUAL_MACHINE_EXTENSIONS.bits(),
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)?;
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vmwrite(vmcs::guest::CS_BASE, 0)?;
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@ -570,13 +593,57 @@ impl VCpu {
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}
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}
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fn load_guest_xcr0(&mut self) -> Result<(), VmFail> {
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let host_cr4 = unsafe { cr4() };
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if (host_cr4.bits() & Cr4Flags::OSXSAVE.bits() as usize) == 0 {
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return Ok(());
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}
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if self.host_xcr0 == 0 {
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self.host_xcr0 = unsafe { _xgetbv(0) };
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}
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let guest_cr4 = unsafe { vmread(vmcs::guest::CR4)? };
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if guest_cr4 & Cr4Flags::OSXSAVE.bits() != 0 && self.xcr0.0 != self.host_xcr0 {
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unsafe {
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_xsetbv(0, self.xcr0.0);
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}
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}
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Ok(())
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}
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fn load_host_xcr0(&mut self) -> Result<(), VmFail> {
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let host_cr4 = unsafe { cr4() };
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if (host_cr4.bits() & Cr4Flags::OSXSAVE.bits() as usize) == 0 {
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return Ok(());
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}
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let guest_cr4 = unsafe { vmread(vmcs::guest::CR4)? };
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if guest_cr4 & Cr4Flags::OSXSAVE.bits() != 0 {
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let current_xcr0 = unsafe { _xgetbv(0) };
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if current_xcr0 != self.host_xcr0 {
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self.xcr0 = XCR0(current_xcr0);
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unsafe {
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_xsetbv(0, self.host_xcr0);
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}
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}
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}
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Ok(())
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}
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|
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fn vmentry(&mut self) -> Result<(), InstructionError> {
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let success = {
|
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let result: u16;
|
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|
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self.load_guest_xcr0().unwrap();
|
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unsafe {
|
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result = crate::vmm::asm::asm_vm_entry(self as *mut _);
|
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};
|
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self.load_host_xcr0().unwrap();
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result == 0
|
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};
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@ -627,6 +694,7 @@ impl VCpu {
|
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_ => {}
|
||||
}
|
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} else {
|
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info!("RIP: {:#x}", unsafe { vmread(vmcs::guest::RIP) }.unwrap());
|
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match info.get_reason() {
|
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VmxExitReason::HLT => {
|
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info!("HLT instruction executed");
|
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@ -649,6 +717,22 @@ impl VCpu {
|
||||
cr::handle_cr_access(self, &qual);
|
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self.step_next_inst().unwrap();
|
||||
}
|
||||
VmxExitReason::XSETBV => {
|
||||
fpu::set_xcr(
|
||||
self,
|
||||
self.guest_registers.rcx as u32,
|
||||
self.guest_registers.rax,
|
||||
)
|
||||
.unwrap();
|
||||
self.step_next_inst().unwrap();
|
||||
}
|
||||
VmxExitReason::EXCEPTION => {
|
||||
self.step_next_inst().unwrap();
|
||||
}
|
||||
VmxExitReason::IO_INSTRUCTION => {
|
||||
info!("IO instruction executed");
|
||||
self.step_next_inst().unwrap();
|
||||
}
|
||||
_ => {
|
||||
panic!("VMExit reason: {:?}", info.get_reason());
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user