mirror of
https://github.com/mii443/nel_os.git
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AMD-V on Intel VT-d
This commit is contained in:
Masato Imai
@ -7,6 +7,8 @@ use x86::vmx::vmcs;
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use x86_64::structures::paging::{OffsetPageTable, Translate};
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use x86_64::{PhysAddr, VirtAddr};
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use crate::info;
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use super::vcpu::VCpu;
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type MsrIndex = u32;
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@ -132,7 +134,7 @@ impl ShadowMsr {
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// Lock bit (0) | Enable VMX inside SMX (1) | Enable VMX outside SMX (2)
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Self::set_ret_val(vcpu, 0x5)
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}
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0x48 => Self::set_ret_val(vcpu, 0), // IA32_SPEC_CTRL
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0x48 => Self::set_ret_val(vcpu, 0), // IA32_SPEC_CTRL
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0x122 => Self::set_ret_val(vcpu, 0), // IA32_TSX_CTRL
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0x560 => Self::set_ret_val(vcpu, 0), // IA32_RTIT_OUTPUT_BASE
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0x561 => Self::set_ret_val(vcpu, 0), // IA32_RTIT_OUTPUT_MASK_PTRS
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@ -158,15 +160,15 @@ impl ShadowMsr {
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x86::msr::IA32_LSTAR => Self::shadow_read(vcpu, msr_kind),
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x86::msr::IA32_CSTAR => Self::shadow_read(vcpu, msr_kind),
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x86::msr::IA32_FMASK => Self::shadow_read(vcpu, msr_kind),
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x86::msr::SYSENTER_CS_MSR => {
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Self::set_ret_val(vcpu, unsafe { vmread(vmcs::guest::IA32_SYSENTER_CS).unwrap() })
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}
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x86::msr::SYSENTER_ESP_MSR => {
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Self::set_ret_val(vcpu, unsafe { vmread(vmcs::guest::IA32_SYSENTER_ESP).unwrap() })
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}
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x86::msr::SYSENTER_EIP_MSR => {
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Self::set_ret_val(vcpu, unsafe { vmread(vmcs::guest::IA32_SYSENTER_EIP).unwrap() })
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}
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x86::msr::SYSENTER_CS_MSR => Self::set_ret_val(vcpu, unsafe {
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vmread(vmcs::guest::IA32_SYSENTER_CS).unwrap()
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}),
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x86::msr::SYSENTER_ESP_MSR => Self::set_ret_val(vcpu, unsafe {
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vmread(vmcs::guest::IA32_SYSENTER_ESP).unwrap()
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}),
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x86::msr::SYSENTER_EIP_MSR => Self::set_ret_val(vcpu, unsafe {
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vmread(vmcs::guest::IA32_SYSENTER_EIP).unwrap()
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}),
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0x1b => Self::shadow_read(vcpu, msr_kind),
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0x8b => Self::set_ret_val(vcpu, 0x8701021),
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0xc0011029 => Self::set_ret_val(vcpu, 0x3000310e08202),
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@ -179,10 +181,10 @@ impl ShadowMsr {
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0xc0010117 => Self::set_ret_val(vcpu, 0), // MSR_VM_HSAVE_PA
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0x277 => Self::set_ret_val(vcpu, 0x0007040600070406),
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0xc0000103 => Self::shadow_read(vcpu, msr_kind), // TSC_AUX
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0xd90 => Self::set_ret_val(vcpu, 0), // MSR_C1_PMON_EVNT_SEL0
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0xe1 => Self::set_ret_val(vcpu, 0), // IA32_UMWAIT_CONTROL
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0x1c4 => Self::set_ret_val(vcpu, 0), // Unknown MSR
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0x1c5 => Self::set_ret_val(vcpu, 0), // Unknown MSR
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0xd90 => Self::set_ret_val(vcpu, 0), // MSR_C1_PMON_EVNT_SEL0
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0xe1 => Self::set_ret_val(vcpu, 0), // IA32_UMWAIT_CONTROL
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0x1c4 => Self::set_ret_val(vcpu, 0), // Unknown MSR
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0x1c5 => Self::set_ret_val(vcpu, 0), // Unknown MSR
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_ => {
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panic!("Unhandled RDMSR: {:#x}", msr_kind);
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}
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@ -218,11 +220,17 @@ impl ShadowMsr {
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x86::msr::SYSENTER_ESP_MSR => unsafe {
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vmwrite(vmcs::guest::IA32_SYSENTER_ESP, value).unwrap()
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},
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x86::msr::IA32_EFER => unsafe { vmwrite(vmcs::guest::IA32_EFER_FULL, value).unwrap() },
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x86::msr::IA32_EFER => {
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info!("Setting IA32_EFER: {:#x}", value);
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if value == 0xd01 || value == 0x100 {
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unsafe { vmwrite(vmcs::guest::IA32_EFER_FULL, value).unwrap() }
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}
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}
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x86::msr::IA32_FS_BASE => unsafe { vmwrite(vmcs::guest::FS_BASE, value).unwrap() },
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x86::msr::IA32_GS_BASE => unsafe { vmwrite(vmcs::guest::GS_BASE, value).unwrap() },
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0x1b => Self::shadow_write(vcpu, msr_kind),
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0xc0010007 => Self::shadow_write(vcpu, msr_kind),
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0xc0010117 => Self::shadow_write(vcpu, msr_kind),
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_ => {
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panic!("Unhandled WRMSR: {:#x}", msr_kind);
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@ -369,6 +369,7 @@ impl VCpu {
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.unwrap();
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self.guest_msr.set(0x1b, 0).unwrap();
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self.guest_msr.set(0xc0010007, 0).unwrap();
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self.guest_msr.set(0xc0010117, 0).unwrap();
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vmwrite(
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vmcs::control::VMEXIT_MSR_LOAD_ADDR_FULL,
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@ -1017,7 +1018,7 @@ impl VCpu {
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if let Err(e) = self.ept.map_4k(gpa, hpa, frame_allocator) {
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panic!("Failed to map page at GPA {:#x}: {}", gpa, e);
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}
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// Invalidate EPT after mapping new page
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// Note: INVEPT might not be available on all processors
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use crate::vmm::invlpg::invept_single_context;
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@ -1061,44 +1062,57 @@ impl VCpu {
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33 => {
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info!(" Reason: VM-entry failure due to invalid guest state");
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// Read VM-instruction error for more details
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let vm_instruction_error = unsafe {
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vmread(vmcs::ro::VM_INSTRUCTION_ERROR).unwrap_or(0)
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};
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let vm_instruction_error =
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unsafe { vmread(vmcs::ro::VM_INSTRUCTION_ERROR).unwrap_or(0) };
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info!(" VM-instruction error: {}", vm_instruction_error);
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// Dump guest state for debugging
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unsafe {
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info!(" Guest state dump:");
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info!(" CS: selector={:#x}, base={:#x}, limit={:#x}, rights={:#x}",
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vmread(vmcs::guest::CS_SELECTOR).unwrap(),
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vmread(vmcs::guest::CS_BASE).unwrap(),
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vmread(vmcs::guest::CS_LIMIT).unwrap(),
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vmread(vmcs::guest::CS_ACCESS_RIGHTS).unwrap());
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info!(" SS: selector={:#x}, base={:#x}, limit={:#x}, rights={:#x}",
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vmread(vmcs::guest::SS_SELECTOR).unwrap(),
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vmread(vmcs::guest::SS_BASE).unwrap(),
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vmread(vmcs::guest::SS_LIMIT).unwrap(),
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vmread(vmcs::guest::SS_ACCESS_RIGHTS).unwrap());
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info!(" DS: selector={:#x}, base={:#x}, limit={:#x}, rights={:#x}",
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vmread(vmcs::guest::DS_SELECTOR).unwrap(),
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vmread(vmcs::guest::DS_BASE).unwrap(),
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vmread(vmcs::guest::DS_LIMIT).unwrap(),
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vmread(vmcs::guest::DS_ACCESS_RIGHTS).unwrap());
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info!(" ES: selector={:#x}, base={:#x}, limit={:#x}, rights={:#x}",
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vmread(vmcs::guest::ES_SELECTOR).unwrap(),
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vmread(vmcs::guest::ES_BASE).unwrap(),
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vmread(vmcs::guest::ES_LIMIT).unwrap(),
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vmread(vmcs::guest::ES_ACCESS_RIGHTS).unwrap());
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info!(" RIP={:#x}, RSP={:#x}, RFLAGS={:#x}",
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vmread(vmcs::guest::RIP).unwrap(),
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vmread(vmcs::guest::RSP).unwrap(),
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vmread(vmcs::guest::RFLAGS).unwrap());
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info!(" CR0={:#x}, CR3={:#x}, CR4={:#x}",
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vmread(vmcs::guest::CR0).unwrap(),
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vmread(vmcs::guest::CR3).unwrap(),
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vmread(vmcs::guest::CR4).unwrap());
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info!(" EFER={:#x}",
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vmread(vmcs::guest::IA32_EFER_FULL).unwrap());
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info!(
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" CS: selector={:#x}, base={:#x}, limit={:#x}, rights={:#x}",
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vmread(vmcs::guest::CS_SELECTOR).unwrap(),
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vmread(vmcs::guest::CS_BASE).unwrap(),
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vmread(vmcs::guest::CS_LIMIT).unwrap(),
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vmread(vmcs::guest::CS_ACCESS_RIGHTS).unwrap()
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);
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info!(
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" SS: selector={:#x}, base={:#x}, limit={:#x}, rights={:#x}",
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vmread(vmcs::guest::SS_SELECTOR).unwrap(),
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vmread(vmcs::guest::SS_BASE).unwrap(),
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vmread(vmcs::guest::SS_LIMIT).unwrap(),
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vmread(vmcs::guest::SS_ACCESS_RIGHTS).unwrap()
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);
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info!(
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" DS: selector={:#x}, base={:#x}, limit={:#x}, rights={:#x}",
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vmread(vmcs::guest::DS_SELECTOR).unwrap(),
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vmread(vmcs::guest::DS_BASE).unwrap(),
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vmread(vmcs::guest::DS_LIMIT).unwrap(),
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vmread(vmcs::guest::DS_ACCESS_RIGHTS).unwrap()
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);
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info!(
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" ES: selector={:#x}, base={:#x}, limit={:#x}, rights={:#x}",
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vmread(vmcs::guest::ES_SELECTOR).unwrap(),
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vmread(vmcs::guest::ES_BASE).unwrap(),
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vmread(vmcs::guest::ES_LIMIT).unwrap(),
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vmread(vmcs::guest::ES_ACCESS_RIGHTS).unwrap()
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);
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info!(
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" RIP={:#x}, RSP={:#x}, RFLAGS={:#x}",
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vmread(vmcs::guest::RIP).unwrap(),
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vmread(vmcs::guest::RSP).unwrap(),
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vmread(vmcs::guest::RFLAGS).unwrap()
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);
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info!(
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" CR0={:#x}, CR3={:#x}, CR4={:#x}",
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vmread(vmcs::guest::CR0).unwrap(),
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vmread(vmcs::guest::CR3).unwrap(),
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vmread(vmcs::guest::CR4).unwrap()
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);
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info!(
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" EFER={:#x}",
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vmread(vmcs::guest::IA32_EFER_FULL).unwrap()
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);
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}
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panic!("VM-entry failure due to invalid guest state");
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}
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