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mii
2023-06-15 14:29:24 +09:00
commit d0c583fca6
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11
MDIO.gprj Normal file
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
<FileList>
<File path="src/Top.v" type="file.verilog" enable="1"/>
<File path="src/MDIO.cst" type="file.cst" enable="1"/>
</FileList>
</Project>

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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/MDIO.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/MDIO.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/MDIO.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/MDIO.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/MDIO.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/MDIO.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/MDIO.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/MDIO.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/MDIO_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/MDIO_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd0000000200000000000001000000044dfc0200000001fc000000380000044d0000008a01000018fa000000000200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000005600fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005200fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007100ffffff0000000300000494000000f2fc0100000001fc0000000000000494000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004700fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff0000038e0000044d00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000ffffffff0100000207ffffffff0000000000000000</Ui>
</UserConfig>

32
impl/gwsynthesis/MDIO.log Normal file
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GowinSynthesis start
Running parser ...
Analyzing Verilog file '/home/mii/work/MDIO/src/Top.v'
WARN (EX2810) : Extra semicolon in $unit (global) scope("/home/mii/work/MDIO/src/Top.v":203)
Compiling module 'Top'("/home/mii/work/MDIO/src/Top.v":1)
WARN (EX3780) : Using initial value of 'reg_mdc_cnt_max' since it is never assigned("/home/mii/work/MDIO/src/Top.v":13)
WARN (EX3780) : Using initial value of 'read_preamble' since it is never assigned("/home/mii/work/MDIO/src/Top.v":39)
WARN (EX3780) : Using initial value of 'write_preamble' since it is never assigned("/home/mii/work/MDIO/src/Top.v":40)
WARN (EX3780) : Using initial value of 'reg_phy_address' since it is never assigned("/home/mii/work/MDIO/src/Top.v":42)
WARN (EX3780) : Using initial value of 'reg_register_address' since it is never assigned("/home/mii/work/MDIO/src/Top.v":43)
WARN (EX3780) : Using initial value of 'write' since it is never assigned("/home/mii/work/MDIO/src/Top.v":46)
WARN (EX3791) : Expression size 6 truncated to fit in target size 5("/home/mii/work/MDIO/src/Top.v":16)
NOTE (EX0101) : Current top module is "Top"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "/home/mii/work/MDIO/impl/gwsynthesis/MDIO.vg" completed
[100%] Generate report file "/home/mii/work/MDIO/impl/gwsynthesis/MDIO_syn.rpt.html" completed
GowinSynthesis finish

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impl/gwsynthesis/MDIO.prj Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="/home/mii/work/MDIO/src/Top.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="dsp_balance" value="0"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="/home/mii/work/MDIO/impl/gwsynthesis/MDIO.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="1"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>

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impl/gwsynthesis/MDIO.vg Normal file
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//
//Written by GowinSynthesis
//Product Version "V1.9.8.11 Education"
//Thu Jun 15 14:25:43 2023
//Source file index table:
//file0 "\/home/mii/work/MDIO/src/Top.v"
`pragma protect begin_protected
`pragma protect version="2.2"
`pragma protect author="default"
`pragma protect author_info="default"
`pragma protect encrypt_agent="GOWIN"
`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.2"
`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
`pragma protect key_keyowner="GOWIN",key_keyname="GWK2022-10",key_method="rsa"
`pragma protect key_block
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`pragma protect encoding=(enctype="base64", line_length=76, bytes=24608)
`pragma protect data_keyowner="default-ip-vendor"
`pragma protect data_keyname="default-ip-key"
`pragma protect data_method="aes128-cbc"
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`pragma protect end_protected

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Hierarchy Module Resource</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
div#main_wrapper{ width: 100%; }
h1 {text-align: center; }
h1 {margin-top: 36px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { align = "center"; padding: 5px 2px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="content">
<h1>Hierarchy Module Resource</h1>
<table>
<tr>
<th class="label">MODULE NAME</th>
<th class="label">REG NUMBER</th>
<th class="label">ALU NUMBER</th>
<th class="label">LUT NUMBER</th>
<th class="label">DSP NUMBER</th>
<th class="label">BSRAM NUMBER</th>
<th class="label">SSRAM NUMBER</th>
</tr>
<tr>
<td class="label">Top (/home/mii/work/MDIO/src/Top.v)</td>
<td align = "center">47</td>
<td align = "center">4</td>
<td align = "center">122</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<Module name="Top" Register="47" Alu="4" Lut="122"/>

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Reading netlist file: "/home/mii/work/MDIO/impl/gwsynthesis/MDIO.vg"
Parsing netlist file "/home/mii/work/MDIO/impl/gwsynthesis/MDIO.vg" completed
Processing netlist completed
Reading constraint file: "/home/mii/work/MDIO/src/MDIO.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/home/mii/work/MDIO/impl/pnr/MDIO.power.html" completed
Generate file "/home/mii/work/MDIO/impl/pnr/MDIO.pin.html" completed
Generate file "/home/mii/work/MDIO/impl/pnr/MDIO.rpt.html" completed
Generate file "/home/mii/work/MDIO/impl/pnr/MDIO.rpt.txt" completed
Generate file "/home/mii/work/MDIO/impl/pnr/MDIO.tr.html" completed
Thu Jun 15 14:25:46 2023

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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Power Analysis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper { width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
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div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
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div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table th.label { min-width: 8%; width: 8%; }
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
</li>
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
<ul>
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
</ul>
</li>
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
<ul>
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="Message">Power Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Power Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>/home/mii/work/MDIO/impl/gwsynthesis/MDIO.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>/home/mii/work/MDIO/src/MDIO.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.11 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Thu Jun 15 14:25:46 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Power Summary</a></h1>
<h2><a name="Power_Info">Power Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Total Power (mW)</td>
<td>164.593</td>
</tr>
<tr>
<td class="label">Quiescent Power (mW)</td>
<td>160.886</td>
</tr>
<tr>
<td class="label">Dynamic Power (mW)</td>
<td>3.707</td>
</tr>
</table>
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Junction Temperature</td>
<td>30.270</td>
</tr>
<tr>
<td class="label">Theta JA</td>
<td>32.020</td>
</tr>
<tr>
<td class="label">Max Allowed Ambient Temperature</td>
<td>79.730</td>
</tr>
</table>
<h2><a name="Configure_Info">Configure Information:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Default IO Toggle Rate</td>
<td>0.125</td>
</tr>
<td class="label">Default Remain Toggle Rate</td>
<td>0.125</td>
</tr>
<tr>
<td class="label">Use Vectorless Estimation</td>
<td>false</td>
</tr>
<tr>
<td class="label">Filter Glitches</td>
<td>false</td>
</tr>
<tr>
<td class="label">Related Vcd File</td>
<td></td>
</tr>
<tr>
<td class="label">Related Saif File</td>
<td></td>
</tr>
<tr>
<td class="label">Use Custom Theta JA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Air Flow</td>
<td>LFM_0</td>
</tr>
<tr>
<td class="label">Heat Sink</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta SA</td>
<td>false</td>
</tr>
<tr>
<td class="label">Board Thermal Model</td>
<td>None</td>
</tr>
<tr>
<td class="label">Use Custom Theta JB</td>
<td>false</td>
</tr>
<tr>
<td class="label">Ambient Temperature</td>
<td>25.000
</tr>
</table>
<h2><a name="Supply_Summary">Supply Information:</a></h2>
<table class="summary_table">
<tr>
<th class="label">Voltage Source</th>
<th class="label">Voltage</th>
<th class="label">Dynamic Current(mA)</th>
<th class="label">Quiescent Current(mA)</th>
<th class="label">Power(mW)</th>
</tr>
<tr>
<td>VCC</td>
<td>1.000</td>
<td>0.902</td>
<td>101.983</td>
<td>102.885</td>
</tr>
<tr>
<td>VCCX</td>
<td>2.500</td>
<td>0.654</td>
<td>23.366</td>
<td>60.050</td>
</tr>
<tr>
<td>VCCIO18</td>
<td>1.800</td>
<td>0.650</td>
<td>0.272</td>
<td>1.658</td>
</tr>
</table>
<h1><a name="Detail">Power Details</a></h1>
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Block Type</th>
<th class="label">Total Power(mW)</th>
<th class="label">Static Power(mW)</th>
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
</tr>
<tr>
<td>Logic</td>
<td>0.203</td>
<td>NA</td>
<td>16.020</td>
</tr>
<tr>
<td>IO</td>
<td>4.911
<td>1.448
<td>23.438
</tr>
</table>
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Hierarchy Entity</th>
<th class="label">Total Power(mW)</th>
<th class="label">Block Dynamic Power(mW)</th>
</tr>
<tr>
<td>Top</td>
<td>0.203</td>
<td>0.203(0.000)</td>
</table>
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Domain</th>
<th class="label">Clock Frequency(Mhz)</th>
<th class="label">Total Dynamic Power(mW)</th>
</tr>
<tr>
<td>MDC_d</td>
<td>100.000</td>
<td>0.166</td>
</tr>
<tr>
<td>CLK</td>
<td>100.000</td>
<td>0.078</td>
</tr>
</table>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>

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//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
//All rights reserved.
1. PnR Messages
<Report Title>: PnR Report
<Design File>: /home/mii/work/MDIO/impl/gwsynthesis/MDIO.vg
<Physical Constraints File>: /home/mii/work/MDIO/src/MDIO.cst
<Timing Constraints File>: ---
<PnR Version>: V1.9.8.11 Education
<Part Number>: GW2A-LV18PG256C8/I7
<Device>: GW2A-18
<Device Version>: C
<Created Time>:Thu Jun 15 14:25:46 2023
2. PnR Details
Running placement:
Placement Phase 0: CPU time = 0h 0m 0.013s, Elapsed time = 0h 0m 0.013s
Placement Phase 1: CPU time = 0h 0m 0.341s, Elapsed time = 0h 0m 0.339s
Placement Phase 2: CPU time = 0h 0m 0.011s, Elapsed time = 0h 0m 0.011s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.19s, Elapsed time = 0h 0m 0.189s
Routing Phase 2: CPU time = 0h 0m 0.156s, Elapsed time = 0h 0m 0.153s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.346s, Elapsed time = 0h 0m 0.342s
Generate output files:
CPU time = 0h 0m 0.732s, Elapsed time = 0h 0m 0.727s
Total Time and Memory Usage: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 487MB
3. Resource Usage Summary
----------------------------------------------------------
Resources | Usage
----------------------------------------------------------
Logic | 125/20736 <1%
--LUT,ALU,ROM16 | 125(120 LUT, 5 ALU, 0 ROM16)
--SSRAM(RAM16) | 0
Register | 47/16173 <1%
--Logic Register as Latch | 0/15552 0%
--Logic Register as FF | 46/15552 <1%
--I/O Register as Latch | 0/621 0%
--I/O Register as FF | 1/621 <1%
CLS | 74/10368 <1%
I/O Port | 7
I/O Buf | 7
--Input Buf | 1
--Output Buf | 5
--Inout Buf | 1
IOLOGIC | 0%
BSRAM | 0%
DSP | 0%
PLL | 0/4 0%
DCS | 0/8 0%
DQCE | 0/24 0%
OSC | 0/1 0%
CLKDIV | 0/8 0%
DLLDLY | 0/8 0%
DQS | 0/9 0%
DHCEN | 0/16 0%
==========================================================
4. I/O Bank Usage Summary
-----------------------
I/O Bank | Usage
-----------------------
bank 0 | 3/29(10%)
bank 1 | 4/20(20%)
bank 2 | 0/20(0%)
bank 3 | 0/32(0%)
bank 4 | 0/36(0%)
bank 5 | 0/36(0%)
bank 6 | 0/18(0%)
bank 7 | 0/16(0%)
=======================
5. Global Clock Usage Summary
-------------------------------
Global Clock | Usage
-------------------------------
PRIMARY | 2/8(25%)
LW | 0/8(0%)
GCLK_PIN | 1/8(13%)
PLL | 0/4(0%)
CLKDIV | 0/8(0%)
DLLDLY | 0/8(0%)
===============================
6. Global Clock Signals
-------------------------------------------
Signal | Global Clock | Location
-------------------------------------------
CLK_d | PRIMARY | TR TL
MDC_d | PRIMARY | TR TL BR BL
===========================================
7. Pinout by Port Name
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CLK | | H11/0 | Y | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
MDC | | F14/0 | Y | out | IOT9[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
LED[0] | | N16/1 | Y | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
LED[1] | | N14/1 | Y | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
LED[2] | | L14/1 | Y | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
LED[3] | | L16/1 | Y | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
MDIO | | F16/0 | Y | io | IOT9[B] | LVCMOS18 | 8 | UP | NA | NONE | OFF | NA | NA | NA | 1.8
==================================================================================================================================================================================================================
8. All Package Pins
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
L15/0 | - | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D16/0 | - | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E14/0 | - | in | IOT4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
C16/0 | - | in | IOT5[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
F14/0 | MDC | out | IOT9[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
F16/0 | MDIO | io | IOT9[B] | LVCMOS18 | 8 | UP | NA | NONE | OFF | NA | NA | NA | 1.8
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
H11/0 | CLK | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L16/1 | LED[3] | out | IOT34[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
L14/1 | LED[2] | out | IOT34[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
N16/1 | LED[0] | out | IOT52[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
N14/1 | LED[1] | out | IOT52[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
B14/7 | - | in | IOL2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A15/7 | - | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C12/7 | - | in | IOL7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B12/7 | - | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | -
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | -
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
====================================================================================================================================================================================

857
impl/pnr/MDIO.timing_paths Normal file
View File

@ -0,0 +1,857 @@
=====
SETUP
4.849
5.898
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.864
n646_s42
3.038
3.491
n646_s27
3.935
4.397
n646_s44
4.570
5.023
n646_s43
5.436
5.898
state_0_s1
5.898
=====
SETUP
5.713
5.034
10.747
cnt_0_s1
0.782
1.014
n674_s23
1.700
2.153
n661_s24
2.606
3.059
n647_s23
3.654
4.025
n651_s22
4.464
5.034
cnt_27_s1
5.034
=====
SETUP
5.716
5.031
10.747
cnt_0_s1
0.782
1.014
n674_s23
1.700
2.153
n661_s24
2.606
3.059
n647_s23
3.654
4.025
n649_s22
4.461
5.031
cnt_29_s1
5.031
=====
SETUP
5.716
5.031
10.747
cnt_0_s1
0.782
1.014
n674_s23
1.700
2.153
n661_s24
2.606
3.059
n647_s23
3.654
4.025
n648_s22
4.461
5.031
cnt_30_s1
5.031
=====
SETUP
5.722
5.025
10.747
cnt_0_s1
0.782
1.014
n674_s23
1.700
2.153
n661_s24
2.606
3.059
n647_s23
3.654
4.025
n653_s22
4.455
5.025
cnt_25_s1
5.025
=====
SETUP
5.724
5.023
10.747
cnt_0_s1
0.782
1.014
n674_s23
1.700
2.153
n661_s24
2.606
3.059
n656_s24
3.746
4.295
n659_s22
4.474
5.023
cnt_19_s1
5.023
=====
SETUP
5.724
5.023
10.747
cnt_0_s1
0.782
1.014
n674_s23
1.700
2.153
n661_s24
2.606
3.059
n656_s24
3.746
4.295
n656_s22
4.474
5.023
cnt_22_s1
5.023
=====
SETUP
5.818
4.928
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_28_s1
4.928
=====
SETUP
5.818
4.928
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_29_s1
4.928
=====
SETUP
5.818
4.928
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_30_s1
4.928
=====
SETUP
5.818
4.928
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_31_s1
4.928
=====
SETUP
5.822
4.925
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_9_s1
4.925
=====
SETUP
5.822
4.925
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_10_s1
4.925
=====
SETUP
5.822
4.925
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_11_s1
4.925
=====
SETUP
5.822
4.925
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_19_s1
4.925
=====
SETUP
5.822
4.925
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_22_s1
4.925
=====
SETUP
5.826
4.921
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_7_s1
4.921
=====
SETUP
5.826
4.921
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_24_s1
4.921
=====
SETUP
5.826
4.921
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_25_s1
4.921
=====
SETUP
5.829
4.917
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_14_s1
4.917
=====
SETUP
5.829
4.917
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_15_s1
4.917
=====
SETUP
5.829
4.917
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_17_s1
4.917
=====
SETUP
5.829
4.917
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_18_s1
4.917
=====
SETUP
5.830
4.917
10.747
cnt_0_s1
0.782
1.014
n674_s23
1.700
2.153
n661_s24
2.606
3.059
n647_s23
3.654
4.025
n654_s22
4.455
4.917
cnt_24_s1
4.917
=====
SETUP
5.830
4.917
10.747
cnt_29_s1
0.782
1.014
n646_s41
1.178
1.733
n643_s24
2.402
2.855
n643_s23
3.287
3.857
cnt_31_s3
4.031
4.358
cnt_27_s1
4.917
=====
HOLD
-0.081
0.825
0.906
mdc_cnt_0_s0
0.825
=====
HOLD
-0.078
0.828
0.906
mdc_cnt_4_s0
0.828
=====
HOLD
-0.078
0.828
0.906
mdc_cnt_1_s0
0.828
=====
HOLD
-0.078
0.828
0.906
mdc_cnt_2_s0
0.828
=====
HOLD
-0.078
0.828
0.906
mdc_cnt_3_s0
0.828
=====
HOLD
0.228
1.134
0.906
state_2_s0
0.565
0.767
n1024_s22
0.902
1.134
mdio_out_en_s1
1.134
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
mdc_cnt_0_s0
0.860
1.062
n60_s2
1.064
1.296
mdc_cnt_0_s0
1.296
=====
HOLD
0.425
1.296
0.871
CLK_ibuf
0.000
0.675
mdc_cnt_3_s0
0.860
1.062
n57_s
1.064
1.296
mdc_cnt_3_s0
1.296
=====
HOLD
0.425
1.002
0.576
cnt_8_s1
0.565
0.767
n670_s22
0.770
1.002
cnt_8_s1
1.002
=====
HOLD
0.425
1.002
0.576
cnt_21_s1
0.565
0.767
n657_s22
0.770
1.002
cnt_21_s1
1.002
=====
HOLD
0.425
1.002
0.576
cnt_25_s1
0.565
0.767
n653_s22
0.770
1.002
cnt_25_s1
1.002
=====
HOLD
0.427
1.003
0.576
cnt_11_s1
0.565
0.767
n667_s23
0.771
1.003
cnt_11_s1
1.003
=====
HOLD
0.427
1.003
0.576
cnt_13_s1
0.565
0.767
n665_s23
0.771
1.003
cnt_13_s1
1.003
=====
HOLD
0.427
1.003
0.576
cnt_14_s1
0.565
0.767
n664_s23
0.771
1.003
cnt_14_s1
1.003
=====
HOLD
0.427
1.003
0.576
cnt_17_s1
0.565
0.767
n661_s22
0.771
1.003
cnt_17_s1
1.003
=====
HOLD
0.427
1.003
0.576
cnt_30_s1
0.565
0.767
n648_s22
0.771
1.003
cnt_30_s1
1.003
=====
HOLD
0.428
1.004
0.576
cnt_4_s1
0.565
0.767
n674_s22
0.772
1.004
cnt_4_s1
1.004
=====
HOLD
0.428
1.004
0.576
cnt_9_s1
0.565
0.767
n669_s22
0.772
1.004
cnt_9_s1
1.004
=====
HOLD
0.428
1.004
0.576
cnt_20_s1
0.565
0.767
n658_s23
0.772
1.004
cnt_20_s1
1.004
=====
HOLD
0.428
1.004
0.576
cnt_23_s1
0.565
0.767
n655_s23
0.772
1.004
cnt_23_s1
1.004
=====
HOLD
0.428
1.004
0.576
cnt_27_s1
0.565
0.767
n651_s22
0.772
1.004
cnt_27_s1
1.004
=====
HOLD
0.429
1.006
0.576
state_2_s0
0.565
0.767
n644_s22
0.774
1.006
state_2_s0
1.006
=====
HOLD
0.483
1.060
0.576
cnt_29_s1
0.565
0.767
n649_s22
0.770
1.060
cnt_29_s1
1.060
=====
HOLD
0.485
1.061
0.576
cnt_19_s1
0.565
0.767
n659_s22
0.771
1.061
cnt_19_s1
1.061
=====
HOLD
0.488
1.065
0.576
cnt_1_s1
0.565
0.767
n677_s22
0.775
1.065
cnt_1_s1
1.065

10
impl/pnr/MDIO.tr.html Normal file
View File

@ -0,0 +1,10 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Analysis Report</title>
</head>
<frameset cols="20%, 80%">
<frame src="MDIO_tr_cata.html" name="cataFrame" />
<frame src="MDIO_tr_content.html" name="mainFrame"/>
</frameset>
</html>

132
impl/pnr/MDIO_tr_cata.html Normal file
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@ -0,0 +1,132 @@
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>Timing Report Navigation</title>
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div.triangle { border-left: 5px solid #0084ff; }
div.triangle:hover { border-left-color: #000; }
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13429
impl/pnr/MDIO_tr_content.html Normal file
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File diff suppressed because it is too large Load Diff

12
impl/pnr/cmd.do Normal file
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@ -0,0 +1,12 @@
-d /home/mii/work/MDIO/impl/gwsynthesis/MDIO.vg
-p GW2A-18C-PBGA256-8
-pn GW2A-LV18PG256C8/I7
-cst /home/mii/work/MDIO/src/MDIO.cst
-cfg /home/mii/work/MDIO/impl/pnr/device.cfg
-bit
-tr
-ph
-timing
-cst_error
-correct_hold 1
-route_maxfan 23

20
impl/pnr/device.cfg Normal file
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@ -0,0 +1,20 @@
set JTAG regular_io = false
set SSPI regular_io = false
set MSPI regular_io = false
set READY regular_io = false
set DONE regular_io = false
set RECONFIG_N regular_io = false
set I2C regular_io = false
set CRC_check = true
set compress = false
set encryption = false
set security_bit_enable = true
set bsram_init_fuse_print = true
set background_programming = off
set secure_mode = false
set program_done_bypass = false
set wake_up = 0
set spi_flash_address = 0x00000000
set format = binary
set power_on_reset_monitor = true
set unused_pin = default

86
impl/project_process_config.json Normal file
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@ -0,0 +1,86 @@
{
"Allow_Duplicate_Modules" : false,
"Annotated_Properties_for_Analyst" : true,
"BACKGROUND_PROGRAMMING" : "off",
"COMPRESS" : false,
"CRC_CHECK" : true,
"Clock_Conversion" : true,
"Clock_Route_Order" : 0,
"Correct_Hold_Violation" : true,
"DONE" : false,
"DOWNLOAD_SPEED" : "default",
"Default_Enum_Encoding" : "default",
"Disable_Insert_Pad" : false,
"ENCRYPTION_KEY" : false,
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
"FORMAT" : "binary",
"FSM Compiler" : true,
"Fanout_Guide" : 10000,
"Frequency" : "Auto",
"Generate_Constraint_File_of_Ports" : false,
"Generate_IBIS_File" : false,
"Generate_Plain_Text_Timing_Report" : false,
"Generate_Post_PNR_Simulation_Model_File" : false,
"Generate_Post_Place_File" : false,
"Generate_SDF_File" : false,
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
"GwSyn_Loop_Limit" : 2000,
"HOTBOOT" : false,
"I2C" : false,
"I2C_SLAVE_ADDR" : "00",
"Implicit_Initial_Value_Support" : false,
"IncludePath" : [
],
"Incremental_Compile" : "",
"Initialize_Primitives" : false,
"JTAG" : false,
"MODE_IO" : false,
"MSPI" : false,
"Multiple_File_Compilation_Unit" : true,
"Number_of_Critical_Paths" : "",
"Number_of_Start/End_Points" : "",
"OUTPUT_BASE_NAME" : "MDIO",
"POWER_ON_RESET_MONITOR" : true,
"PRINT_BSRAM_VALUE" : true,
"PROGRAM_DONE_BYPASS" : false,
"Pipelining" : true,
"PlaceInRegToIob" : true,
"PlaceIoRegToIob" : true,
"PlaceOutRegToIob" : true,
"Place_Option" : "0",
"Process_Configuration_Verion" : "1.0",
"Promote_Physical_Constraint_Warning_to_Error" : true,
"Push_Tristates" : true,
"READY" : false,
"RECONFIG_N" : false,
"Ram_RW_Check" : true,
"Report_Auto-Placed_Io_Information" : false,
"Resolve_Mixed_Drivers" : false,
"Resource_Sharing" : true,
"Retiming" : false,
"Route_Maxfan" : "23",
"Route_Option" : "0",
"Run_Timing_Driven" : true,
"SECURE_MODE" : false,
"SECURITY_BIT" : true,
"SPI_FLASH_ADDR" : "00000000",
"SSPI" : false,
"Show_All_Warnings" : false,
"Synthesis On/Off Implemented as Translate On/Off" : false,
"Synthesize_tool" : "GowinSyn",
"TclPre" : "",
"TopModule" : "",
"USERCODE" : "default",
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
"Update_Compile_Point_Timing_Data" : false,
"Use_Clock_Period_for_Unconstrainted IO" : false,
"VCCAUX" : "3.3",
"VHDL_Standard" : "VHDL_Std_1993",
"Verilog_Standard" : "Vlg_Std_2001",
"WAKE_UP" : "0",
"Write_Vendor_Constraint_File" : true,
"dsp_balance" : false,
"show_all_warnings" : false,
"turn_off_bg" : false
}

10
impl/temp/rtl_parser.result Normal file
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@ -0,0 +1,10 @@
[
{
"InstFile" : "/home/mii/work/MDIO/src/Top.v",
"InstLine" : 1,
"InstName" : "Top",
"ModuleFile" : "/home/mii/work/MDIO/src/Top.v",
"ModuleLine" : 1,
"ModuleName" : "Top"
}
]

16
impl/temp/rtl_parser_arg.json Normal file
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@ -0,0 +1,16 @@
{
"Files" : [
{
"Path" : "/home/mii/work/MDIO/src/Top.v",
"Type" : "verilog"
}
],
"IncludePath" : [
],
"LoopLimit" : 2000,
"ResultFile" : "/home/mii/work/MDIO/impl/temp/rtl_parser.result",
"Top" : "",
"VerilogStd" : "verilog_2001",
"VhdlStd" : "vhdl_93"
}

23
src/MDIO.cst Normal file
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@ -0,0 +1,23 @@
//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//GOWIN Version: 1.9.8.11 Education
//Part Number: GW2A-LV18PG256C8/I7
//Device: GW2A-18
//Device Version: C
//Created Time: Wed 06 14 23:01:49 2023
IO_LOC "LED[3]" L16;
IO_PORT "LED[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "LED[2]" L14;
IO_PORT "LED[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "LED[1]" N14;
IO_PORT "LED[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "LED[0]" N16;
IO_PORT "LED[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "MDC" F14;
IO_PORT "MDC" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "MDIO" F16;
IO_PORT "MDIO" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "CLK" H11;
IO_PORT "CLK" PULL_MODE=UP BANK_VCCIO=1.8;

203
src/Top.v Normal file
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@ -0,0 +1,203 @@
module Top(
input CLK,
output MDC,
inout MDIO,
output [3:0] LED
);
reg [4:0] mdc_cnt = 0;
reg mdc_cnt_half = 0;
reg mdc_cnt_half_flag = 1;
wire mdclock;
wire [15:0] mdc_cnt_max;
reg [15:0] reg_mdc_cnt_max = 30;
always @(posedge CLK) begin
mdc_cnt <= mdclock ? 0 : mdc_cnt + 1;
end
localparam S_IDLE = 0;
localparam S_PREAMBLE = 1;
localparam S_READ = 2;
localparam S_WRITE = 3;
localparam S_READ_PREAMBLE = 4;
localparam S_WRITE_PREAMBLE = 5;
localparam S_PHY = 6;
localparam S_REG = 7;
localparam S_TURN = 8;
reg [3:0] state = S_IDLE;
reg [31:0] cnt = 0;
reg read_flag = 1;
reg mdio_write = 0;
reg mdio_out_en = 0;
assign MDIO = mdio_out_en ? mdio_write : 1'bz;
reg [3:0] read_preamble = 4'b0110;
reg [3:0] write_preamble = 4'b0101;
reg [4:0] reg_phy_address = 5'b00001;
reg [4:0] reg_register_address = 5'b00000;
reg [15:0] read = 16'b0;
reg [15:0] write = 16'b0000111111111010;
reg [15:0] led_read = 0;
// STATE MACHINE
always @(posedge mdclock) begin
case (state)
S_IDLE: begin
state <= S_PREAMBLE;
mdc_cnt_half <= 0;
end
S_PREAMBLE: begin
if (cnt == 31) begin
cnt = 0;
if (read_flag == 1'b1)
state <= S_READ_PREAMBLE;
else
state <= S_WRITE_PREAMBLE;
end else begin
state <= S_PREAMBLE;
cnt <= cnt + 1;
end
end
S_READ_PREAMBLE: begin
if (cnt == 3) begin
state <= S_PHY;
cnt <= 0;
end else begin
state <= S_READ_PREAMBLE;
cnt <= cnt + 1;
end
end
S_WRITE_PREAMBLE: begin
if (cnt == 3) begin
state <= S_PHY;
cnt <= 0;
end else begin
state <= S_WRITE_PREAMBLE;
cnt <= cnt + 1;
end
end
S_PHY: begin
if (cnt == 4) begin
state <= S_REG;
cnt <= 0;
end else begin
state <= S_PHY;
cnt <= cnt + 1;
end
end
S_REG: begin
if (cnt == 4) begin
state <= S_TURN;
cnt <= 0;
end else begin
state <= S_REG;
cnt <= cnt + 1;
end
end
S_TURN: begin
if (cnt == 1) begin
if (read_flag == 1)
state <= S_READ;
else
state <= S_WRITE;
end else begin
state <= S_TURN;
cnt <= cnt + 1;
end
end
S_READ: begin
if (cnt == 15) begin
state <= S_IDLE;
cnt <= 0;
end else begin
state <= S_READ;
cnt <= cnt + 1;
end
end
S_WRITE: begin
if (cnt == 15) begin
state <= S_IDLE;
cnt <= 0;
end else begin
state <= S_WRITE;
cnt <= cnt + 1;
end
end
endcase
end
// REG
always @(posedge CLK) begin
case (state)
S_IDLE: begin
mdio_out_en = 1;
mdio_write = 0;
led_read <= read;
end
S_PREAMBLE: begin
mdio_out_en = 1;
mdio_write = 1;
end
S_READ_PREAMBLE: begin
mdio_out_en = 1;
mdio_write = read_preamble[cnt];
end
S_WRITE_PREAMBLE: begin
mdio_out_en = 1;
mdio_write = write_preamble[cnt];
end
S_PHY: begin
mdio_out_en = 1;
mdio_write = reg_phy_address[4 - cnt];
end
S_REG: begin
mdio_out_en = 1;
mdio_write = reg_register_address[4 - cnt];
end
S_TURN: begin
mdio_out_en = ~read_flag;
mdio_write = 0;
end
S_READ: begin
mdio_out_en = 0;
read[15 - cnt] <= MDIO;
end
S_WRITE: begin
mdio_out_en = 1;
mdio_write <= write[15 - cnt];
read_flag <= 1;
end
endcase
end
assign mdc_cnt_max = reg_mdc_cnt_max;
assign mdclock = mdc_cnt == mdc_cnt_max;
assign MDC = mdclock;
assign LED = ~read[9:6];
endmodule;

473
src/a.out Executable file
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#! /usr/bin/vvp
:ivl_version "12.0 (stable)" "(v12_0-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/ivl/system.vpi";
:vpi_module "/usr/lib/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/ivl/va_math.vpi";
S_0x55a7b8470680 .scope module, "tb" "tb" 2 1;
.timescale 0 0;
P_0x55a7b846b8b0 .param/l "RATE" 0 2 3, +C4<00000000000000000000000000000001>;
v0x55a7b84a5cf0_0 .var "clk", 0 0;
S_0x55a7b8470860 .scope module, "top" "Top" 2 15, 3 1 0, S_0x55a7b8470680;
.timescale 0 0;
.port_info 0 /INPUT 1 "CLK";
.port_info 1 /OUTPUT 1 "MDC";
.port_info 2 /INOUT 1 "MDIO";
.port_info 3 /OUTPUT 4 "LED";
P_0x55a7b846bde0 .param/l "S_IDLE" 1 3 19, +C4<00000000000000000000000000000000>;
P_0x55a7b846be20 .param/l "S_PHY" 1 3 25, +C4<00000000000000000000000000000110>;
P_0x55a7b846be60 .param/l "S_PREAMBLE" 1 3 20, +C4<00000000000000000000000000000001>;
P_0x55a7b846bea0 .param/l "S_READ" 1 3 21, +C4<00000000000000000000000000000010>;
P_0x55a7b846bee0 .param/l "S_READ_PREAMBLE" 1 3 23, +C4<00000000000000000000000000000100>;
P_0x55a7b846bf20 .param/l "S_REG" 1 3 26, +C4<00000000000000000000000000000111>;
P_0x55a7b846bf60 .param/l "S_TURN" 1 3 27, +C4<00000000000000000000000000001000>;
P_0x55a7b846bfa0 .param/l "S_WRITE" 1 3 22, +C4<00000000000000000000000000000011>;
P_0x55a7b846bfe0 .param/l "S_WRITE_PREAMBLE" 1 3 24, +C4<00000000000000000000000000000101>;
L_0x55a7b84b6260 .functor BUFZ 1, L_0x55a7b84b6120, C4<0>, C4<0>, C4<0>;
L_0x55a7b84b63f0 .functor NOT 4, L_0x55a7b84b6320, C4<0000>, C4<0000>, C4<0000>;
v0x55a7b84631f0_0 .net "CLK", 0 0, v0x55a7b84a5cf0_0; 1 drivers
v0x55a7b845fa40_0 .net "LED", 3 0, L_0x55a7b84b63f0; 1 drivers
v0x55a7b84a4810_0 .net "MDC", 0 0, L_0x55a7b84b6260; 1 drivers
v0x55a7b84a48e0_0 .net "MDIO", 0 0, L_0x55a7b84a5db0; 1 drivers
o0x7ff6977b10d8 .functor BUFZ 1, C4<z>; HiZ drive
; Elide local net with no drivers, v0x55a7b84a49a0_0 name=_ivl_0
v0x55a7b84a4ad0_0 .net *"_ivl_15", 3 0, L_0x55a7b84b6320; 1 drivers
v0x55a7b84a4bb0_0 .net *"_ivl_6", 15 0, L_0x55a7b84a5fe0; 1 drivers
L_0x7ff697768018 .functor BUFT 1, C4<00000000000>, C4<0>, C4<0>, C4<0>;
v0x55a7b84a4c90_0 .net *"_ivl_9", 10 0, L_0x7ff697768018; 1 drivers
v0x55a7b84a4d70_0 .var "cnt", 31 0;
v0x55a7b84a4e50_0 .var "led_read", 15 0;
v0x55a7b84a4f30_0 .var "mdc_cnt", 4 0;
v0x55a7b84a5010_0 .var "mdc_cnt_half", 0 0;
v0x55a7b84a50d0_0 .var "mdc_cnt_half_flag", 0 0;
v0x55a7b84a5190_0 .net "mdc_cnt_max", 15 0, v0x55a7b84a5730_0; 1 drivers
v0x55a7b84a5270_0 .net "mdclock", 0 0, L_0x55a7b84b6120; 1 drivers
v0x55a7b84a5330_0 .var "mdio_out_en", 0 0;
v0x55a7b84a53f0_0 .var "mdio_write", 0 0;
v0x55a7b84a54b0_0 .var "read", 15 0;
v0x55a7b84a5590_0 .var "read_flag", 0 0;
v0x55a7b84a5650_0 .var "read_preamble", 3 0;
v0x55a7b84a5730_0 .var "reg_mdc_cnt_max", 15 0;
v0x55a7b84a5810_0 .var "reg_phy_address", 4 0;
v0x55a7b84a58f0_0 .var "reg_register_address", 4 0;
v0x55a7b84a59d0_0 .var "state", 3 0;
v0x55a7b84a5ab0_0 .var "write", 15 0;
v0x55a7b84a5b90_0 .var "write_preamble", 3 0;
E_0x55a7b84744f0 .event posedge, v0x55a7b84631f0_0;
E_0x55a7b84777f0 .event posedge, v0x55a7b84a5270_0;
L_0x55a7b84a5db0 .functor MUXZ 1, o0x7ff6977b10d8, v0x55a7b84a53f0_0, v0x55a7b84a5330_0, C4<>;
L_0x55a7b84a5fe0 .concat [ 5 11 0 0], v0x55a7b84a4f30_0, L_0x7ff697768018;
L_0x55a7b84b6120 .cmp/eq 16, L_0x55a7b84a5fe0, v0x55a7b84a5730_0;
L_0x55a7b84b6320 .part v0x55a7b84a4e50_0, 0, 4;
.scope S_0x55a7b8470860;
T_0 ;
%pushi/vec4 0, 0, 5;
%store/vec4 v0x55a7b84a4f30_0, 0, 5;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a7b84a5010_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a50d0_0, 0, 1;
%pushi/vec4 30, 0, 16;
%store/vec4 v0x55a7b84a5730_0, 0, 16;
%pushi/vec4 0, 0, 4;
%store/vec4 v0x55a7b84a59d0_0, 0, 4;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a7b84a4d70_0, 0, 32;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a5590_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a7b84a53f0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%pushi/vec4 6, 0, 4;
%store/vec4 v0x55a7b84a5650_0, 0, 4;
%pushi/vec4 5, 0, 4;
%store/vec4 v0x55a7b84a5b90_0, 0, 4;
%pushi/vec4 1, 0, 5;
%store/vec4 v0x55a7b84a5810_0, 0, 5;
%pushi/vec4 0, 0, 5;
%store/vec4 v0x55a7b84a58f0_0, 0, 5;
%pushi/vec4 0, 0, 16;
%store/vec4 v0x55a7b84a54b0_0, 0, 16;
%pushi/vec4 4090, 0, 16;
%store/vec4 v0x55a7b84a5ab0_0, 0, 16;
%pushi/vec4 0, 0, 16;
%store/vec4 v0x55a7b84a4e50_0, 0, 16;
%end;
.thread T_0;
.scope S_0x55a7b8470860;
T_1 ;
%wait E_0x55a7b84744f0;
%load/vec4 v0x55a7b84a5270_0;
%flag_set/vec4 8;
%jmp/0 T_1.0, 8;
%pushi/vec4 0, 0, 5;
%jmp/1 T_1.1, 8;
T_1.0 ; End of true expr.
%load/vec4 v0x55a7b84a4f30_0;
%addi 1, 0, 5;
%jmp/0 T_1.1, 8;
; End of false expr.
%blend;
T_1.1;
%assign/vec4 v0x55a7b84a4f30_0, 0;
%jmp T_1;
.thread T_1;
.scope S_0x55a7b8470860;
T_2 ;
%wait E_0x55a7b84777f0;
%load/vec4 v0x55a7b84a59d0_0;
%dup/vec4;
%pushi/vec4 0, 0, 4;
%cmp/u;
%jmp/1 T_2.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 4;
%cmp/u;
%jmp/1 T_2.1, 6;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_2.2, 6;
%dup/vec4;
%pushi/vec4 5, 0, 4;
%cmp/u;
%jmp/1 T_2.3, 6;
%dup/vec4;
%pushi/vec4 6, 0, 4;
%cmp/u;
%jmp/1 T_2.4, 6;
%dup/vec4;
%pushi/vec4 7, 0, 4;
%cmp/u;
%jmp/1 T_2.5, 6;
%dup/vec4;
%pushi/vec4 8, 0, 4;
%cmp/u;
%jmp/1 T_2.6, 6;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_2.7, 6;
%dup/vec4;
%pushi/vec4 3, 0, 4;
%cmp/u;
%jmp/1 T_2.8, 6;
%jmp T_2.9;
T_2.0 ;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x55a7b84a5010_0, 0;
%jmp T_2.9;
T_2.1 ;
%load/vec4 v0x55a7b84a4d70_0;
%cmpi/e 31, 0, 32;
%jmp/0xz T_2.10, 4;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x55a7b84a4d70_0, 0, 32;
%load/vec4 v0x55a7b84a5590_0;
%cmpi/e 1, 0, 1;
%jmp/0xz T_2.12, 4;
%pushi/vec4 4, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%jmp T_2.13;
T_2.12 ;
%pushi/vec4 5, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
T_2.13 ;
%jmp T_2.11;
T_2.10 ;
%pushi/vec4 1, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%load/vec4 v0x55a7b84a4d70_0;
%addi 1, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
T_2.11 ;
%jmp T_2.9;
T_2.2 ;
%load/vec4 v0x55a7b84a4d70_0;
%cmpi/e 3, 0, 32;
%jmp/0xz T_2.14, 4;
%pushi/vec4 6, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
%jmp T_2.15;
T_2.14 ;
%pushi/vec4 4, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%load/vec4 v0x55a7b84a4d70_0;
%addi 1, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
T_2.15 ;
%jmp T_2.9;
T_2.3 ;
%load/vec4 v0x55a7b84a4d70_0;
%cmpi/e 3, 0, 32;
%jmp/0xz T_2.16, 4;
%pushi/vec4 6, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
%jmp T_2.17;
T_2.16 ;
%pushi/vec4 5, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%load/vec4 v0x55a7b84a4d70_0;
%addi 1, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
T_2.17 ;
%jmp T_2.9;
T_2.4 ;
%load/vec4 v0x55a7b84a4d70_0;
%cmpi/e 4, 0, 32;
%jmp/0xz T_2.18, 4;
%pushi/vec4 7, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
%jmp T_2.19;
T_2.18 ;
%pushi/vec4 6, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%load/vec4 v0x55a7b84a4d70_0;
%addi 1, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
T_2.19 ;
%jmp T_2.9;
T_2.5 ;
%load/vec4 v0x55a7b84a4d70_0;
%cmpi/e 4, 0, 32;
%jmp/0xz T_2.20, 4;
%pushi/vec4 8, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
%jmp T_2.21;
T_2.20 ;
%pushi/vec4 7, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%load/vec4 v0x55a7b84a4d70_0;
%addi 1, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
T_2.21 ;
%jmp T_2.9;
T_2.6 ;
%load/vec4 v0x55a7b84a4d70_0;
%cmpi/e 1, 0, 32;
%jmp/0xz T_2.22, 4;
%load/vec4 v0x55a7b84a5590_0;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_2.24, 4;
%pushi/vec4 2, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%jmp T_2.25;
T_2.24 ;
%pushi/vec4 3, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
T_2.25 ;
%jmp T_2.23;
T_2.22 ;
%pushi/vec4 8, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%load/vec4 v0x55a7b84a4d70_0;
%addi 1, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
T_2.23 ;
%jmp T_2.9;
T_2.7 ;
%load/vec4 v0x55a7b84a4d70_0;
%cmpi/e 15, 0, 32;
%jmp/0xz T_2.26, 4;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
%jmp T_2.27;
T_2.26 ;
%pushi/vec4 2, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%load/vec4 v0x55a7b84a4d70_0;
%addi 1, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
T_2.27 ;
%jmp T_2.9;
T_2.8 ;
%load/vec4 v0x55a7b84a4d70_0;
%cmpi/e 15, 0, 32;
%jmp/0xz T_2.28, 4;
%pushi/vec4 0, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%pushi/vec4 0, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
%jmp T_2.29;
T_2.28 ;
%pushi/vec4 3, 0, 4;
%assign/vec4 v0x55a7b84a59d0_0, 0;
%load/vec4 v0x55a7b84a4d70_0;
%addi 1, 0, 32;
%assign/vec4 v0x55a7b84a4d70_0, 0;
T_2.29 ;
%jmp T_2.9;
T_2.9 ;
%pop/vec4 1;
%jmp T_2;
.thread T_2;
.scope S_0x55a7b8470860;
T_3 ;
%wait E_0x55a7b84744f0;
%load/vec4 v0x55a7b84a59d0_0;
%dup/vec4;
%pushi/vec4 0, 0, 4;
%cmp/u;
%jmp/1 T_3.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 4;
%cmp/u;
%jmp/1 T_3.1, 6;
%dup/vec4;
%pushi/vec4 4, 0, 4;
%cmp/u;
%jmp/1 T_3.2, 6;
%dup/vec4;
%pushi/vec4 5, 0, 4;
%cmp/u;
%jmp/1 T_3.3, 6;
%dup/vec4;
%pushi/vec4 6, 0, 4;
%cmp/u;
%jmp/1 T_3.4, 6;
%dup/vec4;
%pushi/vec4 7, 0, 4;
%cmp/u;
%jmp/1 T_3.5, 6;
%dup/vec4;
%pushi/vec4 8, 0, 4;
%cmp/u;
%jmp/1 T_3.6, 6;
%dup/vec4;
%pushi/vec4 2, 0, 4;
%cmp/u;
%jmp/1 T_3.7, 6;
%dup/vec4;
%pushi/vec4 3, 0, 4;
%cmp/u;
%jmp/1 T_3.8, 6;
%jmp T_3.9;
T_3.0 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a7b84a53f0_0, 0, 1;
%load/vec4 v0x55a7b84a54b0_0;
%assign/vec4 v0x55a7b84a4e50_0, 0;
%jmp T_3.9;
T_3.1 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a53f0_0, 0, 1;
%jmp T_3.9;
T_3.2 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%load/vec4 v0x55a7b84a5650_0;
%load/vec4 v0x55a7b84a4d70_0;
%part/u 1;
%store/vec4 v0x55a7b84a53f0_0, 0, 1;
%jmp T_3.9;
T_3.3 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%load/vec4 v0x55a7b84a5b90_0;
%load/vec4 v0x55a7b84a4d70_0;
%part/u 1;
%store/vec4 v0x55a7b84a53f0_0, 0, 1;
%jmp T_3.9;
T_3.4 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%load/vec4 v0x55a7b84a5810_0;
%pushi/vec4 4, 0, 32;
%load/vec4 v0x55a7b84a4d70_0;
%sub;
%part/u 1;
%store/vec4 v0x55a7b84a53f0_0, 0, 1;
%jmp T_3.9;
T_3.5 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%load/vec4 v0x55a7b84a58f0_0;
%pushi/vec4 4, 0, 32;
%load/vec4 v0x55a7b84a4d70_0;
%sub;
%part/u 1;
%store/vec4 v0x55a7b84a53f0_0, 0, 1;
%jmp T_3.9;
T_3.6 ;
%load/vec4 v0x55a7b84a5590_0;
%inv;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a7b84a53f0_0, 0, 1;
%jmp T_3.9;
T_3.7 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%load/vec4 v0x55a7b84a48e0_0;
%ix/load 5, 0, 0;
%pushi/vec4 15, 0, 32;
%load/vec4 v0x55a7b84a4d70_0;
%sub;
%ix/vec4 4;
%assign/vec4/off/d v0x55a7b84a54b0_0, 4, 5;
%jmp T_3.9;
T_3.8 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55a7b84a5330_0, 0, 1;
%load/vec4 v0x55a7b84a5ab0_0;
%pushi/vec4 15, 0, 32;
%load/vec4 v0x55a7b84a4d70_0;
%sub;
%part/u 1;
%assign/vec4 v0x55a7b84a53f0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x55a7b84a5590_0, 0;
%jmp T_3.9;
T_3.9 ;
%pop/vec4 1;
%jmp T_3;
.thread T_3;
.scope S_0x55a7b8470680;
T_4 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55a7b84a5cf0_0, 0, 1;
%end;
.thread T_4;
.scope S_0x55a7b8470680;
T_5 ;
%vpi_call 2 6 "$dumpfile", "tb.vcd" {0 0 0};
%vpi_call 2 7 "$dumpvars", 32'sb00000000000000000000000000000011, S_0x55a7b8470680 {0 0 0};
%delay 270000, 0;
%vpi_call 2 9 "$finish" {0 0 0};
%end;
.thread T_5;
.scope S_0x55a7b8470680;
T_6 ;
%delay 1, 0;
%load/vec4 v0x55a7b84a5cf0_0;
%nor/r;
%store/vec4 v0x55a7b84a5cf0_0, 0, 1;
%jmp T_6;
.thread T_6;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb.v";
"Top.v";

82
src/nohup.out Normal file
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@ -0,0 +1,82 @@
(process:11056): Gtk-WARNING **: 22:48:31.855: Locale not supported by C library.
Using the fallback 'C' locale.
GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
[0] start time.
[270000] end time.
WM Destroy
(process:5898): Gtk-WARNING **: 12:05:13.803: Locale not supported by C library.
Using the fallback 'C' locale.
GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
[0] start time.
[270000] end time.
WM Destroy
(process:6131): Gtk-WARNING **: 12:06:52.470: Locale not supported by C library.
Using the fallback 'C' locale.
GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
[0] start time.
[270000] end time.
WM Destroy
(process:6375): Gtk-WARNING **: 12:10:49.216: Locale not supported by C library.
Using the fallback 'C' locale.
GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
[0] start time.
[270000] end time.
WM Destroy
(process:6576): Gtk-WARNING **: 12:11:42.201: Locale not supported by C library.
Using the fallback 'C' locale.
GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
[0] start time.
[270000] end time.
WM Destroy
(process:6779): Gtk-WARNING **: 12:12:46.998: Locale not supported by C library.
Using the fallback 'C' locale.
GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
[0] start time.
[270000] end time.
WM Destroy
(process:7037): Gtk-WARNING **: 12:16:17.036: Locale not supported by C library.
Using the fallback 'C' locale.
GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
[0] start time.
[270000] end time.
WM Destroy
(process:7226): Gtk-WARNING **: 12:18:07.087: Locale not supported by C library.
Using the fallback 'C' locale.
GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
[0] start time.
[270000] end time.
WM Destroy
(process:7489): Gtk-WARNING **: 12:22:07.139: Locale not supported by C library.
Using the fallback 'C' locale.
GTKWave Analyzer v3.3.115 (w)1999-2023 BSI
[0] start time.
[270000] end time.
[0] start time.
[270000] end time.

5
src/simulate.sh Executable file
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@ -0,0 +1,5 @@
#!/bin/sh
iverilog tb.v Top.v
vvp a.out
nohup gtkwave tb.vcd

19
src/tb.v Normal file
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@ -0,0 +1,19 @@
module tb;
parameter RATE = 1;
initial begin
$dumpfile("tb.vcd");
$dumpvars(3, tb);
# (270000) $finish;
end
reg clk = 0;
always #(RATE) clk = !clk;
Top top(
.CLK(clk)
);
endmodule

698304
src/tb.vcd Normal file
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