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14182 lines
228 KiB
HTML
14182 lines
228 KiB
HTML
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html>
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<head>
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<title>Timing Analysis Report</title>
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<style type="text/css">
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body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
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div#content { width: 100%; margin: }
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hr { margin-top: 30px; margin-bottom: 30px; }
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h1, h3 { text-align: center; }
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h1 {margin-top: 50px; }
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table, th, td {white-space:pre; border: 1px solid #aaa; }
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table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
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th, td { padding: 5px 5px 5px 5px; }
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th { color: #fff; font-weight: bold; background-color: #0084ff; }
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table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
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table.detail_table th.label { min-width: 8%; width: 8%; }
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</style>
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</head>
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<body>
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<div id="content">
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<h1><a name="Message">Timing Messages</a></h1>
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<table class="summary_table">
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<tr>
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<td class="label">Report Title</td>
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<td>Timing Analysis Report</td>
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</tr>
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<tr>
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<td class="label">Design File</td>
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<td>C:\Users\kuroc\Downloads\cpu\impl\gwsynthesis\cpu.vg</td>
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</tr>
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<tr>
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<td class="label">Physical Constraints File</td>
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<td>C:\Users\kuroc\Downloads\cpu\src\cpu.cst</td>
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</tr>
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<tr>
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<td class="label">Timing Constraint File</td>
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<td>---</td>
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</tr>
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<tr>
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<td class="label">Version</td>
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<td>V1.9.8.09 Education</td>
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</tr>
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<tr>
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<td class="label">Part Number</td>
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<td>GW2A-LV18PG256C8/I7</td>
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</tr>
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<tr>
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<td class="label">Device</td>
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<td>GW2A-18C</td>
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Sun May 28 23:10:01 2023
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</td>
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</tr>
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<tr>
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<td class="label">Legal Announcement</td>
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<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
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</tr>
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</table>
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<h1><a name="Summary">Timing Summaries</a></h1>
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<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
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<table class="summary_table">
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<tr>
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<td class="label">Setup Delay Model</td>
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<td>Slow 0.95V 85C C8/I7</td>
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</tr>
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<tr>
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<td class="label">Hold Delay Model</td>
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<td>Fast 1.05V 0C C8/I7</td>
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</tr>
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<tr>
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<td class="label">Numbers of Paths Analyzed</td>
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<td>82</td>
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</tr>
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<tr>
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<td class="label">Numbers of Endpoints Analyzed</td>
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<td>83</td>
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</tr>
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<tr>
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<td class="label">Numbers of Falling Endpoints</td>
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<td>0</td>
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</tr>
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<tr>
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<td class="label">Numbers of Setup Violated Endpoints</td>
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<td>0</td>
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</tr>
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<tr>
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<td class="label">Numbers of Hold Violated Endpoints</td>
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<td>0</td>
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</tr>
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</table>
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<h2><a name="Clock_Report">Clock Summary:</a></h2>
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<table class="detail_table">
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<tr>
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<th class="label">Clock Name</th>
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<th class="label">Type</th>
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<th class="label">Period</th>
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<th class="label">Frequency(MHz)</th>
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<th class="label">Rise</th>
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<th class="label">Fall</th>
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<th class="label">Source</th>
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<th class="label">Master</th>
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<th class="label">Objects</th>
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</tr>
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<tr>
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<td>clock</td>
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<td>Base</td>
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<td>10.000</td>
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<td>100.000
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<td>0.000</td>
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<td>5.000</td>
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<td></td>
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<td></td>
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<td>clock_ibuf/I </td>
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</tr>
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</table>
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<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
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<table>
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<tr>
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<th>NO.</th>
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<th>Clock Name</th>
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<th>Constraint</th>
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<th>Actual Fmax</th>
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<th>Logic Level</th>
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<th>Entity</th>
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</tr>
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<tr>
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<td>1</td>
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<td>clock</td>
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<td>100.000(MHz)</td>
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<td>246.713(MHz)</td>
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<td>5</td>
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<td>TOP</td>
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</tr>
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</table>
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<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
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<table class="detail_table">
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<tr>
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<th class="label">Clock Name</th>
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<th class="label">Analysis Type</th>
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<th class="label">Endpoints TNS</th>
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<th class="label">Number of Endpoints</th>
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</tr>
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<tr>
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<td>clock</td>
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<td>Setup</td>
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<td>0.000</td>
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<td>0</td>
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</tr>
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<tr>
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<td>clock</td>
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<td>Hold</td>
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<td>0.000</td>
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<td>0</td>
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</tr>
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</table>
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<h1><a name="Detail">Timing Details</a></h1>
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<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
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<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
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<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
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<table class="detail_table">
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<tr>
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<th class="label">Path Number</th>
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<th class="label">Path Slack</th>
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<th class="label">From Node</th>
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<th class="label">To Node</th>
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<th class="label">From Clock</th>
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<th class="label">To Clock</th>
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<th class="label">Relation</th>
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<th class="label">Clock Skew</th>
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<th class="label">Data Delay</th>
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</tr>
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<tr>
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<td>1</td>
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<td>5.947</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/send_count_2_s2/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>4.018</td>
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</tr>
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<tr>
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<td>2</td>
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<td>6.006</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/state_2_s3/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.959</td>
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</tr>
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<tr>
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<td>3</td>
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<td>6.006</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/state_0_s1/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.959</td>
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</tr>
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<tr>
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<td>4</td>
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<td>6.130</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/send_count_1_s2/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.835</td>
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</tr>
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<tr>
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<td>5</td>
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<td>6.130</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/send_count_3_s2/CE</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.835</td>
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</tr>
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<tr>
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<td>6</td>
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<td>6.229</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/state_1_s3/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.736</td>
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</tr>
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<tr>
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<td>7</td>
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<td>6.276</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/send_count_0_s4/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.689</td>
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</tr>
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<tr>
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<td>8</td>
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<td>6.276</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/send_count_1_s2/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.689</td>
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</tr>
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<tr>
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<td>9</td>
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<td>6.280</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/send_count_3_s2/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.685</td>
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</tr>
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<tr>
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<td>10</td>
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<td>6.448</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/send_count_2_s2/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.517</td>
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</tr>
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<tr>
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<td>11</td>
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<td>6.472</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/tx_reg_s2/D</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.493</td>
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</tr>
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<tr>
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<td>12</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_1_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>13</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_2_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>14</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_3_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>15</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_4_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>16</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_5_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>17</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_6_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>18</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_7_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>19</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_8_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>20</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_9_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>21</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_10_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>22</td>
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<td>6.475</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_11_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.490</td>
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</tr>
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<tr>
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<td>23</td>
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<td>6.512</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_24_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.453</td>
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</tr>
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<tr>
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<td>24</td>
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<td>6.512</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_25_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.453</td>
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</tr>
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<tr>
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<td>25</td>
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<td>6.512</td>
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<td>uart0/clock_count_31_s0/Q</td>
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<td>uart0/clock_count_26_s0/RESET</td>
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<td>clock:[R]</td>
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<td>clock:[R]</td>
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<td>10.000</td>
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<td>0.000</td>
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<td>3.453</td>
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</tr>
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</table>
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<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
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<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
|
<table class="detail_table">
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<tr>
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<th class="label">Path Number</th>
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<th class="label">Path Slack</th>
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<th class="label">From Node</th>
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<th class="label">To Node</th>
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<th class="label">From Clock</th>
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<th class="label">To Clock</th>
|
|
<th class="label">Relation</th>
|
|
<th class="label">Clock Skew</th>
|
|
<th class="label">Data Delay</th>
|
|
</tr>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>0.425</td>
|
|
<td>uart0/led_flag_s1/Q</td>
|
|
<td>uart0/led_flag_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_2_s0/Q</td>
|
|
<td>uart0/clock_count_2_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_6_s0/Q</td>
|
|
<td>uart0/clock_count_6_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_8_s0/Q</td>
|
|
<td>uart0/clock_count_8_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_12_s0/Q</td>
|
|
<td>uart0/clock_count_12_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_14_s0/Q</td>
|
|
<td>uart0/clock_count_14_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_18_s0/Q</td>
|
|
<td>uart0/clock_count_18_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_20_s0/Q</td>
|
|
<td>uart0/clock_count_20_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_24_s0/Q</td>
|
|
<td>uart0/clock_count_24_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_26_s0/Q</td>
|
|
<td>uart0/clock_count_26_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>11</td>
|
|
<td>0.425</td>
|
|
<td>uart0/clock_count_30_s0/Q</td>
|
|
<td>uart0/clock_count_30_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.436</td>
|
|
</tr>
|
|
<tr>
|
|
<td>12</td>
|
|
<td>0.427</td>
|
|
<td>uart0/clock_count_0_s0/Q</td>
|
|
<td>uart0/clock_count_0_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.438</td>
|
|
</tr>
|
|
<tr>
|
|
<td>13</td>
|
|
<td>0.428</td>
|
|
<td>uart0/state_2_s3/Q</td>
|
|
<td>uart0/state_2_s3/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.439</td>
|
|
</tr>
|
|
<tr>
|
|
<td>14</td>
|
|
<td>0.428</td>
|
|
<td>uart0/state_0_s1/Q</td>
|
|
<td>uart0/state_0_s1/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.439</td>
|
|
</tr>
|
|
<tr>
|
|
<td>15</td>
|
|
<td>0.483</td>
|
|
<td>uart0/send_count_1_s2/Q</td>
|
|
<td>uart0/send_count_1_s2/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.494</td>
|
|
</tr>
|
|
<tr>
|
|
<td>16</td>
|
|
<td>0.537</td>
|
|
<td>uart0/send_count_3_s2/Q</td>
|
|
<td>uart0/send_count_3_s2/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.548</td>
|
|
</tr>
|
|
<tr>
|
|
<td>17</td>
|
|
<td>0.539</td>
|
|
<td>uart0/send_count_2_s2/Q</td>
|
|
<td>uart0/send_count_2_s2/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.550</td>
|
|
</tr>
|
|
<tr>
|
|
<td>18</td>
|
|
<td>0.542</td>
|
|
<td>uart0/clock_count_3_s0/Q</td>
|
|
<td>uart0/clock_count_3_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.553</td>
|
|
</tr>
|
|
<tr>
|
|
<td>19</td>
|
|
<td>0.542</td>
|
|
<td>uart0/clock_count_4_s0/Q</td>
|
|
<td>uart0/clock_count_4_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.553</td>
|
|
</tr>
|
|
<tr>
|
|
<td>20</td>
|
|
<td>0.542</td>
|
|
<td>uart0/clock_count_11_s0/Q</td>
|
|
<td>uart0/clock_count_11_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.553</td>
|
|
</tr>
|
|
<tr>
|
|
<td>21</td>
|
|
<td>0.542</td>
|
|
<td>uart0/clock_count_23_s0/Q</td>
|
|
<td>uart0/clock_count_23_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.553</td>
|
|
</tr>
|
|
<tr>
|
|
<td>22</td>
|
|
<td>0.542</td>
|
|
<td>uart0/clock_count_27_s0/Q</td>
|
|
<td>uart0/clock_count_27_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.553</td>
|
|
</tr>
|
|
<tr>
|
|
<td>23</td>
|
|
<td>0.542</td>
|
|
<td>uart0/clock_count_28_s0/Q</td>
|
|
<td>uart0/clock_count_28_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.553</td>
|
|
</tr>
|
|
<tr>
|
|
<td>24</td>
|
|
<td>0.542</td>
|
|
<td>uart0/clock_count_29_s0/Q</td>
|
|
<td>uart0/clock_count_29_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.553</td>
|
|
</tr>
|
|
<tr>
|
|
<td>25</td>
|
|
<td>0.544</td>
|
|
<td>uart0/clock_count_31_s0/Q</td>
|
|
<td>uart0/clock_count_31_s0/D</td>
|
|
<td>clock:[R]</td>
|
|
<td>clock:[R]</td>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>0.555</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>Nothing to report!</h4>
|
|
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
|
|
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>Nothing to report!</h4>
|
|
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">Number</th>
|
|
<th class="label">Slack</th>
|
|
<th class="label">Actual Width</th>
|
|
<th class="label">Required Width</th>
|
|
<th class="label">Type</th>
|
|
<th class="label">Clock</th>
|
|
<th class="label">Objects</th>
|
|
</tr>
|
|
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
<tr>
|
|
<td>1</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_30_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_28_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_16_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_0_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>6</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_1_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>7</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_17_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_3_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10</td>
|
|
<td>3.911</td>
|
|
<td>4.911</td>
|
|
<td>1.000</td>
|
|
<td>Low Pulse Width</td>
|
|
<td>clock</td>
|
|
<td>uart0/clock_count_25_s0</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
|
|
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
|
<h3>Path1</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>5.947</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.944</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_2_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.066</td>
|
|
<td>0.211</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C41[1][B]</td>
|
|
<td>uart0/send_count_3_s10/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.615</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>3</td>
|
|
<td>R14C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.944</td>
|
|
<td>0.329</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_2_s2/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>uart0/send_count_2_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>uart0/send_count_2_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.917, 47.707%; route: 1.869, 46.520%; tC2Q: 0.232, 5.774%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path2</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.006</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.884</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/state_2_s3</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.314</td>
|
|
<td>0.459</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td>uart0/n191_s14/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.884</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n191_s14/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.884</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/state_2_s3/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td>uart0/state_2_s3/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td>uart0/state_2_s3</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.938, 48.957%; route: 1.789, 45.182%; tC2Q: 0.232, 5.861%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path3</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.006</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.884</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/state_0_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.314</td>
|
|
<td>0.459</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td>uart0/n194_s10/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.884</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n194_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.884</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/state_0_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td>uart0/state_0_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td>uart0/state_0_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.938, 48.957%; route: 1.789, 45.182%; tC2Q: 0.232, 5.861%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path4</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.130</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.760</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_1_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.066</td>
|
|
<td>0.211</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C41[1][B]</td>
|
|
<td>uart0/send_count_3_s10/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.615</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>3</td>
|
|
<td>R14C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.760</td>
|
|
<td>0.146</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_1_s2/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td>uart0/send_count_1_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td>uart0/send_count_1_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.917, 49.992%; route: 1.686, 43.958%; tC2Q: 0.232, 6.050%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path5</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.130</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.760</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_3_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.066</td>
|
|
<td>0.211</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C41[1][B]</td>
|
|
<td>uart0/send_count_3_s10/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.615</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>3</td>
|
|
<td>R14C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.760</td>
|
|
<td>0.146</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_3_s2/CE</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td>uart0/send_count_3_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td>uart0/send_count_3_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.917, 49.992%; route: 1.686, 43.958%; tC2Q: 0.232, 6.050%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path6</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.229</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.662</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/state_1_s3</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.291</td>
|
|
<td>0.435</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][B]</td>
|
|
<td>uart0/n192_s14/I3</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.662</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n192_s14/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.662</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][B]</td>
|
|
<td style=" font-weight:bold;">uart0/state_1_s3/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][B]</td>
|
|
<td>uart0/state_1_s3/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C41[1][B]</td>
|
|
<td>uart0/state_1_s3</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.739, 46.551%; route: 1.765, 47.239%; tC2Q: 0.232, 6.210%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path7</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.276</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.615</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_0_s4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.066</td>
|
|
<td>0.211</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C41[1][A]</td>
|
|
<td>uart0/n210_s10/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.615</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R14C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n210_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.615</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_0_s4/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[1][A]</td>
|
|
<td>uart0/send_count_0_s4/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C41[1][A]</td>
|
|
<td>uart0/send_count_0_s4</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.917, 51.964%; route: 1.540, 41.747%; tC2Q: 0.232, 6.289%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path8</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.276</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.615</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_1_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.066</td>
|
|
<td>0.211</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td>uart0/n208_s8/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.615</td>
|
|
<td>0.549</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n208_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.615</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_1_s2/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td>uart0/send_count_1_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td>uart0/send_count_1_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.917, 51.964%; route: 1.540, 41.747%; tC2Q: 0.232, 6.289%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path9</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.280</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.611</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_3_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.041</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td>uart0/n204_s8/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.611</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n204_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.611</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_3_s2/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td>uart0/send_count_3_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td>uart0/send_count_3_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.947, 52.838%; route: 1.506, 40.866%; tC2Q: 0.232, 6.296%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path10</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.448</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.443</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_2_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.873</td>
|
|
<td>0.018</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>uart0/n206_s8/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.443</td>
|
|
<td>0.570</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n206_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.443</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_2_s2/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>uart0/send_count_2_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>uart0/send_count_2_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.938, 55.105%; route: 1.347, 38.298%; tC2Q: 0.232, 6.597%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path11</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.472</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.419</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/tx_reg_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td>uart0/send_count_3_s5/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.855</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>9</td>
|
|
<td>R14C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/send_count_3_s5/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.048</td>
|
|
<td>0.193</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C42[1][B]</td>
|
|
<td>uart0/n185_s11/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.419</td>
|
|
<td>0.371</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n185_s11/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.419</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C42[1][B]</td>
|
|
<td style=" font-weight:bold;">uart0/tx_reg_s2/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C42[1][B]</td>
|
|
<td>uart0/tx_reg_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C42[1][B]</td>
|
|
<td>uart0/tx_reg_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>5</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.739, 49.785%; route: 1.522, 43.573%; tC2Q: 0.232, 6.642%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path12</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_1_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_1_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[0][B]</td>
|
|
<td>uart0/clock_count_1_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C38[0][B]</td>
|
|
<td>uart0/clock_count_1_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path13</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_2_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td>uart0/clock_count_2_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path14</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_3_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_3_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td>uart0/clock_count_3_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td>uart0/clock_count_3_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path15</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_4_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td>uart0/clock_count_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td>uart0/clock_count_4_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path16</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_5_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_5_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][B]</td>
|
|
<td>uart0/clock_count_5_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C38[2][B]</td>
|
|
<td>uart0/clock_count_5_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path17</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_6_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>uart0/clock_count_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>uart0/clock_count_6_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path18</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_7_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_7_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td>uart0/clock_count_7_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[0][B]</td>
|
|
<td>uart0/clock_count_7_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path19</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_8_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td>uart0/clock_count_8_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td>uart0/clock_count_8_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path20</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_9_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[1][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_9_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[1][B]</td>
|
|
<td>uart0/clock_count_9_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[1][B]</td>
|
|
<td>uart0/clock_count_9_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path21</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_10_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_10_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[2][A]</td>
|
|
<td>uart0/clock_count_10_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[2][A]</td>
|
|
<td>uart0/clock_count_10_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path22</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.475</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_11_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.415</td>
|
|
<td>0.551</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_11_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td>uart0/clock_count_11_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td>uart0/clock_count_11_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.461%; route: 1.881, 53.890%; tC2Q: 0.232, 6.648%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path23</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.512</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.379</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.379</td>
|
|
<td>0.515</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_24_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.877%; route: 1.844, 53.405%; tC2Q: 0.232, 6.719%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path24</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.512</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.379</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_25_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.379</td>
|
|
<td>0.515</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_25_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][B]</td>
|
|
<td>uart0/clock_count_25_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[0][B]</td>
|
|
<td>uart0/clock_count_25_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.877%; route: 1.844, 53.405%; tC2Q: 0.232, 6.719%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path25</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>6.512</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>4.379</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>10.891</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_26_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.683</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.158</td>
|
|
<td>0.232</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.822</td>
|
|
<td>0.664</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td>uart0/n12_s6/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.275</td>
|
|
<td>0.453</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s6/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>2.765</td>
|
|
<td>0.490</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td>uart0/n12_s1/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.227</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>FR</td>
|
|
<td>2</td>
|
|
<td>R13C42[3][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s1/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.402</td>
|
|
<td>0.176</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td>uart0/n12_s0/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>3.864</td>
|
|
<td>0.462</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>33</td>
|
|
<td>R14C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n12_s0/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4.379</td>
|
|
<td>0.515</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_26_s0/RESET</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>10.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.682</td>
|
|
<td>0.683</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.926</td>
|
|
<td>0.243</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td>uart0/clock_count_26_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.891</td>
|
|
<td>-0.035</td>
|
|
<td>tSu</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td>uart0/clock_count_26_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Setup Relationship </td>
|
|
<td>10.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>4</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 1.377, 39.877%; route: 1.844, 53.405%; tC2Q: 0.232, 6.719%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.683, 73.717%; route: 0.243, 26.283%</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
|
<h3>Path1</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/led_flag_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/led_flag_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C43[0][A]</td>
|
|
<td>uart0/led_flag_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R14C43[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/led_flag_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C43[0][A]</td>
|
|
<td>uart0/n79_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R14C43[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n79_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C43[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/led_flag_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C43[0][A]</td>
|
|
<td>uart0/led_flag_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C43[0][A]</td>
|
|
<td>uart0/led_flag_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path2</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td>uart0/clock_count_2_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_2_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td>uart0/n44_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n44_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_2_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td>uart0/clock_count_2_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C38[1][A]</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path3</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_6_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>uart0/clock_count_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>3</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_6_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>uart0/n40_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n40_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_6_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>uart0/clock_count_6_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[0][A]</td>
|
|
<td>uart0/clock_count_6_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path4</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_8_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td>uart0/clock_count_8_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_8_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td>uart0/n38_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n38_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_8_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td>uart0/clock_count_8_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[1][A]</td>
|
|
<td>uart0/clock_count_8_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path5</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_12_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_12_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td>uart0/clock_count_12_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_12_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td>uart0/n34_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n34_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_12_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td>uart0/clock_count_12_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C40[0][A]</td>
|
|
<td>uart0/clock_count_12_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path6</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_14_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_14_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C40[1][A]</td>
|
|
<td>uart0/clock_count_14_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C40[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_14_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C40[1][A]</td>
|
|
<td>uart0/n32_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C40[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n32_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C40[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_14_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C40[1][A]</td>
|
|
<td>uart0/clock_count_14_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C40[1][A]</td>
|
|
<td>uart0/clock_count_14_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path7</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_18_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_18_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C41[0][A]</td>
|
|
<td>uart0/clock_count_18_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C41[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_18_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C41[0][A]</td>
|
|
<td>uart0/n28_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n28_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_18_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C41[0][A]</td>
|
|
<td>uart0/clock_count_18_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C41[0][A]</td>
|
|
<td>uart0/clock_count_18_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path8</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_20_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_20_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C41[1][A]</td>
|
|
<td>uart0/clock_count_20_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C41[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_20_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C41[1][A]</td>
|
|
<td>uart0/n26_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n26_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_20_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C41[1][A]</td>
|
|
<td>uart0/clock_count_20_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C41[1][A]</td>
|
|
<td>uart0/clock_count_20_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path9</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_24_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>uart0/n22_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n22_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_24_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[0][A]</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path10</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_26_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_26_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td>uart0/clock_count_26_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_26_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td>uart0/n20_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n20_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_26_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td>uart0/clock_count_26_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[1][A]</td>
|
|
<td>uart0/clock_count_26_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path11</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.425</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.296</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_30_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_30_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][A]</td>
|
|
<td>uart0/clock_count_30_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_30_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][A]</td>
|
|
<td>uart0/n16_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n16_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.296</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_30_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][A]</td>
|
|
<td>uart0/clock_count_30_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C43[0][A]</td>
|
|
<td>uart0/clock_count_30_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path12</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.427</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.297</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_0_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_0_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C43[1][A]</td>
|
|
<td>uart0/clock_count_0_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>4</td>
|
|
<td>R14C43[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_0_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.065</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C43[1][A]</td>
|
|
<td>uart0/n46_s2/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.297</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R14C43[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n46_s2/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.297</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C43[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_0_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C43[1][A]</td>
|
|
<td>uart0/clock_count_0_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C43[1][A]</td>
|
|
<td>uart0/clock_count_0_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path13</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.428</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.299</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/state_2_s3</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/state_2_s3</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td>uart0/state_2_s3/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/state_2_s3/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.067</td>
|
|
<td>0.005</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td>uart0/n191_s14/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.299</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n191_s14/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.299</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td style=" font-weight:bold;">uart0/state_2_s3/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td>uart0/state_2_s3/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C41[1][A]</td>
|
|
<td>uart0/state_2_s3</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path14</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.428</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.299</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/state_0_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/state_0_s1</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td>uart0/state_0_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>8</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/state_0_s1/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.067</td>
|
|
<td>0.005</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td>uart0/n194_s10/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.299</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n194_s10/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.299</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td style=" font-weight:bold;">uart0/state_0_s1/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td>uart0/state_0_s1/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R15C41[0][A]</td>
|
|
<td>uart0/state_0_s1</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path15</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.483</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.354</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/send_count_1_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_1_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td>uart0/send_count_1_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>4</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_1_s2/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td>uart0/n208_s8/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.354</td>
|
|
<td>0.290</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n208_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.354</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_1_s2/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td>uart0/send_count_1_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C41[2][A]</td>
|
|
<td>uart0/send_count_1_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.290, 58.652%; route: 0.002, 0.494%; tC2Q: 0.202, 40.854%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path16</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.537</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.408</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/send_count_3_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_3_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td>uart0/send_count_3_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>2</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_3_s2/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.064</td>
|
|
<td>0.002</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td>uart0/n204_s8/I2</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.408</td>
|
|
<td>0.344</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n204_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.408</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_3_s2/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td>uart0/send_count_3_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C41[2][B]</td>
|
|
<td>uart0/send_count_3_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.344, 62.723%; route: 0.002, 0.446%; tC2Q: 0.202, 36.831%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path17</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.539</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.409</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/send_count_2_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/send_count_2_s2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>uart0/send_count_2_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.062</td>
|
|
<td>0.202</td>
|
|
<td>tC2Q</td>
|
|
<td>RR</td>
|
|
<td>3</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_2_s2/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.065</td>
|
|
<td>0.004</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>uart0/n206_s8/I0</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.409</td>
|
|
<td>0.344</td>
|
|
<td>tINS</td>
|
|
<td>RF</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n206_s8/F</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.409</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/send_count_2_s2/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>uart0/send_count_2_s2/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R14C42[2][B]</td>
|
|
<td>uart0/send_count_2_s2</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.344, 62.583%; route: 0.004, 0.667%; tC2Q: 0.202, 36.750%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path18</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.542</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.413</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_3_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_3_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td>uart0/clock_count_3_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.061</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>3</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_3_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.181</td>
|
|
<td>0.120</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td>uart0/n43_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n43_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_3_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td>uart0/clock_count_3_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C38[1][B]</td>
|
|
<td>uart0/clock_count_3_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path19</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.542</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.413</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_4_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td>uart0/clock_count_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.061</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_4_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.181</td>
|
|
<td>0.120</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td>uart0/n42_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n42_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_4_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td>uart0/clock_count_4_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C38[2][A]</td>
|
|
<td>uart0/clock_count_4_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path20</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.542</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.413</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_11_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_11_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td>uart0/clock_count_11_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.061</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_11_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.181</td>
|
|
<td>0.120</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td>uart0/n35_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n35_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_11_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td>uart0/clock_count_11_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C39[2][B]</td>
|
|
<td>uart0/clock_count_11_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path21</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.542</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.413</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_23_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_23_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C41[2][B]</td>
|
|
<td>uart0/clock_count_23_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.061</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C41[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_23_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.181</td>
|
|
<td>0.120</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C41[2][B]</td>
|
|
<td>uart0/n23_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[2][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n23_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C41[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_23_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C41[2][B]</td>
|
|
<td>uart0/clock_count_23_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C41[2][B]</td>
|
|
<td>uart0/clock_count_23_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path22</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.542</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.413</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_27_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_27_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td>uart0/clock_count_27_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.061</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_27_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.181</td>
|
|
<td>0.120</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td>uart0/n19_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n19_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_27_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td>uart0/clock_count_27_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[1][B]</td>
|
|
<td>uart0/clock_count_27_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path23</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.542</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.413</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_28_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_28_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[2][A]</td>
|
|
<td>uart0/clock_count_28_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.061</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C42[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_28_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.181</td>
|
|
<td>0.120</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C42[2][A]</td>
|
|
<td>uart0/n18_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[2][A]</td>
|
|
<td style=" background: #97FFFF;">uart0/n18_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[2][A]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_28_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[2][A]</td>
|
|
<td>uart0/clock_count_28_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[2][A]</td>
|
|
<td>uart0/clock_count_28_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path24</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.542</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.413</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_29_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_29_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[2][B]</td>
|
|
<td>uart0/clock_count_29_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.061</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C42[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_29_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.181</td>
|
|
<td>0.120</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C42[2][B]</td>
|
|
<td>uart0/n17_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[2][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n17_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.413</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C42[2][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_29_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C42[2][B]</td>
|
|
<td>uart0/clock_count_29_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C42[2][B]</td>
|
|
<td>uart0/clock_count_29_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3>Path25</h3>
|
|
<p><b>Path Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack</td>
|
|
<td>0.544</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Arrival Time</td>
|
|
<td>1.415</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Data Required Time</td>
|
|
<td>0.871</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">From</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">To</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Launch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Latch Clk</td>
|
|
<td>clock:[R]</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Arrival Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.061</td>
|
|
<td>0.201</td>
|
|
<td>tC2Q</td>
|
|
<td>RF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/Q</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.183</td>
|
|
<td>0.122</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>2</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/n15_s/I1</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.415</td>
|
|
<td>0.232</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" background: #97FFFF;">uart0/n15_s/SUM</td>
|
|
</tr>
|
|
<tr>
|
|
<td>1.415</td>
|
|
<td>0.000</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td style=" font-weight:bold;">uart0/clock_count_31_s0/D</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Data Required Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">LOC</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>42</td>
|
|
<td>IOT27[A]</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0/CLK</td>
|
|
</tr>
|
|
<tr>
|
|
<td>0.871</td>
|
|
<td>0.011</td>
|
|
<td>tHld</td>
|
|
<td></td>
|
|
<td>1</td>
|
|
<td>R13C43[0][B]</td>
|
|
<td>uart0/clock_count_31_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Path Statistics:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Clock Skew</td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Hold Relationship </td>
|
|
<td>0.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Logic Level</td>
|
|
<td>2</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Arrival Data Path Delay</td>
|
|
<td>cell: 0.232, 41.810%; route: 0.122, 21.967%; tC2Q: 0.201, 36.223%</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Clock Path Delay</td>
|
|
<td>cell: 0.675, 78.568%; route: 0.184, 21.432%</td>
|
|
</tr>
|
|
</table>
|
|
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>No recovery paths to report!</h4>
|
|
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
|
|
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
|
<h4>No removal paths to report!</h4>
|
|
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
|
|
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
|
<h3>MPW1</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_30_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_30_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_30_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW2</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_28_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_28_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_28_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW3</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_24_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_24_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW4</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_16_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_16_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_16_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW5</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_0_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_0_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_0_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW6</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_1_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_1_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_1_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW7</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_17_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_17_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_17_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW8</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_2_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_2_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_2_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW9</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_3_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_3_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_3_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h3>MPW10</h3>
|
|
<p><b>MPW Summary:</b></p>
|
|
<table class="summary_table">
|
|
<tr>
|
|
<td class="label">Slack:</td>
|
|
<td>3.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Actual Width:</td>
|
|
<td>4.911</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Required Width:</td>
|
|
<td>1.000</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Type:</td>
|
|
<td>Low Pulse Width</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label">Clock:</td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td class="label"> Objects:</td>
|
|
<td>uart0/clock_count_25_s0</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Late clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.688</td>
|
|
<td>0.688</td>
|
|
<td>tINS</td>
|
|
<td>FF</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5.949</td>
|
|
<td>0.261</td>
|
|
<td>tNET</td>
|
|
<td>FF</td>
|
|
<td>uart0/clock_count_25_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<p><b>Early clock Path:</b></p>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">AT</th>
|
|
<th class="label">DELAY</th>
|
|
<th class="label">TYPE</th>
|
|
<th class="label">RF</th>
|
|
<th>NODE</th>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>active clock edge time</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td></td>
|
|
<td></td>
|
|
<td>clock</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.000</td>
|
|
<td>0.000</td>
|
|
<td>tCL</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/I</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.675</td>
|
|
<td>0.675</td>
|
|
<td>tINS</td>
|
|
<td>RR</td>
|
|
<td>clock_ibuf/O</td>
|
|
</tr>
|
|
<tr>
|
|
<td>10.860</td>
|
|
<td>0.184</td>
|
|
<td>tNET</td>
|
|
<td>RR</td>
|
|
<td>uart0/clock_count_25_s0/CLK</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
|
|
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">FANOUT</th>
|
|
<th class="label">NET NAME</th>
|
|
<th class="label">WORST SLACK</th>
|
|
<th class="label">MAX DELAY</th>
|
|
</tr>
|
|
<tr>
|
|
<td>42</td>
|
|
<td>clock_d</td>
|
|
<td>5.947</td>
|
|
<td>0.261</td>
|
|
</tr>
|
|
<tr>
|
|
<td>33</td>
|
|
<td>n12_4</td>
|
|
<td>6.475</td>
|
|
<td>0.681</td>
|
|
</tr>
|
|
<tr>
|
|
<td>9</td>
|
|
<td>send_count_3_10</td>
|
|
<td>5.947</td>
|
|
<td>0.459</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>state[0]</td>
|
|
<td>8.340</td>
|
|
<td>0.206</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>state[1]</td>
|
|
<td>8.187</td>
|
|
<td>0.201</td>
|
|
</tr>
|
|
<tr>
|
|
<td>8</td>
|
|
<td>state[2]</td>
|
|
<td>8.202</td>
|
|
<td>0.197</td>
|
|
</tr>
|
|
<tr>
|
|
<td>5</td>
|
|
<td>send_count[0]</td>
|
|
<td>7.432</td>
|
|
<td>0.191</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>clock_count[0]</td>
|
|
<td>7.077</td>
|
|
<td>0.689</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>n204_14</td>
|
|
<td>8.340</td>
|
|
<td>0.260</td>
|
|
</tr>
|
|
<tr>
|
|
<td>4</td>
|
|
<td>send_count[1]</td>
|
|
<td>7.514</td>
|
|
<td>0.191</td>
|
|
</tr>
|
|
</table>
|
|
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
|
|
<h4>Report Command:report_route_congestion -max_grids 10</h4>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">GRID LOC</th>
|
|
<th class="label">ROUTE CONGESTIONS</th>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C39</td>
|
|
<td>77.78%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C40</td>
|
|
<td>77.78%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C42</td>
|
|
<td>76.39%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C41</td>
|
|
<td>76.39%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C38</td>
|
|
<td>61.11%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R15C41</td>
|
|
<td>45.83%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R14C41</td>
|
|
<td>44.44%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R13C43</td>
|
|
<td>41.67%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R15C42</td>
|
|
<td>36.11%</td>
|
|
</tr>
|
|
<tr>
|
|
<td>R14C42</td>
|
|
<td>34.72%</td>
|
|
</tr>
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|
</table>
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|
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
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|
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
|
|
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
|
|
<h4>No timing exceptions to report!</h4>
|
|
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
|
|
<table class="detail_table">
|
|
<tr>
|
|
<th class="label">SDC Command Type</th>
|
|
<th class="label">State</th>
|
|
<th class="label">Detail Command</th>
|
|
</tr>
|
|
</table>
|
|
</div><!-- content -->
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</body>
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</html>
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