mirror of
https://github.com/mii443/tangprimer-riscv.git
synced 2025-12-03 11:18:31 +00:00
984 lines
8.5 KiB
Plaintext
984 lines
8.5 KiB
Plaintext
=====
|
|
SETUP
|
|
5.947
|
|
4.944
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/send_count_3_s10
|
|
4.066
|
|
4.615
|
|
uart0/send_count_2_s2
|
|
4.944
|
|
=====
|
|
SETUP
|
|
6.006
|
|
4.884
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/n191_s14
|
|
4.314
|
|
4.884
|
|
uart0/state_2_s3
|
|
4.884
|
|
=====
|
|
SETUP
|
|
6.006
|
|
4.884
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/n194_s10
|
|
4.314
|
|
4.884
|
|
uart0/state_0_s1
|
|
4.884
|
|
=====
|
|
SETUP
|
|
6.130
|
|
4.760
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/send_count_3_s10
|
|
4.066
|
|
4.615
|
|
uart0/send_count_1_s2
|
|
4.760
|
|
=====
|
|
SETUP
|
|
6.130
|
|
4.760
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/send_count_3_s10
|
|
4.066
|
|
4.615
|
|
uart0/send_count_3_s2
|
|
4.760
|
|
=====
|
|
SETUP
|
|
6.229
|
|
4.662
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/n192_s14
|
|
4.291
|
|
4.662
|
|
uart0/state_1_s3
|
|
4.662
|
|
=====
|
|
SETUP
|
|
6.276
|
|
4.615
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/n210_s10
|
|
4.066
|
|
4.615
|
|
uart0/send_count_0_s4
|
|
4.615
|
|
=====
|
|
SETUP
|
|
6.276
|
|
4.615
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/n208_s8
|
|
4.066
|
|
4.615
|
|
uart0/send_count_1_s2
|
|
4.615
|
|
=====
|
|
SETUP
|
|
6.280
|
|
4.611
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.864
|
|
uart0/n204_s8
|
|
4.041
|
|
4.611
|
|
uart0/send_count_3_s2
|
|
4.611
|
|
=====
|
|
SETUP
|
|
6.448
|
|
4.443
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/n206_s8
|
|
3.873
|
|
4.443
|
|
uart0/send_count_2_s2
|
|
4.443
|
|
=====
|
|
SETUP
|
|
6.472
|
|
4.419
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/send_count_3_s5
|
|
3.402
|
|
3.855
|
|
uart0/n185_s11
|
|
4.048
|
|
4.419
|
|
uart0/tx_reg_s2
|
|
4.419
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_1_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_2_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_3_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_4_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_5_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_6_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_7_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_8_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_9_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_10_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.475
|
|
4.415
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_11_s0
|
|
4.415
|
|
=====
|
|
SETUP
|
|
6.512
|
|
4.379
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_24_s0
|
|
4.379
|
|
=====
|
|
SETUP
|
|
6.512
|
|
4.379
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_25_s0
|
|
4.379
|
|
=====
|
|
SETUP
|
|
6.512
|
|
4.379
|
|
10.891
|
|
clock_ibuf
|
|
0.000
|
|
0.683
|
|
uart0/clock_count_31_s0
|
|
0.926
|
|
1.158
|
|
uart0/n12_s6
|
|
1.822
|
|
2.275
|
|
uart0/n12_s1
|
|
2.765
|
|
3.227
|
|
uart0/n12_s0
|
|
3.402
|
|
3.864
|
|
uart0/clock_count_26_s0
|
|
4.379
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/led_flag_s1
|
|
0.860
|
|
1.062
|
|
uart0/n79_s2
|
|
1.064
|
|
1.296
|
|
uart0/led_flag_s1
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_2_s0
|
|
0.860
|
|
1.062
|
|
uart0/n44_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_2_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_6_s0
|
|
0.860
|
|
1.062
|
|
uart0/n40_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_6_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_8_s0
|
|
0.860
|
|
1.062
|
|
uart0/n38_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_8_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_12_s0
|
|
0.860
|
|
1.062
|
|
uart0/n34_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_12_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_14_s0
|
|
0.860
|
|
1.062
|
|
uart0/n32_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_14_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_18_s0
|
|
0.860
|
|
1.062
|
|
uart0/n28_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_18_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_20_s0
|
|
0.860
|
|
1.062
|
|
uart0/n26_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_20_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_24_s0
|
|
0.860
|
|
1.062
|
|
uart0/n22_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_24_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_26_s0
|
|
0.860
|
|
1.062
|
|
uart0/n20_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_26_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.425
|
|
1.296
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_30_s0
|
|
0.860
|
|
1.062
|
|
uart0/n16_s
|
|
1.064
|
|
1.296
|
|
uart0/clock_count_30_s0
|
|
1.296
|
|
=====
|
|
HOLD
|
|
0.427
|
|
1.297
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_0_s0
|
|
0.860
|
|
1.062
|
|
uart0/n46_s2
|
|
1.065
|
|
1.297
|
|
uart0/clock_count_0_s0
|
|
1.297
|
|
=====
|
|
HOLD
|
|
0.428
|
|
1.299
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/state_2_s3
|
|
0.860
|
|
1.062
|
|
uart0/n191_s14
|
|
1.067
|
|
1.299
|
|
uart0/state_2_s3
|
|
1.299
|
|
=====
|
|
HOLD
|
|
0.428
|
|
1.299
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/state_0_s1
|
|
0.860
|
|
1.062
|
|
uart0/n194_s10
|
|
1.067
|
|
1.299
|
|
uart0/state_0_s1
|
|
1.299
|
|
=====
|
|
HOLD
|
|
0.483
|
|
1.354
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/send_count_1_s2
|
|
0.860
|
|
1.062
|
|
uart0/n208_s8
|
|
1.064
|
|
1.354
|
|
uart0/send_count_1_s2
|
|
1.354
|
|
=====
|
|
HOLD
|
|
0.537
|
|
1.408
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/send_count_3_s2
|
|
0.860
|
|
1.062
|
|
uart0/n204_s8
|
|
1.064
|
|
1.408
|
|
uart0/send_count_3_s2
|
|
1.408
|
|
=====
|
|
HOLD
|
|
0.539
|
|
1.409
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/send_count_2_s2
|
|
0.860
|
|
1.062
|
|
uart0/n206_s8
|
|
1.065
|
|
1.409
|
|
uart0/send_count_2_s2
|
|
1.409
|
|
=====
|
|
HOLD
|
|
0.542
|
|
1.413
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_3_s0
|
|
0.860
|
|
1.061
|
|
uart0/n43_s
|
|
1.181
|
|
1.413
|
|
uart0/clock_count_3_s0
|
|
1.413
|
|
=====
|
|
HOLD
|
|
0.542
|
|
1.413
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_4_s0
|
|
0.860
|
|
1.061
|
|
uart0/n42_s
|
|
1.181
|
|
1.413
|
|
uart0/clock_count_4_s0
|
|
1.413
|
|
=====
|
|
HOLD
|
|
0.542
|
|
1.413
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_11_s0
|
|
0.860
|
|
1.061
|
|
uart0/n35_s
|
|
1.181
|
|
1.413
|
|
uart0/clock_count_11_s0
|
|
1.413
|
|
=====
|
|
HOLD
|
|
0.542
|
|
1.413
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_23_s0
|
|
0.860
|
|
1.061
|
|
uart0/n23_s
|
|
1.181
|
|
1.413
|
|
uart0/clock_count_23_s0
|
|
1.413
|
|
=====
|
|
HOLD
|
|
0.542
|
|
1.413
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_27_s0
|
|
0.860
|
|
1.061
|
|
uart0/n19_s
|
|
1.181
|
|
1.413
|
|
uart0/clock_count_27_s0
|
|
1.413
|
|
=====
|
|
HOLD
|
|
0.542
|
|
1.413
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_28_s0
|
|
0.860
|
|
1.061
|
|
uart0/n18_s
|
|
1.181
|
|
1.413
|
|
uart0/clock_count_28_s0
|
|
1.413
|
|
=====
|
|
HOLD
|
|
0.542
|
|
1.413
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_29_s0
|
|
0.860
|
|
1.061
|
|
uart0/n17_s
|
|
1.181
|
|
1.413
|
|
uart0/clock_count_29_s0
|
|
1.413
|
|
=====
|
|
HOLD
|
|
0.544
|
|
1.415
|
|
0.871
|
|
clock_ibuf
|
|
0.000
|
|
0.675
|
|
uart0/clock_count_31_s0
|
|
0.860
|
|
1.061
|
|
uart0/n15_s
|
|
1.183
|
|
1.415
|
|
uart0/clock_count_31_s0
|
|
1.415
|