mii/tangprimer-riscv
1
0
Fork 0
mirror of https://github.com/mii443/tangprimer-riscv.git synced 2025-12-03 11:18:31 +00:00
Code Issues Packages Projects Releases Wiki Activity
Files
main
tangprimer-riscv/impl/gwsynthesis/cpu_syn.rpt.html
mii de9ab6ca3d auipc...
2023-05-29 13:33:19 +09:00

1405 lines
25 KiB
HTML
Raw Permalink Blame History

<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html>
<head>
<title>synthesis Report</title>
<style type="text/css">
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
div#main_wrapper{ width: 100%; }
div#content { margin-left: 350px; margin-right: 30px; }
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
div#catalog ul { list-style-type: none; }
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
div#catalog a:visited { color: #0084ff; }
div#catalog a:hover { color: #fff; background: #0084ff; }
hr { margin-top: 30px; margin-bottom: 30px; }
h1, h3 { text-align: center; }
h1 {margin-top: 50px; }
table, th, td { border: 1px solid #aaa; }
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
th, td { padding: 5px 5px 5px 5px; }
th { color: #fff; font-weight: bold; background-color: #0084ff; }
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
table.detail_table td.label { min-width: 100px; width: 8%;}
</style>
</head>
<body>
<div id="main_wrapper">
<div id="catalog_wrapper">
<div id="catalog">
<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
</div><!-- catalog -->
</div><!-- catalog_wrapper -->
<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\kuroc\Downloads\cpu\src\core.v<br>
C:\Users\kuroc\Downloads\cpu\src\defs.vh<br>
C:\Users\kuroc\Downloads\cpu\src\memory.v<br>
C:\Users\kuroc\Downloads\cpu\src\top.v<br>
C:\Users\kuroc\Downloads\cpu\src\uart.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>GowinSynthesis V1.9.8.09 Education</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV18PG256C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-18C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun May 28 23:09:57 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>TOP</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.18s, Peak memory usage = 291.445MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 291.445MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 291.445MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 291.445MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 291.445MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 291.445MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 291.445MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 291.445MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 291.445MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 291.445MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 291.445MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.23s, Peak memory usage = 291.445MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 291.445MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 291.445MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 0.48s, Elapsed time = 0h 0m 0.539s, Peak memory usage = 291.445MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>42</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>5</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>32</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>32</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>7</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>21</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>31</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>31</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>2</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>65(34 LUTs, 31 ALUs) / 20736</td>
<td>1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>42 / 16173</td>
<td>1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 16173</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>42 / 16173</td>
<td>1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>0 / 46</td>
<td>0%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clock</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>clock_ibuf/I </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clock</td>
<td>100.0(MHz)</td>
<td>272.3(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.328</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.500</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart0/clock_count_24_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart0/send_count_3_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/clock_count_24_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>uart0/clock_count_24_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s1/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>uart0/n12_s1/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/send_count_3_s5/I1</td>
</tr>
<tr>
<td>3.471</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>uart0/send_count_3_s5/F</td>
</tr>
<tr>
<td>3.708</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n204_s8/I1</td>
</tr>
<tr>
<td>4.263</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>uart0/n204_s8/F</td>
</tr>
<tr>
<td>4.500</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/send_count_3_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/send_count_3_s2/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>uart0/send_count_3_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.220, 61.039%; route: 1.185, 32.582%; tC2Q: 0.232, 6.379%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.366</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.462</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart0/clock_count_24_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart0/send_count_0_s4</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/clock_count_24_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>uart0/clock_count_24_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s1/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>uart0/n12_s1/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/send_count_3_s5/I1</td>
</tr>
<tr>
<td>3.471</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>uart0/send_count_3_s5/F</td>
</tr>
<tr>
<td>3.708</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n210_s10/I0</td>
</tr>
<tr>
<td>4.225</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>uart0/n210_s10/F</td>
</tr>
<tr>
<td>4.462</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/send_count_0_s4/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/send_count_0_s4/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>uart0/send_count_0_s4</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.366</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.462</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart0/clock_count_24_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart0/tx_reg_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/clock_count_24_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>uart0/clock_count_24_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s1/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>uart0/n12_s1/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/send_count_3_s5/I1</td>
</tr>
<tr>
<td>3.471</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>uart0/send_count_3_s5/F</td>
</tr>
<tr>
<td>3.708</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n185_s11/I0</td>
</tr>
<tr>
<td>4.225</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>uart0/n185_s11/F</td>
</tr>
<tr>
<td>4.462</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/tx_reg_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/tx_reg_s2/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>uart0/tx_reg_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.182, 60.628%; route: 1.185, 32.926%; tC2Q: 0.232, 6.446%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.437</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart0/clock_count_24_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart0/send_count_1_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/clock_count_24_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>uart0/clock_count_24_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s1/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>uart0/n12_s1/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/send_count_3_s5/I1</td>
</tr>
<tr>
<td>3.471</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>uart0/send_count_3_s5/F</td>
</tr>
<tr>
<td>3.708</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/send_count_3_s10/I0</td>
</tr>
<tr>
<td>4.257</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>uart0/send_count_3_s10/F</td>
</tr>
<tr>
<td>4.437</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/send_count_1_s2/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/send_count_1_s2/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>uart0/send_count_1_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.214, 61.948%; route: 1.128, 31.561%; tC2Q: 0.232, 6.491%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>4.437</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.828</td>
</tr>
<tr>
<td class="label">From</td>
<td>uart0/clock_count_24_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>uart0/send_count_2_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>clock[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clock[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>0.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/clock_count_24_s0/CLK</td>
</tr>
<tr>
<td>1.095</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>2</td>
<td>uart0/clock_count_24_s0/Q</td>
</tr>
<tr>
<td>1.332</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/I1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s5/F</td>
</tr>
<tr>
<td>2.124</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/n12_s1/I1</td>
</tr>
<tr>
<td>2.679</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>uart0/n12_s1/F</td>
</tr>
<tr>
<td>2.916</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/send_count_3_s5/I1</td>
</tr>
<tr>
<td>3.471</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>9</td>
<td>uart0/send_count_3_s5/F</td>
</tr>
<tr>
<td>3.708</td>
<td>0.237</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>uart0/send_count_3_s10/I0</td>
</tr>
<tr>
<td>4.257</td>
<td>0.549</td>
<td>tINS</td>
<td>FR</td>
<td>3</td>
<td>uart0/send_count_3_s10/F</td>
</tr>
<tr>
<td>4.437</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/send_count_2_s2/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clock</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clock_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>42</td>
<td>clock_ibuf/O</td>
</tr>
<tr>
<td>10.863</td>
<td>0.180</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>uart0/send_count_2_s2/CLK</td>
</tr>
<tr>
<td>10.828</td>
<td>-0.035</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>uart0/send_count_2_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>5</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 2.214, 61.948%; route: 1.128, 31.561%; tC2Q: 0.232, 6.491%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 79.130%; route: 0.180, 20.870%</td></tr>
</table>
<br/>
</div><!-- content -->
</div><!-- main_wrapper -->
</body>
</html>
Reference in New Issue View Git Blame Copy Permalink