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ec8e23e37f80072a67ad409e6cdf67b65bb19eef
qemu/target
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David Hildenbrand ec8e23e37f s390x: Align vector registers to 16 bytes 
11e2bfef79 ("tcg/i386: Use MOVDQA for TCG_TYPE_V128 load/store")
revealed that the vregs are not aligned to 16 bytes. Align them to
16 bytes, to avoid segfault'ing on x86.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
2019-06-07 14:53:25 +02:00
..
alpha
target/alpha: Fix user-only floating-point exceptions
2019-05-19 07:30:03 -07:00
arm
target/arm: correct return values for WRITE/READ in arm-semi
2019-05-28 10:28:51 +01:00
cris
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into staging
2019-05-16 13:15:08 +01:00
hppa
tcg: Use CPUClass::tlb_fill in cputlb.c
2019-05-10 11:12:50 -07:00
i386
i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor
2019-06-03 14:03:01 +02:00
lm32
semihosting: move semihosting configuration into its own directory
2019-05-28 10:28:50 +01:00
m68k
semihosting: move semihosting configuration into its own directory
2019-05-28 10:28:50 +01:00
microblaze
tcg: Use CPUClass::tlb_fill in cputlb.c
2019-05-10 11:12:50 -07:00
mips
target/mips: Unroll loops in helpers for MSA logic instructions
2019-06-07 11:53:07 +02:00
moxie
tcg: Use CPUClass::tlb_fill in cputlb.c
2019-05-10 11:12:50 -07:00
nios2
semihosting: move semihosting configuration into its own directory
2019-05-28 10:28:50 +01:00
openrisc
tcg: Use CPUClass::tlb_fill in cputlb.c
2019-05-10 11:12:50 -07:00
ppc
spapr/xive: add KVM support
2019-05-29 11:39:45 +10:00
riscv
target/riscv: Only flush TLB if SATP.ASID changes
2019-05-24 12:09:25 -07:00
s390x
s390x: Align vector registers to 16 bytes
2019-06-07 14:53:25 +02:00
sh4
tcg: Use CPUClass::tlb_fill in cputlb.c
2019-05-10 11:12:50 -07:00
sparc
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into staging
2019-05-16 13:15:08 +01:00
tilegx
target/tilegx: Convert to CPUClass::tlb_fill
2019-05-10 11:12:50 -07:00
tricore
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190510' into staging
2019-05-16 13:15:08 +01:00
unicore32
tcg: Use CPUClass::tlb_fill in cputlb.c
2019-05-10 11:12:50 -07:00
xtensa
semihosting: move semihosting configuration into its own directory
2019-05-28 10:28:50 +01:00