Yu Li 7035b8420f docs/system: riscv: Update description of CPU ...

Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.

Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2022-02-16 12:25:52 +10:00

..

microchip-icicle-kit.rst

docs: Format literals correctly

2021-08-02 11:42:38 +01:00

shakti-c.rst

Fix some typos in documentation (found by codespell)

2021-11-22 15:02:38 +01:00

sifive_u.rst

docs/system/riscv: sifive_u: Update U-Boot instructions

2021-09-21 07:56:49 +10:00

virt.rst

docs/system: riscv: Update description of CPU

2022-02-16 12:25:52 +10:00