Chih-Min Chao 15161e425e target/riscv: change the api for RVF/RVD fmin/fmax ...

The sNaN propagation behavior has been changed since cd20cee7 in
https://github.com/riscv/riscv-isa-manual.

In Priv spec v1.10, RVF is v2.0. fmin.s and fmax.s are implemented with
IEEE 754-2008 minNum and maxNum operations.

In Priv spec v1.11, RVF is v2.2. fmin.s and fmax.s are amended to
implement IEEE 754-2019 minimumNumber and maximumNumber operations.

Therefore, to prevent the risk of having too many version variables.
Instead of introducing an extra *fext_ver* variable, we tie RVF version
to Priv version. Though it's not completely accurate but is close enough.

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211021160847.2748577-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2021-10-29 16:56:12 +10:00

..

insn_trans

target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions

2021-10-28 14:39:23 +10:00

arch_dump.c

target-riscv: support QMP dump-guest-memory

2021-03-04 09:43:29 -05:00

bitmanip_helper.c

target/riscv: Add rev8 instruction, removing grev/grevi

2021-10-07 08:41:33 +10:00

cpu_bits.h

target/riscv: remove force HS exception

2021-10-29 16:54:45 +10:00

cpu_helper.c

target/riscv: remove force HS exception

2021-10-29 16:54:45 +10:00

cpu_user.h

Supply missing header guards

2019-06-12 13:20:21 +02:00

cpu-param.h

target/riscv: Add a virtualised MMU Mode

2020-11-09 15:08:45 -08:00

cpu.c

target/riscv: Allow experimental J-ext to be turned on

2021-10-28 14:39:23 +10:00

cpu.h

target/riscv: remove force HS exception

2021-10-29 16:54:45 +10:00

csr.c

target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode

2021-10-28 14:39:23 +10:00

fpu_helper.c

target/riscv: change the api for RVF/RVD fmin/fmax

2021-10-29 16:56:12 +10:00

gdbstub.c

target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl

2021-10-22 07:47:51 +10:00

helper.h

target/riscv: Add rev8 instruction, removing grev/grevi

2021-10-07 08:41:33 +10:00

insn16.decode

target/riscv: Consolidate RV32/64 16-bit instructions

2021-05-11 20:02:07 +10:00

insn32.decode

target/riscv: Remove RVB (replaced by Zb[abcs])

2021-10-07 08:41:33 +10:00

instmap.h

target/riscv: progressively load the instruction during decode

2020-02-25 20:20:23 +00:00

internals.h

target/riscv: Add basic vmstate description of CPU

2020-11-03 07:17:23 -08:00

Kconfig

meson: Introduce target-specific Kconfig

2021-07-09 18:21:34 +02:00

machine.c

target/riscv: Add J extension state description

2021-10-28 14:39:23 +10:00

meson.build

target/riscv: rvb: generalized reverse

2021-06-08 09:59:45 +10:00

monitor.c

target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl

2021-10-22 07:47:51 +10:00

op_helper.c

target/riscv: Reorg csr instructions

2021-09-01 11:59:12 +10:00

pmp.c

target/riscv: pmp: Fix some typos

2021-07-15 08:56:00 +10:00

pmp.h

target/riscv: Add ePMP CSR access functions

2021-05-11 20:02:06 +10:00

trace-events

target/riscv: Add ePMP CSR access functions

2021-05-11 20:02:06 +10:00

trace.h

trace: switch position of headers to what Meson requires

2020-08-21 06:18:24 -04:00

translate.c

target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension

2021-10-28 14:39:23 +10:00

vector_helper.c

target/riscv: Consolidate RV32/64 32-bit instructions

2021-05-11 20:02:07 +10:00