mii/qemu
1
0
Fork 0
mirror of https://github.com/mii443/qemu.git synced 2025-12-04 03:28:31 +00:00
Code Issues Packages Projects Releases Wiki Activity
Files
dd8014e4e904e895435aae9f11a686f072762782
qemu/include/hw/riscv
History
Bin Meng 6eaf9cf56f hw/riscv: sifive_u: Add a dummy L2 cache controller device 
It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-08-21 22:37:55 -07:00
..
boot_opensbi.h
riscv: Add opensbi firmware dynamic support
2020-07-13 17:25:37 -07:00
boot.h
riscv: Add opensbi firmware dynamic support
2020-07-13 17:25:37 -07:00
opentitan.h
riscv/opentitan: Connect the UART device
2020-06-19 08:24:07 -07:00
riscv_hart.h
riscv: hart: Add a "hartid-base" property to RISC-V hart array
2019-09-17 08:42:47 -07:00
riscv_htif.h
Clean up inclusion of sysemu/sysemu.h
2019-08-16 13:31:53 +02:00
sifive_clint.h
hw/riscv: Provide rdtime callback for TCG in CLINT emulation
2020-02-27 13:46:37 -08:00
sifive_cpu.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_e_prci.h
riscv: sifive_e: prci: Update the PRCI register block size
2019-09-17 08:42:46 -07:00
sifive_e.h
sifive_e: Support the revB machine
2020-06-19 08:24:07 -07:00
sifive_gpio.h
hw/riscv: sifive_gpio: Add a new 'ngpio' property
2020-06-19 08:24:07 -07:00
sifive_plic.h
riscv: plic: Remove unused interrupt functions
2019-09-17 08:42:42 -07:00
sifive_test.h
riscv: sifive_test: Add reset functionality
2019-09-17 08:42:44 -07:00
sifive_u_otp.h
riscv: sifive: Implement a model for SiFive FU540 OTP
2019-09-17 08:42:49 -07:00
sifive_u_prci.h
riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
2019-09-17 08:42:48 -07:00
sifive_u.h
hw/riscv: sifive_u: Add a dummy L2 cache controller device
2020-08-21 22:37:55 -07:00
sifive_uart.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00
spike.h
hw/riscv: spike: Remove deprecated ISA specific machines
2020-06-03 09:11:51 -07:00
virt.h
riscv: virt: Use Goldfish RTC device
2020-02-10 12:01:38 -08:00