mii/qemu
1
0
Fork 0
mirror of https://github.com/mii443/qemu.git synced 2025-12-03 19:18:23 +00:00
Code Issues Packages Projects Releases Wiki Activity
Files
dbdea0dbfe2cef9ef6c752e9077e4fc98724194c
qemu/include/hw/riscv
History
Sunil V L 7da2fb240f hw/riscv/virt: Enable basic ACPI infrastructure 
Add basic ACPI infrastructure for RISC-V with below tables.
        1) DSDT with below basic objects
                - CPUs
                - fw_cfg
        2) FADT revision 6 with HW_REDUCED flag
        3) XSDT
        4) RSDP

Add this functionality in a new file virt-acpi-build.c and enable
building this infrastructure.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20230302091212.999767-5-sunilvl@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06 11:35:04 -08:00
..
boot_opensbi.h
include: Include headers where needed
2023-01-08 01:54:22 -05:00
boot.h
hw/riscv/boot.c: make riscv_load_initrd() static
2023-02-16 07:55:37 -08:00
microchip_pfsoc.h
include: Include headers where needed
2023-01-08 01:54:22 -05:00
numa.h
hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix()
2023-01-20 10:14:14 +10:00
opentitan.h
include/hw/riscv/opentitan: update opentitan IRQs
2023-02-07 08:19:22 +10:00
riscv_hart.h
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
shakti_c.h
hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
2023-01-06 10:42:55 +10:00
sifive_cpu.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_e.h
hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
2023-01-06 10:42:55 +10:00
sifive_u.h
hw/riscv: Move the dtb load bits outside of create_fdt()
2023-03-01 17:19:14 -08:00
spike.h
hw/riscv/spike: use 'fdt' from MachineState
2023-01-20 10:14:13 +10:00
virt.h
hw/riscv/virt: Enable basic ACPI infrastructure
2023-03-06 11:35:04 -08:00