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dad2f2f5afbaf58d6056f31dfd4b9edd0854b8ab
qemu/tcg/sparc64
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Richard Henderson dad2f2f5af tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32 
Since a59a293126 ("tcg/sparc64: Remove sparc32plus constraints")
we no longer distinguish registers with 32 vs 64 bits.
Therefore we can remove support for the backend-specific
type change opcodes.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-29 09:57:39 -07:00
..
tcg-target-con-set.h
tcg/sparc64: Use standard slow path for softmmu
2023-05-16 15:21:39 -07:00
tcg-target-con-str.h
tcg/sparc64: Use standard slow path for softmmu
2023-05-16 15:21:39 -07:00
tcg-target-reg-bits.h
tcg: Split out tcg-target-reg-bits.h
2023-06-05 12:04:28 -07:00
tcg-target.c.inc
tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32
2023-08-29 09:57:39 -07:00
tcg-target.h
tcg/sparc64: Disable TCG_TARGET_HAS_extr_i64_i32
2023-08-29 09:57:39 -07:00