Peter Maydell bb27210c8c pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset ...

Convert the TYPE_PCIE_ROOT_PORT device to 3-phase reset; this is a
necessary precursor to converting any of its child classes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221125115240.3005559-4-peter.maydell@linaro.org

2022-12-16 15:59:07 +00:00

..

cxl_downstream.c

pci-bridge/cxl_downstream: Add a CXL switch downstream port

2022-06-16 12:54:57 -04:00

cxl_root_port.c

hw/cxl/rp: Add a root port

2022-05-13 06:13:36 -04:00

cxl_upstream.c

hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE

2022-11-07 13:12:19 -05:00

dec.c

Use OBJECT_DECLARE_SIMPLE_TYPE when possible

2020-09-18 14:12:32 -04:00

dec.h

Include qemu-common.h exactly where needed

2019-06-12 13:20:20 +02:00

gen_pcie_root_port.c

hw/pcie-root-port: Fix hotplug for PCI devices requiring IO

2021-08-03 16:31:07 -04:00

i82801b11.c

nomaintainer: Fix Lesser GPL version number

2020-11-15 17:04:40 +01:00

ioh3420.c

Include migration/vmstate.h less

2019-08-16 13:31:52 +02:00

Kconfig

hw/cxl/rp: Add a root port

2022-05-13 06:13:36 -04:00

meson.build

pci-bridge/cxl_downstream: Add a CXL switch downstream port

2022-06-16 12:54:57 -04:00

pci_bridge_dev.c

Use OBJECT_DECLARE_SIMPLE_TYPE when possible

2020-09-18 14:12:32 -04:00

pci_expander_bridge_stubs.c

pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.

2022-06-09 19:32:49 -04:00

pci_expander_bridge.c

pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.

2022-06-09 19:32:49 -04:00

pcie_pci_bridge.c

Use OBJECT_DECLARE_SIMPLE_TYPE when possible

2020-09-18 14:12:32 -04:00

pcie_root_port.c

pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset

2022-12-16 15:59:07 +00:00

simba.c

Include qemu/module.h where needed, drop it from qemu-common.h

2019-06-12 13:18:33 +02:00

xio3130_downstream.c

pci: expose TYPE_XIO3130_DOWNSTREAM name

2022-03-06 05:08:23 -05:00

xio3130_upstream.c

pci-bridge/xio3130_upstream: Fix error handling

2022-03-06 05:08:23 -05:00