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qemu/include/hw/riscv
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Alex Bennée c65d7080d8 hw/riscv: migrate fdt field to generic MachineState 
This is a mechanical change to make the fdt available through
MachineState.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210303173642.3805-3-alex.bennee@linaro.org>
2021-03-10 15:34:11 +00:00
..
boot_opensbi.h
riscv: Add opensbi firmware dynamic support
2020-07-13 17:25:37 -07:00
boot.h
riscv: Pass RISCVHartArrayState by pointer
2021-01-16 14:34:46 -08:00
microchip_pfsoc.h
hw/riscv: microchip_pfsoc: add QSPI NOR flash
2020-12-17 21:56:43 -08:00
numa.h
hw/riscv: Add helpers for RISC-V multi-socket NUMA machines
2020-08-25 09:11:35 -07:00
opentitan.h
riscv/opentitan: Update the OpenTitan memory layout
2020-12-17 21:56:44 -08:00
riscv_hart.h
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
sifive_cpu.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_e.h
sifive_e: Rename memmap enum constants
2020-09-18 13:49:48 -04:00
sifive_u.h
hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value
2021-03-04 09:43:29 -05:00
spike.h
riscv: spike: Remove target macro conditionals
2020-12-17 21:56:44 -08:00
virt.h
hw/riscv: migrate fdt field to generic MachineState
2021-03-10 15:34:11 +00:00