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I noticed i2c rx transfers were getting shortened to "1" on Zephyr. It seems to be because the Zephyr i2c driver sets the RX DMA len with the RX field write-enable bit set (bit 31) to avoid a read-modify-write. [1] /* 0x1C : I2CM Master DMA Transfer Length Register */ I think we should be checking the write-enable bits on the incoming value, not checking the register array. I'm not sure we're even writing the write-enable bits to the register array, actually. [1]db3dbcc9c5/drivers/i2c/i2c_aspeed.c (L145-L148)Fixes:ba2cccd64e("aspeed: i2c: Add new mode support") Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220630045133.32251-3-me@pjd.dev> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>