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qemu/target/riscv/insn_trans
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Weiwei Li 356c13f94d target/riscv: Enable PC-relative translation 
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Use gen_pc_plus_diff to get the pc-relative address.
Enable CF_PCREL in System mode.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230526072124.298466-7-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13 17:37:12 +10:00
..
trans_privileged.c.inc
target/riscv: Change gen_set_pc_imm to gen_update_pc
2023-06-13 17:35:20 +10:00
trans_rva.c.inc
target/riscv: Ensure opcode is saved for all relevant instructions
2023-02-07 08:19:23 +10:00
trans_rvb.c.inc
target/riscv: Drop tcg_temp_free
2023-03-05 13:44:08 -08:00
trans_rvd.c.inc
target/riscv: Update check for Zca/Zcf/Zcd
2023-06-13 17:01:30 +10:00
trans_rvf.c.inc
target/riscv: Reuse tb->flags.FS
2023-06-13 17:24:00 +10:00
trans_rvh.c.inc
target/riscv: Handle HLV, HSV via helpers
2023-05-05 10:49:50 +10:00
trans_rvi.c.inc
target/riscv: Enable PC-relative translation
2023-06-13 17:37:12 +10:00
trans_rvk.c.inc
target/riscv: Drop tcg_temp_free
2023-03-05 13:44:08 -08:00
trans_rvm.c.inc
target/riscv: Drop tcg_temp_free
2023-03-05 13:44:08 -08:00
trans_rvv.c.inc
target/riscv: Change gen_set_pc_imm to gen_update_pc
2023-06-13 17:35:20 +10:00
trans_rvzawrs.c.inc
target/riscv: Change gen_set_pc_imm to gen_update_pc
2023-06-13 17:35:20 +10:00
trans_rvzce.c.inc
target/riscv: Enable PC-relative translation
2023-06-13 17:37:12 +10:00
trans_rvzfh.c.inc
target/riscv: Avoid tcg_const_*
2023-03-05 13:46:13 -08:00
trans_rvzicbo.c.inc
target/riscv: implement Zicbom extension
2023-03-05 11:49:42 -08:00
trans_rvzicond.c.inc
target/riscv: refactor Zicond support
2023-05-05 10:49:50 +10:00
trans_svinval.c.inc
target/riscv: Ensure opcode is saved for all relevant instructions
2023-02-07 08:19:23 +10:00
trans_xthead.c.inc
target/riscv: Change gen_set_pc_imm to gen_update_pc
2023-06-13 17:35:20 +10:00
trans_xventanacondops.c.inc
target/riscv: redirect XVentanaCondOps to use the Zicond functions
2023-05-05 10:49:50 +10:00