Michael Clark 5aec3247c1 RISC-V: Mark ROM read-only after copying in code ...

The sifive_u machine already marks its ROM readonly however
it has the wrong base address for its mask ROM. This patch
fixes the sifive_u mask ROM base address.

This commit makes all other boards consistently use mask_rom
as the variable name for their ROMs. Boards that use device
tree now check that that the device tree fits in the assigned
ROM space using the new qemu_fdt_totalsize(void *fdt)
interface, adding a bounds check and error message. This
can detect truncation.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <Alistair.Francis@wdc.com>

2018-05-06 10:54:21 +12:00

..

Makefile.objs

RISC-V Build Infrastructure

2018-03-07 08:30:28 +13:00

riscv_hart.c

RISC-V: Remove unused class definitions

2018-05-06 10:39:38 +12:00

riscv_htif.c

…

sifive_clint.c

RISC-V: Replace hardcoded constants with enum values

2018-05-06 10:39:38 +12:00

sifive_e.c

RISC-V: Mark ROM read-only after copying in code

2018-05-06 10:54:21 +12:00

sifive_plic.c

SiFive RISC-V PLIC Block

2018-03-07 08:30:28 +13:00

sifive_prci.c

SiFive RISC-V PRCI Block

2018-03-07 08:30:28 +13:00

sifive_test.c

SiFive RISC-V Test Finisher

2018-03-07 08:30:28 +13:00

sifive_u.c

RISC-V: Mark ROM read-only after copying in code

2018-05-06 10:54:21 +12:00

sifive_uart.c

SiFive RISC-V UART Device

2018-03-07 08:30:28 +13:00

spike.c

RISC-V: Mark ROM read-only after copying in code

2018-05-06 10:54:21 +12:00

virt.c

RISC-V: Mark ROM read-only after copying in code

2018-05-06 10:54:21 +12:00