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Capstone disassembler # gpg: Signature made Thu 26 Oct 2017 10:57:27 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dis-20171026: disas: Add capstone as submodule disas: Remove monitor_disas_is_physical ppc: Support Capstone in disas_set_info arm: Support Capstone in disas_set_info i386: Support Capstone in disas_set_info disas: Support the Capstone disassembler library disas: Remove unused flags arguments target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLY target/arm: Move BE32 disassembler fixup target/ppc: Convert to disas_set_info hook target/i386: Convert to disas_set_info hook Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/i386/cpu.c # target/ppc/translate_init.c
LatticeMico32 target -------------------- General ------- All opcodes including the JUART CSRs are supported. JTAG UART --------- JTAG UART is routed to a serial console device. For the current boards it is the second one. Ie to enable it in the qemu virtual console window use the following command line parameters: -serial vc -serial vc This will make serial0 (the lm32_uart) and serial1 (the JTAG UART) available as virtual consoles. Semihosting ----------- Semihosting on this target is supported. Some system calls like read, write and exit are executed on the host if semihosting is enabled. See target/lm32-semi.c for all supported system calls. Emulation aware programs can use this mechanism to shut down the virtual machine and print to the host console. See the tcg tests for an example. Special instructions -------------------- The translation recognizes one special instruction to halt the cpu: and r0, r0, r0 On real hardware this instruction is a nop. It is not used by GCC and should (hopefully) not be used within hand-crafted assembly. Insert this instruction in your idle loop to reduce the cpu load on the host. Ignoring the MSB of the address bus ----------------------------------- Some SoC ignores the MSB on the address bus. Thus creating a shadow memory area. As a general rule, 0x00000000-0x7fffffff is cached, whereas 0x80000000-0xffffffff is not cached and used to access IO devices. This behaviour can be enabled with: cpu_lm32_set_phys_msb_ignore(env, 1);