Cédric Le Goater 6da4433fc5 aspeed/smc: add a 'sdram_base' property ...

The DRAM address of a DMA transaction depends on the DRAM base address
of the SoC. Inform the SMC controller model with this value.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190618165311.27066-15-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2019-07-01 17:28:59 +01:00

..

aspeed_smc.h

aspeed/smc: add a 'sdram_base' property

2019-07-01 17:28:59 +01:00

imx_spi.h

i.MX: Add the Freescale SPI Controller

2016-05-12 13:22:29 +01:00

mss-spi.h

msf2: Add Smartfusion2 SPI controller

2017-09-21 16:36:56 +01:00

pl022.h

hw/ssi/pl022: Allow use as embedded-struct device

2018-08-24 13:17:44 +01:00

ssi.h

ssi: change ssi_slave_init to be a realize ops

2016-07-04 13:15:22 +01:00

stm32f2xx_spi.h

STM32F2xx: Add the SPI device

2016-10-04 13:28:07 +01:00

xilinx_spips.h

xilinx_spips: Make dma transactions as per dma_burst_size

2018-06-26 17:50:39 +01:00