Vijai Kumar K 8a2aca3d79 hw/riscv: Connect Shakti UART to Shakti platform ...

Connect one shakti uart to the shakti_c machine.

Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210401181457.73039-5-vijai@behindbytes.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2021-05-11 20:02:06 +10:00

..

boot.c

riscv: Pass RISCVHartArrayState by pointer

2021-01-16 14:34:46 -08:00

Kconfig

riscv: Add initial support for Shakti C machine

2021-05-11 20:01:38 +10:00

meson.build

riscv: Add initial support for Shakti C machine

2021-05-11 20:01:38 +10:00

microchip_pfsoc.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

numa.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

opentitan.c

Do not include exec/address-spaces.h if it's not really necessary

2021-05-02 17:24:51 +02:00

riscv_hart.c

hw/riscv: hart: Add a new 'resetvec' property

2020-09-09 15:54:18 -07:00

shakti_c.c

hw/riscv: Connect Shakti UART to Shakti platform

2021-05-11 20:02:06 +10:00

sifive_e.c

hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]

2021-05-11 20:01:10 +10:00

sifive_u.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

spike.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

virt.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00