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7b6bb66f02bc81a6bb5d90a4fe08ab9c6841a936
qemu/include/hw/riscv
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Bin Meng 7b6bb66f02 riscv: sifive_u: Fix broken GEM support 
At present the GEM support in sifive_u machine is seriously broken.
The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.

Not like other GEM variants, the FU540-specific GEM has a management
block to control 10/100/1000Mbps link speed changes, that is mapped
to 0x100a0000. We can simply map it into MMIO space without special
handling using create_unimplemented_device().

Update the GEM node compatible string to use the official name used
by the upstream Linux kernel, and add the management block reg base
& size to the <reg> property encoding.

Tested with upstream U-Boot and Linux kernel MACB drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17 08:42:49 -07:00
..
boot.h
riscv: Add a helper routine for finding firmware
2019-09-17 08:42:43 -07:00
riscv_hart.h
riscv: hart: Add a "hartid-base" property to RISC-V hart array
2019-09-17 08:42:47 -07:00
riscv_htif.h
Clean up inclusion of sysemu/sysemu.h
2019-08-16 13:31:53 +02:00
sifive_clint.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00
sifive_cpu.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_e_prci.h
riscv: sifive_e: prci: Update the PRCI register block size
2019-09-17 08:42:46 -07:00
sifive_e.h
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
2019-09-17 08:42:46 -07:00
sifive_gpio.h
SiFive RISC-V GPIO Device
2019-05-24 11:58:30 -07:00
sifive_plic.h
riscv: plic: Remove unused interrupt functions
2019-09-17 08:42:42 -07:00
sifive_test.h
riscv: sifive_test: Add reset functionality
2019-09-17 08:42:44 -07:00
sifive_u_otp.h
riscv: sifive: Implement a model for SiFive FU540 OTP
2019-09-17 08:42:49 -07:00
sifive_u_prci.h
riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
2019-09-17 08:42:48 -07:00
sifive_u.h
riscv: sifive_u: Fix broken GEM support
2019-09-17 08:42:49 -07:00
sifive_uart.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00
spike.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00
virt.h
include: Make headers more self-contained
2019-08-16 13:31:51 +02:00