Anup Patel 092dc6df92 hw/riscv: Remove macros for ELF BIOS image names ...

Now that RISC-V Spike machine can use BIN BIOS images, we remove
the macros used for ELF BIOS image names.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2022-01-21 15:52:57 +10:00

..

boot.c

target/riscv: Support start kernel directly by KVM

2022-01-21 15:52:56 +10:00

Kconfig

hw/intc: Rename sifive_clint sources to riscv_aclint sources

2021-09-21 07:56:49 +10:00

meson.build

hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines

2021-07-20 15:32:49 +02:00

microchip_pfsoc.c

hw/riscv: Use error_fatal for SoC realisation

2022-01-08 15:46:09 +10:00

numa.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

opentitan.c

riscv: opentitan: fixup plic stride len

2022-01-21 15:52:56 +10:00

riscv_hart.c

hw/riscv: hart: Add a new 'resetvec' property

2020-09-09 15:54:18 -07:00

shakti_c.c

hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id

2021-10-22 23:35:47 +10:00

sifive_e.c

hw/riscv: Use error_fatal for SoC realisation

2022-01-08 15:46:09 +10:00

sifive_u.c

hw/riscv: Use error_fatal for SoC realisation

2022-01-08 15:46:09 +10:00

spike.c

hw/riscv: Remove macros for ELF BIOS image names

2022-01-21 15:52:57 +10:00

virt.c

target/riscv: Support start kernel directly by KVM

2022-01-21 15:52:56 +10:00