Daniel Henrique Barboza 6934f15b22 hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() ...

The 'fdt' param is not being used in riscv_setup_rom_reset_vec().
Simplify the API by removing it. While we're at it, remove the redundant
'return' statement at the end of function.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bin.meng@windriver.com>
Cc: Vijai Kumar K <vijai@behindbytes.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220728181926.2123771-1-danielhb413@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2022-09-07 09:18:33 +02:00

..

boot.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00

Kconfig

hw/riscv: Enable TPM backends

2022-04-29 10:48:48 +10:00

meson.build

hw/riscv/Kconfig: Restrict NUMA to Virt & Spike machines

2021-07-20 15:32:49 +02:00

microchip_pfsoc.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00

numa.c

hw: Do not include qemu/log.h if it is not necessary

2021-05-02 17:24:50 +02:00

opentitan.c

hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

2022-05-24 10:38:50 +10:00

riscv_hart.c

hw/riscv: hart: Add a new 'resetvec' property

2020-09-09 15:54:18 -07:00

shakti_c.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00

sifive_e.c

hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

2022-05-24 10:38:50 +10:00

sifive_u.c

hw/riscv/sifive_u: Resolve redundant property accessors

2022-05-24 10:38:50 +10:00

spike.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00

virt.c

hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()

2022-09-07 09:18:33 +02:00