mirror of
https://github.com/mii443/qemu.git
synced 2025-08-28 01:49:38 +00:00
Upon activating an interrupt, set the corresponding priority bit in the APR/NSAPR registers without touching the currently set bits. In the event of nested interrupts, the GIC will then have the information it needs to restore the priority of the pre-empted interrupt once the higher priority interrupt finishes execution. Signed-off-by: François Baldassari <francois@pebble.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>