Alistair Francis d4cad54499 hw/opentitan: Update the interrupt layout ...

Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com

2021-05-11 20:02:06 +10:00

..

boot_opensbi.h

riscv: Add opensbi firmware dynamic support

2020-07-13 17:25:37 -07:00

boot.h

riscv: Pass RISCVHartArrayState by pointer

2021-01-16 14:34:46 -08:00

microchip_pfsoc.h

hw/riscv: microchip_pfsoc: Map EMMC/SD mux register

2021-03-22 21:54:40 -04:00

numa.h

hw/riscv: Add helpers for RISC-V multi-socket NUMA machines

2020-08-25 09:11:35 -07:00

opentitan.h

hw/opentitan: Update the interrupt layout

2021-05-11 20:02:06 +10:00

riscv_hart.h

Use OBJECT_DECLARE_SIMPLE_TYPE when possible

2020-09-18 14:12:32 -04:00

shakti_c.h

hw/riscv: Connect Shakti UART to Shakti platform

2021-05-11 20:02:06 +10:00

sifive_cpu.h

riscv: Add a sifive_cpu.h to include both E and U cpu type defines

2019-09-17 08:42:46 -07:00

sifive_e.h

sifive_e: Rename memmap enum constants

2020-09-18 13:49:48 -04:00

sifive_u.h

hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value

2021-03-04 09:43:29 -05:00

spike.h

riscv: spike: Remove target macro conditionals

2020-12-17 21:56:44 -08:00

virt.h

hw/riscv: Add fw_cfg support to virt

2021-03-22 21:54:40 -04:00