Igor V. Kovalenko d532b26c9d sparc64: interrupt trap handling ...

cpu_check_irqs
- handle SOFTINT register TICK and STICK timer bits
- only check interrupt levels greater than PIL value
- handle preemption by higher level traps

cpu_exec
- handle CPU_INTERRUPT_HARD only if interrupts are enabled
- PIL 15 is not special level on sparcv9

Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

2010-01-08 17:25:13 +00:00

..

cpu.h

sparc64: interrupt trap handling

2010-01-08 17:25:13 +00:00

exec.h

sparc64: move cpu_interrupts_enabled to cpu.h

2010-01-08 17:16:45 +00:00

helper.c

sparc64: add PIL to cpu state dump

2010-01-08 17:13:20 +00:00

helper.h

sparc64: use helper_wrpil to check pending irq on write

2010-01-08 17:14:11 +00:00

machine.c

Sparc64: replace tsptr with helper routine

2009-08-04 20:22:10 +00:00

op_helper.c

sparc64: check for pending irq when pil, pstate or softint is changed

2010-01-08 17:15:05 +00:00

TODO

Remove unnecessary trailing newlines

2008-12-13 09:32:43 +00:00

translate.c

sparc64: use helper_wrpil to check pending irq on write

2010-01-08 17:14:11 +00:00