Markus Armbruster 3e9a88c372 riscv_hart: Fix riscv_harts_realize() error API violations ...

The Error ** argument must be NULL, &error_abort, &error_fatal, or a
pointer to a variable containing NULL.  Passing an argument of the
latter kind twice without clearing it in between is wrong: if the
first call sets an error, it no longer points to NULL for the second
call.

riscv_harts_realize() is wrong that way: it passes @errp to
riscv_hart_realize() in a loop.  I can't tell offhand whether this can
fail.

Fix by checking for failure in each iteration.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: qemu-riscv@nongnu.org
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20200630090351.1247703-19-armbru@redhat.com>

2020-07-02 06:25:29 +02:00

..

boot.c

riscv: Change the default behavior if no -bios option is specified

2020-06-03 09:11:51 -07:00

Kconfig

hw/char: Initial commit of Ibex UART

2020-06-19 08:24:07 -07:00

Makefile.objs

riscv: Initial commit of OpenTitan machine

2020-06-03 09:11:51 -07:00

opentitan.c

hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions

2020-06-19 08:24:07 -07:00

riscv_hart.c

riscv_hart: Fix riscv_harts_realize() error API violations

2020-07-02 06:25:29 +02:00

riscv_htif.c

chardev: Use QEMUChrEvent enum in IOEventHandler typedef

2020-01-08 11:15:35 +01:00

sifive_clint.c

sysbus: Convert to sysbus_realize() etc. with Coccinelle

2020-06-15 22:05:28 +02:00

sifive_e_prci.c

sysbus: Convert to sysbus_realize() etc. with Coccinelle

2020-06-15 22:05:28 +02:00

sifive_e.c

hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004

2020-06-19 08:25:27 -07:00

sifive_gpio.c

hw/riscv: sifive_gpio: Do not blindly trigger output IRQs

2020-06-19 08:25:27 -07:00

sifive_plic.c

sysbus: Convert to sysbus_realize() etc. with Coccinelle

2020-06-15 22:05:28 +02:00

sifive_test.c

sysbus: Convert to sysbus_realize() etc. with Coccinelle

2020-06-15 22:05:28 +02:00

sifive_u_otp.c

qdev: set properties with device_class_set_props()

2020-01-24 20:59:15 +01:00

sifive_u_prci.c

riscv: sifive: Implement PRCI model for FU540

2019-09-17 08:42:47 -07:00

sifive_u.c

riscv/sifive_u: Fix sifive_u_soc_realize() error API violations

2020-07-02 06:25:29 +02:00

sifive_uart.c

chardev: Use QEMUChrEvent enum in IOEventHandler typedef

2020-01-08 11:15:35 +01:00

spike.c

sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1

2020-06-15 22:06:04 +02:00

trace-events

SiFive RISC-V GPIO Device

2019-05-24 11:58:30 -07:00

virt.c

sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1

2020-06-15 22:06:04 +02:00